 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| REJ09B0043-0200H The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 16 H8/3029F-ZTAT TM Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series H8/3029 HD64F3029 Rev. 2.00 Revision date: Jun. 10, 2004 www.renesas.com Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are they are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a pass-through current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed. Preface This LSI is a high performance single-chip microcontroller that integrates peripheral functions necessary for system configuration with an H8/300H CPU featuring a 32-bit internal architecture as its core. In addition, this LSI has an on-chip debugging function using the on-chip debugging emulator (E10T). The E10T emulates a microcontroller and provides functions to support debugging of user programs under the conditions of this LSI being mounted on the user system. Note: * F-ZTATTM is a trademark of Renesas Technology Corp., Ltd. Intended Readership: This manual is intended for users undertaking the design of an application TM system using the H8/3029F-ZTAT . Readers using this manual require a basic knowledge of electrical circuits, logic circuits, and microcomputers. Purpose: The purpose of this manual is to give users an understanding of the TM hardware functions and electrical characteristics of the H8/3029F-ZTAT . Details of execution instructions can be found in the H8/300H Series Programming Manual, which should be read in conjunction with the present manual. Using this Manual: * For an overall understanding of the H8/3029F-ZTAT 's functions Follow the Table of Contents. This manual is broadly divided into sections on the CPU, system control functions, peripheral functions, and electrical characteristics. For a detailed understanding of CPU functions Refer to the separate publication, H8/300H Series Programming Manual. In order to understand the details of a register when its name is known. The addresses, bits, and initial values of the registers are summarized in Appendix B, Internal I/O Registers. The latest information is available at our Web Site. Please make sure that you have the most up-to-date information available. (http:www.renesas.com) TM * Related Material: Rev. 2.0, 06/04, page i of xxiv User's Manual on the H8/3029F-ZTAT : Manual Title H8/3029F-ZTAT TM TM ADE No. Hardware Manual This manual ADE-602-053 H8/300H Series Programming Manual Usr's Manuals for development tools: Manual Title C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual H8S, H8/300 Series Simulator/Debugger User's Manual Renesas Technolgy Embedded Workshop User's Manual H8S, H8/300 Series High-Performance Embedded Workshop, Renesas Technolgy Debegging Interface User's Manual ADE No. ADE-702-247 ADE-702-037 ADE-702-201 ADE-702-231 Application Note: Manual Title H8/300H for CPU Application Note H8/300H On-Chip Supporting Modules Application Note H8/300H Technical Q&A ADE No. ADE-502-033 ADE-502-035 ADE-502-038 Rev. 2.0, 06/04, page ii of xxiv Main Revisions for This Edition Item All Page Revision (See Manual for Details) Product code changed HD64F3029X25HD64F3029TE25 HD64F3029X25WHD64F3029TE25W HD64F3029XBL25HD64F3029TEBL25 1.1 Overview Table 1.1 Features 6 Table amended Regular product code (Internal Product Code) HD64F3029F25 Product Type H8/3029 Product Code (Catalog Product Code) HD64F3029F25 HD64F3029F25W HD64F3029F25W HD64F3029FBL25 HD64F3029FBL25 HD64F3029TE25 HD64F3029X25 HD64F3029TE25W HD64F3029X25W HD64F3029TEBL25 HD64F3029XBL25 12.2.4 Notes on Register Access Writing to RSTCSR Figure12.3 Format of Data Written to RSTCSR 448 Description of RSTOE deleted Rev. 2.0, 06/04, page iii of xxiv Item 18.4.2 Programming/Erasing Interface Register (6) Flash Transfer Destination Address Register (FTDAR) 18.10.1 Serial Communication Interface Specification for Boot Mode * Inquiry and Selection States (2) Device Selection (11) New Bit-Rate Selection Page 596 Revision (See Manual for Details) Table amended Bit 7 TDER 0 1 Description(Return Value after Download) Setting of TDA6 to TDA0 is normal (Initial value) Setting of TDER and TDA6 to TDA0 is H'04 to H'FF and download has been aborted 652 Description amended -- Size (1 byte) : Amount of device-code data This is fixed to 4 657, 658 Description amended --Number of multiplication ratios (1 byte) : The number of multiplication ratios to which the device can be set. Normally the value is two: main operating frequency and peripheral module operating frequency. (Should be set to H'01 for this LSI.) -- Multiplication ratio 2 (1 byte) : The value of multiplication or division ratios for the peripheral frequency -- Multiplication ratio (1 byte) : The value of the multiplication ratio (e.g. when the clock frequency is multiplied by four, the multiplication ratio will be H'04. Cannot be set for this LSI.) * Programming Figure18.27 Programming Sequence (3) 128-byte Programming 663 Figure amended Programming selection (H'42, H'43 ) 664 Description amended -- Programming Address (4 bytes) : Start address for programming Multiple of the size specified in response to the programming unit inquiry (i.e. H'00, H'01, H'00, H'00 : H'00010000) 19.2.2 External Clock Input External Clock Table 19.3 Clock Timing 693 Table amended Item Clock low pulse width Clock high pulse width Test Conditions Figure 21.13 Rev. 2.0, 06/04, page iv of xxiv Item 21.1 Electrical Characteristics of HD64F3029F25, HD64F3029TE25 21.1.2 DC Characteristics Table 21.2 DC Characteristics Page 713 Revision (See Manual for Details) Title amended 715, 716 Table and note amended Item Current 2 dissipation* Normal operation Sleep mode Module standby mode Standby mode Flash memory programming/ 4 erasing* Analog power During A/D supply current conversion During A/D and D/A conversion Idle AICC Symbol ICC* 3 Min -- -- -- -- -- -- Typ 20(3.3V) 17(3.3V) 16(3.3V) 15(3.3V) -- 30(3.3V) Max 38 35 34 70 100 48 Unit mA mA mA A A mA Test Conditions f = 25 MHz f = 25 MHz f = 25 MHz Ta 50C 50C < Ta f = 25 MHz (reference values) -- -- 0.6 0.6 1.5 1.5 mA mA -- -- 0.02(3.3V) 5.0 -- 15 A A Ta 50C at DASTE = 0 50C < Ta at DASTE = 0 Item Reference current During A/D conversion During A/D and D/A conversion Idle RAM standby voltage VCL output Voltage* VCC start Voltage* 6 6 5 Symbol AICC Min -- -- Typ 0.25 1.2 Max 0.8 3.0 Unit mA mA Test Conditions -- VRAM VCL VCC START SVCC 3.0 1.5 -- 0.05 0.02 -- 1.9 0 -- 5.0 -- 2.3 0.8 -- A V V V V/ms DASTE = 0 VCC = 3.3V Ta = 25C Normal operation VCC rise rate* *3 ICC max. (normal operation)= 11 (mA) + 0.13 (mA/(MHz x V)) x VCC x f ICC max. (sleep mode)= 11 (mA) + 0.11 (mA/(MHz x V)) x VCC x f ICC max. (sleep mode + module standby mode) = 11 (mA) + 0.10 (mA/(MHz x V)) x VCC x f Rev. 2.0, 06/04, page v of xxiv Item 21.1.4 A/D Conversion Characteristics Table 21.8 A/D Conversion Characteristics Page 725 Revision (See Manual for Details) Table amended Item Nonlinearity error Conversion time: Offset error 134 states Full-scale error Quantization error Absolute accuracy Item Nonlinearity error Conversion time*: Offset error 70 states Full-scale error Quantization error Absolute accuracy Max 3.5 3.5 3.5 0.5 4.0 Max 7.5 7.5 7.5 0.5 8.0 21.2 Electrical Characteristics of HD64F3029F25W and HD64F3029TE25W 21.2.2 DC Characteristics Table 21.12 DC Characteristics 728 Title amended 730 Table and note amended Item Current 2 dissipation* Normal operation Sleep mode Module standby mode Standby mode Flash memory programming/ 4 erasing* Analog power During A/D supply current conversion During A/D and D/A conversion Idle AICC Symbol ICC* 3 Min -- -- -- -- -- -- Typ 2.0(3.3V) 17(3.3V) 16(3.3V) 15(3.3V) -- 30(3.3V) Max 38 35 34 70 100 48 Unit mA mA mA A A mA Test Conditions f = 25 MHz f = 25 MHz f = 25 MHz Ta 50C 50C < Ta f = 25 MHz (reference values) -- -- 0.6 0.6 1.5 1.5 mA mA -- -- 0.02(3.3V) 5.0 -- 15 A A Ta 50C at DASTE = 0 50C < Ta at DASTE = 0 Rev. 2.0, 06/04, page vi of xxiv Item 21.2.2 DC Characteristics Table 21.12 DC Characteristics Page 731 Revision (See Manual for Details) Table and note amended Item Reference current During A/D conversion During A/D and D/A conversion Idle RAM standby voltage VCL output Voltage*5 VCC start Voltage*6 VCC rise rate*6 Normal operation Symbol AICC Min -- -- Typ 0.25 1.2 Max 0.8 3.0 Unit mA mA -- VRAM VCL VCC START SVCC 3.0 1.5 -- 0.05 0.02 -- 1.9 0 -- 5.0 -- 2.3 0.8 -- A V V V V/ms *3 ICC max. (normal operation)= 11 (mA) + 0.13 (mA/(MHz x V)) x VCC x f ICC max. (sleep mode)= 11 (mA) + 0.11 (mA/(MHz x V)) x VCC x f ICC max. (sleep mode + module standby mode) = 11 (mA) + 0.10 (mA/(MHz x V)) x VCC x f 21.2.4 A/D Conversion Characteristics Table 21.18 A/D Conversion Characteristics 740 Table amended Item Nonlinearity error Conversion time: Offset error 134 states Full-scale error Quantization error Absolute accuracy Item Nonlinearity error Conversion time*: Offset error 70 states Full-scale error Quantization error Absolute accuracy Max 3.5 3.5 3.5 0.5 4.0 Max 7.5 7.5 7.5 0.5 8.0 21.3 Electrical Characteristics of HD64F3029FBL25 and HD64F3029TEBL25 743 Title amended Rev. 2.0, 06/04, page vii of xxiv Item 21.3.2 DC Characteristics Table 21.22 DC Characteristics Page 745, 746 Revision (See Manual for Details) Table and note amended Item Current 2 dissipation* Normal operation Sleep mode Module standby mode Flash memory programming/ 4 erasing* Analog power During A/D supply current conversion During A/D and D/A conversion AICC Symbol ICC* 3 Min -- -- -- -- Typ 20(3.3V) 17(3.3V) 16(3.3V) 30(3.3V) Max 38 35 34 48 Unit mA mA mA mA Test Conditions f = 25 MHz f = 25 MHz f = 25 MHz f = 25 MHz (reference values) -- -- 0.6 0.6 1.5 1.5 mA mA Item Reference current During A/D conversion During A/D and D/A conversion RAM standby voltage Symbol AICC Min -- -- Typ 0.25 1.2 -- Max 0.8 3.0 -- VRAM 3.0 *3 ICC max. (normal operation)= 11 (mA) + 0.13 (mA/(MHz x V)) x VCC x f ICC max. (sleep mode)= 11 (mA) + 0.11 (mA/(MHz x V)) x VCC x f ICC max. (sleep mode + module standby mode) = 11 (mA) + 0.10 (mA/(MHz x V)) x VCC x f 21.3.4 A/D Conversion Characteristics Table 21.28 A/D Conversion Characteristics 755 Table amended Item Nonlinearity error Conversion time: Offset error 134 states Full-scale error Quantization error Absolute accuracy Item Nonlinearity error Conversion time*: Offset error 70 states Full-scale error Quantization error Absolute accuracy Max 3.5 3.5 3.5 0.5 4.0 Max 7.5 7.5 7.5 0.5 8.0 Rev. 2.0, 06/04, page viii of xxiv Item B.1 Addresses (EMC=1) Page 807 Revision (See Manual for Details) Bit table amended Address (Low) H'EE0B6 Register Name FTDAR Data Bus Width 8 Bit Names Bit 7 TDER Bit 6 TDA6 Bit 5 TDA5 Bit 4 TDA4 Bit 3 TDA3 Bit 2 TDA2 Bit 1 TDA1 Bit 0 TDA0 B.2 Addresses (EMC=0) 820 Bit table amended Address (Low) H'EE0B6 Register Name FTDAR Data Bus Width 8 Bit Names Bit 7 TDER Bit 6 TDA6 Bit 5 TDA5 Bit 4 TDA4 Bit 3 TDA3 Bit 2 TDA2 Bit 1 TDA1 Bit 0 TDA0 B.3 Functions FTDAR Flash Transfer Destination Address Register F.1 H8/3029F Product Code Lineup 856 Added 969 Table amended Product Code (Catalog Package Code) Regular product code (Internal Product Code) HD64F3029F25 HD64F3029F25W HD64F3029FBL25 HD64F3029X25 HD64F3029X25W Product Type H8/3029 On-chip flash HD64F3029F25 memory HD64F3029F25W HD64F3029FBL25 HD64F3029TE25 HD64F3029TE25W HD64F3029TEBL25W HD64F3029XBL25 Rev. 2.0, 06/04, page ix of xxiv Rev. 2.0, 06/04, page x of xxiv Contents Section 1 Overview............................................................................................1 1.1 1.2 1.3 Overview........................................................................................................................... 1 Block Diagram .................................................................................................................. 7 Pin Description.................................................................................................................. 8 1.3.1 Pin Arrangement .................................................................................................. 8 1.3.2 Pin Functions ....................................................................................................... 9 1.3.3 Pin Assignments in Each Mode ........................................................................... 14 Section 2 CPU....................................................................................................19 2.1 Overview........................................................................................................................... 19 2.1.1 Features................................................................................................................ 19 2.1.2 Differences from H8/300 CPU ............................................................................ 20 CPU Operating Modes ...................................................................................................... 21 Address Space................................................................................................................... 22 Register Configuration...................................................................................................... 23 2.4.1 Overview.............................................................................................................. 23 2.4.2 General Registers ................................................................................................. 24 2.4.3 Control Registers ................................................................................................. 25 2.4.4 Initial CPU Register Values ................................................................................. 26 Data Formats..................................................................................................................... 27 2.5.1 General Register Data Formats ............................................................................ 27 2.5.2 Memory Data Formats ......................................................................................... 29 Instruction Set ................................................................................................................... 30 2.6.1 Instruction Set Overview ..................................................................................... 30 2.6.2 Instructions and Addressing Modes..................................................................... 31 2.6.3 Tables of Instructions Classified by Function...................................................... 32 2.6.4 Basic Instruction Formats .................................................................................... 41 2.6.5 Notes on Use of Bit Manipulation Instructions.................................................... 42 Addressing Modes and Effective Address Calculation..................................................... 44 2.7.1 Addressing Modes ............................................................................................... 44 2.7.2 Effective Address Calculation ............................................................................. 46 Processing States............................................................................................................... 50 2.8.1 Overview.............................................................................................................. 50 2.8.2 Program Execution State...................................................................................... 51 2.8.3 Exception-Handling State .................................................................................... 51 2.8.4 Exception-Handling Sequences ........................................................................... 53 2.8.5 Bus-Released State............................................................................................... 54 2.8.6 Reset State............................................................................................................ 54 2.8.7 Power-Down State ............................................................................................... 54 Rev. 2.0, 06/04, page xi of xxiv 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 Basic Operational Timing ................................................................................................. 55 2.9.1 Overview.............................................................................................................. 55 2.9.2 On-Chip Memory Access Timing........................................................................ 55 2.9.3 On-Chip Supporting Module Access Timing ...................................................... 56 2.9.4 Access to External Address Space ....................................................................... 57 Section 3 MCU Operating Modes .....................................................................59 3.1 Overview........................................................................................................................... 59 3.1.1 Operating Mode Selection ................................................................................... 59 3.1.2 Register Configuration......................................................................................... 60 Mode Control Register (MDCR) ...................................................................................... 61 System Control Register (SYSCR) ................................................................................... 62 Operating Mode Descriptions ........................................................................................... 64 3.4.1 Mode 1 ................................................................................................................. 64 3.4.2 Mode 2 ................................................................................................................. 64 3.4.3 Mode 3 ................................................................................................................. 64 3.4.4 Mode 4 ................................................................................................................. 65 3.4.5 Mode 5 ................................................................................................................. 65 3.4.6 Mode 7 ................................................................................................................. 65 Pin Functions in Each Operating Mode ............................................................................ 66 Memory Map in Each Operating Mode ............................................................................ 67 3.6.1 Note on Reserved Areas....................................................................................... 67 3.2 3.3 3.4 3.5 3.6 Section 4 Exception Handling ...........................................................................73 4.1 Overview........................................................................................................................... 73 4.1.1 Exception Handling Types and Priority............................................................... 73 4.1.2 Exception Handling Operation ............................................................................ 73 4.1.3 Exception Vector Table ....................................................................................... 74 Reset.................................................................................................................................. 76 4.2.1 Overview.............................................................................................................. 76 4.2.2 Reset Sequence .................................................................................................... 76 4.2.3 Interrupts after Reset............................................................................................ 78 Interrupts........................................................................................................................... 79 Trap Instruction................................................................................................................. 80 Stack Status after Exception Handling.............................................................................. 81 Notes on Stack Usage ....................................................................................................... 82 4.2 4.3 4.4 4.5 4.6 Section 5 Interrupt Controller............................................................................85 5.1 Overview........................................................................................................................... 85 5.1.1 Features................................................................................................................ 85 5.1.2 Block Diagram ..................................................................................................... 86 5.1.3 Pin Configuration................................................................................................. 87 5.1.4 Register Configuration......................................................................................... 87 Rev. 2.0, 06/04, page xii of xxiv 5.2 5.3 5.4 5.5 Register Descriptions ........................................................................................................ 88 5.2.1 System Control Register (SYSCR) ...................................................................... 88 5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB)............................................. 89 5.2.3 IRQ Status Register (ISR).................................................................................... 96 5.2.4 IRQ Enable Register (IER) .................................................................................. 97 5.2.5 IRQ Sense Control Register (ISCR) .................................................................... 98 Interrupt Sources............................................................................................................... 99 5.3.1 External Interrupts ............................................................................................... 99 5.3.2 Internal Interrupts ................................................................................................ 100 5.3.3 Interrupt Vector Table ......................................................................................... 100 Interrupt Operation............................................................................................................ 104 5.4.1 Interrupt Handling Process .................................................................................. 104 5.4.2 Interrupt Sequence ............................................................................................... 109 5.4.3 Interrupt Response Time...................................................................................... 110 Usage Notes ...................................................................................................................... 111 5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction...................... 111 5.5.2 Instructions that Inhibit Interrupts ....................................................................... 112 5.5.3 Interrupts during EEPMOV Instruction Execution.............................................. 112 Section 6 Bus Controller....................................................................................113 6.1 Overview........................................................................................................................... 113 6.1.1 Features................................................................................................................ 113 6.1.2 Block Diagram ..................................................................................................... 115 6.1.3 Pin Configuration................................................................................................. 116 6.1.4 Register Configuration......................................................................................... 117 Register Descriptions ........................................................................................................ 118 6.2.1 Bus Width Control Register (ABWCR)............................................................... 118 6.2.2 Access State Control Register (ASTCR) ............................................................. 119 6.2.3 Wait Control Registers H and L (WCRH, WCRL).............................................. 119 6.2.4 Bus Release Control Register (BRCR) ................................................................ 123 6.2.5 Bus Control Register (BCR) ................................................................................ 124 6.2.6 Chip Select Control Register (CSCR).................................................................. 128 6.2.7 DRAM Control Register A (DRCRA) ................................................................. 129 6.2.8 DRAM Control Register B (DRCRB) ................................................................. 131 6.2.9 Refresh Timer Control/Status Register (RTMCSR) ............................................ 133 6.2.10 Refresh Timer Counter (RTCNT)........................................................................ 135 6.2.11 Refresh Time Constant Register (RTCOR) ......................................................... 135 6.2.12 Address Control Register (ADRCR).................................................................... 136 Operation .......................................................................................................................... 137 6.3.1 Area Division ....................................................................................................... 137 6.3.2 Bus Specifications................................................................................................ 139 6.3.3 Memory Interfaces............................................................................................... 140 6.3.4 Chip Select Signals .............................................................................................. 141 Rev. 2.0, 06/04, page xiii of xxiv 6.2 6.3 6.3.5 Address Output Method....................................................................................... 142 Basic Bus Interface ........................................................................................................... 144 6.4.1 Overview.............................................................................................................. 144 6.4.2 Data Size and Data Alignment............................................................................. 144 6.4.3 Valid Strobes....................................................................................................... 145 6.4.4 Memory Areas ..................................................................................................... 146 6.4.5 Basic Bus Control Signal Timing ........................................................................ 148 6.4.6 Wait Control ........................................................................................................ 155 6.5 DRAM Interface ............................................................................................................... 157 6.5.1 Overview.............................................................................................................. 157 6.5.2 DRAM Space and RAS Output Pin Settings ....................................................... 157 6.5.3 Address Multiplexing........................................................................................... 158 6.5.4 Data Bus............................................................................................................... 159 6.5.5 Pins Used for DRAM Interface............................................................................ 159 6.5.6 Basic Timing........................................................................................................ 160 6.5.7 Precharge State Control ....................................................................................... 161 6.5.8 Wait Control ........................................................................................................ 162 6.5.9 Byte Access Control and CAS Output Pin........................................................... 163 6.5.10 Burst Operation.................................................................................................... 165 6.5.11 Refresh Control.................................................................................................... 170 6.5.12 Examples of Use .................................................................................................. 174 6.5.13 Usage Notes ......................................................................................................... 178 6.6 Interval Timer ................................................................................................................... 181 6.6.1 Operation ............................................................................................................. 181 6.7 Interrupt Sources............................................................................................................... 186 6.8 Burst ROM Interface......................................................................................................... 186 6.8.1 Overview.............................................................................................................. 186 6.8.2 Basic Timing........................................................................................................ 186 6.8.3 Wait Control ........................................................................................................ 187 6.9 Idle Cycle .......................................................................................................................... 188 6.9.1 Operation ............................................................................................................. 188 6.9.2 Pin States in Idle Cycle ........................................................................................ 191 6.10 Bus Arbiter........................................................................................................................ 192 6.10.1 Operation ............................................................................................................. 192 6.11 Register and Pin Input Timing .......................................................................................... 195 6.11.1 Register Write Timing ......................................................................................... 195 6.11.2 BREQ Pin Input Timing ...................................................................................... 196 6.4 Section 7 DMA Controller ................................................................................197 7.1 Overview........................................................................................................................... 197 7.1.1 Features................................................................................................................ 197 7.1.2 Block Diagram ..................................................................................................... 198 7.1.3 Functional Overview............................................................................................ 199 Rev. 2.0, 06/04, page xiv of xxiv 7.2 7.3 7.4 7.5 7.6 7.1.4 Input/Output Pins................................................................................................. 200 7.1.5 Register Configuration......................................................................................... 200 Register Descriptions (1) (Short Address Mode) .............................................................. 202 7.2.1 Memory Address Registers (MAR) ..................................................................... 202 7.2.2 I/O Address Registers (IOAR) ............................................................................. 203 7.2.3 Execute Transfer Count Registers (ETCR).......................................................... 203 7.2.4 Data Transfer Control Registers (DTCR) ............................................................ 205 Register Descriptions (2) (Full Address Mode) ................................................................ 208 7.3.1 Memory Address Registers (MAR) ..................................................................... 208 7.3.2 I/O Address Registers (IOAR) ............................................................................. 208 7.3.3 Execute Transfer Count Registers (ETCR).......................................................... 209 7.3.4 Data Transfer Control Registers (DTCR) ............................................................ 211 Operation .......................................................................................................................... 217 7.4.1 Overview.............................................................................................................. 217 7.4.2 I/O Mode.............................................................................................................. 219 7.4.3 Idle Mode............................................................................................................. 221 7.4.4 Repeat Mode ........................................................................................................ 224 7.4.5 Normal Mode....................................................................................................... 227 7.4.6 Block Transfer Mode ........................................................................................... 230 7.4.7 DMAC Activation................................................................................................ 235 7.4.8 DMAC Bus Cycle ................................................................................................ 237 7.4.9 Multiple-Channel Operation ................................................................................ 243 7.4.10 External Bus Requests, DRAM Interface, and DMAC........................................ 244 7.4.11 NMI Interrupts and DMAC ................................................................................. 245 7.4.12 Aborting a DMAC Transfer................................................................................. 246 7.4.13 Exiting Full Address Mode.................................................................................. 247 7.4.14 DMAC States in Reset State, Standby Modes, and Sleep Mode.......................... 248 Interrupts........................................................................................................................... 249 Usage Notes ...................................................................................................................... 250 7.6.1 Note on Word Data Transfer................................................................................ 250 7.6.2 DMAC Self-Access.............................................................................................. 250 7.6.3 Longword Access to Memory Address Registers ................................................ 250 7.6.4 Note on Full Address Mode Setup....................................................................... 250 7.6.5 Note on Activating DMAC by Internal Interrupts ............................................... 251 7.6.6 NMI Interrupts and Block Transfer Mode ........................................................... 252 7.6.7 Memory and I/O Address Register Values .......................................................... 252 7.6.8 Bus Cycle when Transfer is Aborted ................................................................... 253 7.6.9 Transfer Requests by A/D Converter................................................................... 253 Section 8 I/O Ports .............................................................................................255 8.1 8.2 Overview........................................................................................................................... 255 Port 1................................................................................................................................. 258 8.2.1 Overview.............................................................................................................. 258 Rev. 2.0, 06/04, page xv of xxiv 8.2.2 Register Descriptions ........................................................................................... 259 Port 2................................................................................................................................. 261 8.3.1 Overview.............................................................................................................. 261 8.3.2 Register Descriptions ........................................................................................... 262 8.4 Port 3................................................................................................................................. 265 8.4.1 Overview.............................................................................................................. 265 8.4.2 Register Descriptions ........................................................................................... 265 8.5 Port 4................................................................................................................................. 267 8.5.1 Overview.............................................................................................................. 267 8.5.2 Register Descriptions ........................................................................................... 268 8.6 Port 5................................................................................................................................. 271 8.6.1 Overview.............................................................................................................. 271 8.6.2 Register Descriptions ........................................................................................... 271 8.7 Port 6................................................................................................................................. 275 8.7.1 Overview.............................................................................................................. 275 8.7.2 Register Descriptions ........................................................................................... 276 8.8 Port 7................................................................................................................................. 279 8.8.1 Overview.............................................................................................................. 279 8.8.2 Register Description............................................................................................. 280 8.9 Port 8................................................................................................................................. 281 8.9.1 Overview.............................................................................................................. 281 8.9.2 Register Descriptions ........................................................................................... 283 8.10 Port 9................................................................................................................................. 287 8.10.1 Overview.............................................................................................................. 287 8.10.2 Register Descriptions ........................................................................................... 288 8.11 Port A................................................................................................................................ 292 8.11.1 Overview.............................................................................................................. 292 8.11.2 Register Descriptions ........................................................................................... 294 8.12 Port B ................................................................................................................................ 303 8.12.1 Overview.............................................................................................................. 303 8.12.2 Register Descriptions ........................................................................................... 305 8.3 Section 9 16-Bit Timer ......................................................................................313 9.1 Overview........................................................................................................................... 313 9.1.1 Features................................................................................................................ 313 9.1.2 Block Diagrams ................................................................................................... 315 9.1.3 Pin Configuration................................................................................................. 318 9.1.4 Register Configuration......................................................................................... 319 Register Descriptions ........................................................................................................ 320 9.2.1 Timer Start Register (TSTR)................................................................................ 320 9.2.2 Timer Synchro Register (TSNC) ......................................................................... 321 9.2.3 Timer Mode Register (TMDR) ............................................................................ 322 9.2.4 Timer Interrupt Status Register A (TISRA)......................................................... 325 9.2 Rev. 2.0, 06/04, page xvi of xxiv 9.3 9.4 9.5 9.6 9.2.5 Timer Interrupt Status Register B (TISRB) ......................................................... 328 9.2.6 Timer Interrupt Status Register C (TISRC) ......................................................... 331 9.2.7 Timer Counters (16TCNT) .................................................................................. 333 9.2.8 General Registers (GRA, GRB) ........................................................................... 334 9.2.9 Timer Control Registers (16TCR) ....................................................................... 335 9.2.10 Timer I/O Control Register (TIOR) ..................................................................... 337 9.2.11 Timer Output Level Setting Register C (TOLR) ................................................. 339 CPU Interface.................................................................................................................... 341 9.3.1 16-Bit Accessible Registers ................................................................................. 341 9.3.2 8-Bit Accessible Registers ................................................................................... 343 Operation .......................................................................................................................... 344 9.4.1 Overview.............................................................................................................. 344 9.4.2 Basic Functions.................................................................................................... 344 9.4.3 Synchronization ................................................................................................... 352 9.4.4 PWM Mode.......................................................................................................... 354 9.4.5 Phase Counting Mode .......................................................................................... 358 9.4.6 16-Bit Timer Output Timing................................................................................ 360 Interrupts........................................................................................................................... 361 9.5.1 Setting of Status Flags ......................................................................................... 361 9.5.2 Timing of Clearing of Status Flags ...................................................................... 363 9.5.3 Interrupt Sources.................................................................................................. 364 Usage Notes ...................................................................................................................... 365 Section 10 8-Bit Timers .....................................................................................377 10.1 Overview........................................................................................................................... 377 10.1.1 Features................................................................................................................ 377 10.1.2 Block Diagram ..................................................................................................... 379 10.1.3 Pin Configuration................................................................................................. 380 10.1.4 Register Configuration......................................................................................... 381 10.2 Register Descriptions ........................................................................................................ 382 10.2.1 Timer Counters (8TCNT) .................................................................................... 382 10.2.2 Time Constant Registers A (TCORA) ................................................................. 383 10.2.3 Time Constant Registers B (TCORB).................................................................. 384 10.2.4 Timer Control Register (8TCR) ........................................................................... 385 10.2.5 Timer Control/Status Registers (8TCSR) ............................................................ 388 10.3 CPU Interface.................................................................................................................... 393 10.3.1 8-Bit Registers ..................................................................................................... 393 10.4 Operation .......................................................................................................................... 395 10.4.1 8TCNT Count Timing.......................................................................................... 395 10.4.2 Compare Match Timing....................................................................................... 396 10.4.3 Input Capture Signal Timing ............................................................................... 397 10.4.4 Timing of Status Flag Setting .............................................................................. 398 10.4.5 Operation with Cascaded Connection.................................................................. 399 Rev. 2.0, 06/04, page xvii of xxiv 10.4.6 Input Capture Setting ........................................................................................... 402 10.5 Interrupt ............................................................................................................................ 403 10.5.1 Interrupt Sources.................................................................................................. 403 10.5.2 A/D Converter Activation.................................................................................... 404 10.6 8-Bit Timer Application Example..................................................................................... 404 10.7 Usage Notes ...................................................................................................................... 405 10.7.1 Contention between 8TCNT Write and Clear...................................................... 405 10.7.2 Contention between 8TCNT Write and Increment .............................................. 406 10.7.3 Contention between TCOR Write and Compare Match ...................................... 407 10.7.4 Contention between TCOR Read and Input Capture ........................................... 408 10.7.5 Contention between Counter Clearing by Input Capture and Counter Increment ............................................................................................... 409 10.7.6 Contention between TCOR Write and Input Capture .......................................... 410 10.7.7 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode (Cascaded Connection) ........................................................................................ 411 10.7.8 Contention between Compare Matches A and B ................................................. 412 10.7.9 8TCNT Operation and Internal Clock Source Switchover .................................. 412 Section 11 Programmable Timing Pattern Controller (TPC) ............................415 11.1 Overview........................................................................................................................... 415 11.1.1 Features................................................................................................................ 415 11.1.2 Block Diagram ..................................................................................................... 416 11.1.3 TPC Pins .............................................................................................................. 417 11.1.4 Registers............................................................................................................... 418 11.2 Register Descriptions ........................................................................................................ 419 11.2.1 Port A Data Direction Register (PADDR) ........................................................... 419 11.2.2 Port A Data Register (PADR) .............................................................................. 419 11.2.3 Port B Data Direction Register (PBDDR)............................................................ 420 11.2.4 Port B Data Register (PBDR) .............................................................................. 420 11.2.5 Next Data Register A (NDRA) ............................................................................ 421 11.2.6 Next Data Register B (NDRB)............................................................................. 423 11.2.7 Next Data Enable Register A (NDERA).............................................................. 425 11.2.8 Next Data Enable Register B (NDERB) .............................................................. 426 11.2.9 TPC Output Control Register (TPCR) ................................................................. 427 11.2.10 TPC Output Mode Register (TPMR) ................................................................... 430 11.3 Operation .......................................................................................................................... 432 11.3.1 Overview.............................................................................................................. 432 11.3.2 Output Timing...................................................................................................... 433 11.3.3 Normal TPC Output............................................................................................. 434 11.3.4 Non-Overlapping TPC Output............................................................................. 436 11.3.5 TPC Output Triggering by Input Capture ............................................................ 438 11.4 Usage Notes ...................................................................................................................... 439 11.4.1 Operation of TPC Output Pins ............................................................................. 439 Rev. 2.0, 06/04, page xviii of xxiv 11.4.2 Note on Non-Overlapping Output ....................................................................... 439 Section 12 Watchdog Timer ..............................................................................441 12.1 Overview........................................................................................................................... 441 12.1.1 Features................................................................................................................ 441 12.1.2 Block Diagram ..................................................................................................... 442 12.1.3 Register Configuration......................................................................................... 442 12.2 Register Descriptions ........................................................................................................ 443 12.2.1 Timer Counter (TCNT)........................................................................................ 443 12.2.2 Timer Control/Status Register (TCSR) ................................................................ 444 12.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 446 12.2.4 Notes on Register Access..................................................................................... 447 12.3 Operation .......................................................................................................................... 449 12.3.1 Watchdog Timer Operation ................................................................................. 449 12.3.2 Interval Timer Operation ..................................................................................... 450 12.3.3 Timing of Setting of Overflow Flag (OVF)......................................................... 451 12.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) .................................. 452 12.4 Interrupts........................................................................................................................... 453 12.5 Usage Notes ...................................................................................................................... 453 Section 13 Serial Communication Interface ......................................................455 13.1 Overview........................................................................................................................... 455 13.1.1 Features................................................................................................................ 455 13.1.2 Block Diagram ..................................................................................................... 457 13.1.3 Input/Output Pins................................................................................................. 458 13.1.4 Register Configuration......................................................................................... 459 13.2 Register Descriptions ........................................................................................................ 460 13.2.1 Receive Shift Register (RSR)............................................................................... 460 13.2.2 Receive Data Register (RDR) .............................................................................. 460 13.2.3 Transmit Shift Register (TSR) ............................................................................. 461 13.2.4 Transmit Data Register (TDR)............................................................................. 461 13.2.5 Serial Mode Register (SMR)................................................................................ 462 13.2.6 Serial Control Register (SCR).............................................................................. 466 13.2.7 Serial Status Register (SSR)................................................................................. 471 13.2.8 Bit Rate Register (BRR)....................................................................................... 476 13.3 Operation .......................................................................................................................... 483 13.3.1 Overview.............................................................................................................. 483 13.3.2 Operation in Asynchronous Mode ....................................................................... 485 13.3.3 Multiprocessor Communication........................................................................... 495 13.3.4 Synchronous Operation........................................................................................ 501 13.4 SCI Interrupts.................................................................................................................... 510 13.5 Usage Notes ...................................................................................................................... 510 13.5.1 Notes on Use of SCI ............................................................................................ 510 Rev. 2.0, 06/04, page xix of xxiv Section 14 Smart Card Interface........................................................................517 14.1 Overview........................................................................................................................... 517 14.1.1 Features................................................................................................................ 517 14.1.2 Block Diagram ..................................................................................................... 518 14.1.3 Pin Configuration................................................................................................. 518 14.1.4 Register Configuration......................................................................................... 519 14.2 Register Descriptions ........................................................................................................ 520 14.2.1 Smart Card Mode Register (SCMR) .................................................................... 520 14.2.2 Serial Status Register (SSR)................................................................................. 521 14.2.3 Serial Mode Register (SMR)................................................................................ 523 14.2.4 Serial Control Register (SCR).............................................................................. 524 14.3 Operation .......................................................................................................................... 524 14.3.1 Overview.............................................................................................................. 524 14.3.2 Pin Connections ................................................................................................... 525 14.3.3 Data Format ......................................................................................................... 526 14.3.4 Register Settings .................................................................................................. 527 14.3.5 Clock.................................................................................................................... 529 14.3.6 Transmitting and Receiving Data ........................................................................ 531 14.4 Usage Notes ...................................................................................................................... 539 Section 15 A/D Converter .................................................................................543 15.1 Overview........................................................................................................................... 543 15.1.1 Features................................................................................................................ 543 15.1.2 Block Diagram ..................................................................................................... 544 15.1.3 Input Pins ............................................................................................................. 545 15.1.4 Register Configuration......................................................................................... 546 15.2 Register Descriptions ........................................................................................................ 547 15.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 547 15.2.2 A/D Control/Status Register (ADCSR)................................................................ 548 15.2.3 A/D Control Register (ADCR)............................................................................. 551 15.3 CPU Interface.................................................................................................................... 552 15.4 Operation .......................................................................................................................... 553 15.4.1 Single Mode (SCAN = 0) .................................................................................... 553 15.4.2 Scan Mode (SCAN = 1)....................................................................................... 555 15.4.3 Input Sampling and A/D Conversion Time ......................................................... 557 15.4.4 External Trigger Input Timing............................................................................. 558 15.5 Interrupts........................................................................................................................... 559 15.6 Usage Notes ...................................................................................................................... 559 Section 16 D/A Converter .................................................................................565 16.1 Overview........................................................................................................................... 565 16.1.1 Features................................................................................................................ 565 16.1.2 Block Diagram ..................................................................................................... 565 Rev. 2.0, 06/04, page xx of xxiv 16.1.3 Input/Output Pins................................................................................................. 566 16.1.4 Register Configuration......................................................................................... 566 16.2 Register Descriptions ........................................................................................................ 567 16.2.1 D/A Data Registers 0 and 1 (DADR0/1).............................................................. 567 16.2.2 D/A Control Register (DACR)............................................................................. 567 16.2.3 D/A Standby Control Register (DASTCR).......................................................... 569 16.3 Operation .......................................................................................................................... 570 16.4 D/A Output Control .......................................................................................................... 571 Section 17 RAM ................................................................................................573 17.1 Overview........................................................................................................................... 573 17.1.1 Block Diagram ..................................................................................................... 573 17.1.2 Register Configuration......................................................................................... 574 17.2 System Control Register (SYSCR) ................................................................................... 574 17.3 Operation .......................................................................................................................... 575 Section 18 ROM ................................................................................................577 18.1 Features ............................................................................................................................. 577 18.2 Overview........................................................................................................................... 579 18.2.1 Block Diagram ..................................................................................................... 579 18.2.2 Operating Mode ................................................................................................... 580 18.2.3 Mode Comparison................................................................................................ 581 18.2.4 Flash MAT Configuration.................................................................................... 583 18.2.5 Block Division ..................................................................................................... 583 18.2.6 Programming/Erasing Interface ........................................................................... 584 18.3 Pin Configuration.............................................................................................................. 587 18.4 Register Configuration...................................................................................................... 588 18.4.1 Registers............................................................................................................... 588 18.4.2 Programming/Erasing Interface Register............................................................. 591 18.4.3 Programming/Erasing Interface Parameter .......................................................... 597 18.4.4 RAM Control Register (RAMCR) ....................................................................... 608 18.4.5 Flash Vector Address Control Register (FVACR)............................................... 609 18.4.6 Flash Vector Address Data Register (FVADR) ................................................... 611 18.5 On-Board Programming Mode ......................................................................................... 612 18.5.1 Boot Mode ........................................................................................................... 612 18.5.2 User Program Mode............................................................................................. 615 18.5.3 User Boot Mode................................................................................................... 626 18.6 Protection .......................................................................................................................... 630 18.6.1 Hardware Protection ............................................................................................ 630 18.6.2 Software Protection.............................................................................................. 631 18.6.3 Error Protection.................................................................................................... 632 18.7 Flash Memory Emulation in RAM ................................................................................... 634 18.8 Switching between User MAT and User Boot MAT ........................................................ 637 Rev. 2.0, 06/04, page xxi of xxiv 18.8.1 Usage Notes ......................................................................................................... 638 18.9 PROM Mode..................................................................................................................... 639 18.9.1 Pin Arrangement of the Socket Adapter .............................................................. 639 18.9.2 PROM Mode Operation ....................................................................................... 641 18.9.3 Memory-Read Mode............................................................................................ 642 18.9.4 Auto-Program Mode ............................................................................................ 643 18.9.5 Auto-Erase Mode................................................................................................. 643 18.9.6 Status-Read Mode................................................................................................ 644 18.9.7 Status Polling ....................................................................................................... 644 18.9.8 Time Taken in Transition to PROM Mode .......................................................... 645 18.9.9 Notes on Using PROM Mode .............................................................................. 645 18.10 Further Information........................................................................................................... 646 18.10.1 Serial Communication Interface Specification for Boot Mode............................ 646 18.10.2 AC Characteristics and Timing in Writer Mode .................................................. 672 18.10.3 Procedure Program and Storable Area for Programming Data.......................... 678 Section 19 Clock Pulse Generator .....................................................................689 19.1 Overview........................................................................................................................... 689 19.1.1 Block Diagram ..................................................................................................... 689 19.2 Oscillator Circuit............................................................................................................... 690 19.2.1 Connecting a Crystal Resonator........................................................................... 690 19.2.2 External Clock Input............................................................................................ 692 19.3 Duty Adjustment Circuit................................................................................................... 694 19.4 Prescalers .......................................................................................................................... 694 19.5 Frequency Divider ............................................................................................................ 694 19.5.1 Register Configuration......................................................................................... 695 19.5.2 Division Control Register (DIVCR) .................................................................... 695 19.5.3 Usage Notes ......................................................................................................... 696 Section 20 Power-Down State...........................................................................697 20.1 Overview........................................................................................................................... 697 20.2 Register Configuration...................................................................................................... 699 20.2.1 System Control Register (SYSCR) ...................................................................... 699 20.2.2 Module Standby Control Register H (MSTCRH)................................................ 701 20.2.3 Module Standby Control Register L (MSTCRL)................................................. 702 20.3 Sleep Mode ....................................................................................................................... 704 20.3.1 Transition to Sleep Mode..................................................................................... 704 20.3.2 Exit from Sleep Mode.......................................................................................... 704 20.4 Software Standby Mode.................................................................................................... 705 20.4.1 Transition to Software Standby Mode ................................................................. 705 20.4.2 Exit from Software Standby Mode ...................................................................... 705 20.4.3 Selection of Waiting Time for Exit from Software Standby Mode ..................... 706 20.4.4 Sample Application of Software Standby Mode.................................................. 707 Rev. 2.0, 06/04, page xxii of xxiv 20.4.5 Note...................................................................................................................... 707 20.5 Hardware Standby Mode .................................................................................................. 708 20.5.1 Transition to Hardware Standby Mode................................................................ 708 20.5.2 Exit from Hardware Standby Mode..................................................................... 708 20.5.3 Timing for Hardware Standby Mode................................................................... 708 20.5.4 Timing for Hardware Standby Mode at Power-On.............................................. 709 20.6 Module Standby Function................................................................................................. 710 20.6.1 Module Standby Timing ...................................................................................... 710 20.6.2 Read/Write in Module Standby............................................................................ 710 20.6.3 Usage Notes ......................................................................................................... 710 20.7 System Clock Output Disabling Function......................................................................... 711 Section 21 Electrical Characteristics..................................................................713 21.1 Electrical Characteristics of HD64F3029F25 and HD64F3029TE25............................... 713 21.1.1 Absolute Maximum Ratings ................................................................................ 713 21.1.2 DC Characteristics ............................................................................................... 714 21.1.3 AC Characteristics ............................................................................................... 719 21.1.4 A/D Conversion Characteristics........................................................................... 725 21.1.5 D/A Conversion Characteristics........................................................................... 726 21.1.6 Flash Memory Characteristics ............................................................................. 727 21.2 Electrical Characteristics of HD64F3029F25W and HD64F3029TE25W ....................... 728 21.2.1 Absolute Maximum Ratings ................................................................................ 728 21.2.2 DC Characteristics ............................................................................................... 729 21.2.3 AC Characteristics ............................................................................................... 734 21.2.4 A/D Conversion Characteristics........................................................................... 740 21.2.5 D/A Conversion Characteristics........................................................................... 741 21.2.6 Flash Memory Characteristics ............................................................................. 742 21.3 Electrical Characteristics of HD64F3029FBL25 and HD64F3029TEBL25..................... 743 21.3.1 Absolute Maximum Ratings ................................................................................ 743 21.3.2 DC Characteristics ............................................................................................... 744 21.3.3 AC Characteristics ............................................................................................... 749 21.3.4 A/D Conversion Characteristics........................................................................... 755 21.3.5 D/A Conversion Characteristics........................................................................... 756 21.3.6 Flash Memory Characteristics ............................................................................. 757 21.4 Operational Timing ........................................................................................................... 758 21.4.1 Clock Timing ....................................................................................................... 758 21.4.2 Control Signal Timing ......................................................................................... 759 21.4.3 Bus Timing .......................................................................................................... 760 21.4.4 DRAM Interface Bus Timing .............................................................................. 766 21.4.5 TPC and I/O Port Timing..................................................................................... 769 21.4.6 Timer Input/Output Timing ................................................................................. 770 21.4.7 SCI Input/Output Timing..................................................................................... 771 21.4.8 DMAC Timing..................................................................................................... 772 Rev. 2.0, 06/04, page xxiii of xxiv 21.4.9 Input Signal Timing ............................................................................................. 773 Appendix A Instruction Set ...............................................................................775 A.1 A.2 A.3 Instruction List .................................................................................................................. 775 Operation Code Maps ....................................................................................................... 790 Number of States Required for Execution ........................................................................ 793 Appendix B Internal I/O Registers ....................................................................802 B.1 B.2 B.3 Addresses (EMC = 1)........................................................................................................ 802 Addresses (EMC = 0)........................................................................................................ 815 Functions........................................................................................................................... 827 Appendix C I/O Port Block Diagrams...............................................................923 C.1 C.2 C.3 C.4 C.5 C.6 C.7 C.8 C.9 C.10 C.11 Port 1 Block Diagram ....................................................................................................... 923 Port 2 Block Diagram ....................................................................................................... 924 Port 3 Block Diagram ....................................................................................................... 925 Port 4 Block Diagram ....................................................................................................... 926 Port 5 Block Diagram ....................................................................................................... 927 Port 6 Block Diagrams...................................................................................................... 928 Port 7 Block Diagrams...................................................................................................... 935 Port 8 Block Diagrams...................................................................................................... 936 Port 9 Block Diagrams...................................................................................................... 941 Port A Block Diagrams ..................................................................................................... 947 Port B Block Diagrams ..................................................................................................... 950 Appendix D Pin States.......................................................................................958 D.1 D.2 Port States in Each Mode .................................................................................................. 958 Pin States at Reset ............................................................................................................. 965 Appendix E Timing of Transition to and Recovery from Hardware Standby Mode ...............................................................968 Appendix F Product Code Lineup .....................................................................969 F.1 H8/3029 Product Code Lineup ......................................................................................... 969 Appendix G Package Dimensions .....................................................................970 Appendix H Comparison of H8/300H Series Product Specifications ...............972 H.1 H.2 Differences between H8/3029, H8/3069R, H8/3067 Group and H8/3062 Group, H8/3048 Group, H8/3007 and H8/3006, and H8/3002..................................................... 972 Comparison of Pin Functions of 100-Pin Package Products (FP-100B, TFP-100B)....... 976 Rev. 2.0, 06/04, page xxiv of xxiv Section 1 Overview 1.1 Overview The H8/3029 is a series of microcontrollers (MCUs) that integrate system supporting functions together with an H8/300H CPU core having an original Renesas Technology architecture. The H8/3029 is a single-chip microcontroller (MCU) that integrates peripheral functions necessary for system configuration with an H8/300H CPU featuring a 32-bit internal architecture as its core. In addition, this LSI has an on-chip debugging function using the on-chip debugging emulator (E10T). The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address space. Its instruction set is upward-compatible at the object-code level with the H8/300 CPU, enabling easy porting of software from the H8/300 Series. The on-chip system supporting functions include ROM, RAM, a 16-bit timer, an 8-bit timer, a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication interface (SCI), an A/D converter, a D/A converter, I/O ports, a direct memory access controller (DMAC), and other facilities. The H8/3029 has 512 kbytes of flash memory and 16 kbytes of RAM. Six MCU operating modes offer a choice of bus width and address space size. The modes (modes 1 to 5, 7) include one single-chip mode and five expanded modes. The H8/3029 includes an F-ZTATTM* version with on-chip flash memory that can be programmed on-board. This version enables users to respond quickly and flexibly to changing application specifications, growing production volumes, and other conditions. The E10T emulates a microcontroller and provides functions to support debugging of user programs under the conditions of this LSI being mounted on the user system. Table 1.1 summarizes the features of the H8/3029. Note: * F-ZTATTM (Flexible ZTAT) is a trademark of Renesas Technology Corp. Rev. 2.0, 06/04, page 1 of 980 Notes on using the on-chip debugging functions incorporated in the H8/3029 The following must be noted when developing and debugging H8/3029 programs using the onchip debugging function. 1. The on-chip emulator supports only the development and debugging of programs on the onchip flash memory. The on-chip emulator cannot emulate external memory or when the LSI is in ROM-disabled modes. 2. Since the DRAM interface and DMAC does not operate, do not set the registers for these modules. 3. In the break mode of on-chip emulation, the watchdog timer (WDT) stops counting. Therefore, the WDT count will be different from the expected value after leaving break mode. 4. The FWE (BRK), P91, P93, and P95 pins are specifically used by the E10T and cannot be used by the user. 5. In the 16-Mbyte address mode, address area from H'FF7000 to H'FF7FFF is used by the E10T and cannot be used by the user. 6. Emulation of hardware standby mode can not be performed. Rev. 2.0, 06/04, page 2 of 980 Table 1.1 Feature CPU Features Description Upward-compatible with the H8/300 CPU at the object-code level General-register machine * Sixteen 16-bit general registers (also usable as sixteen 8-bit registers, eight 16-bit registers, or eight 32-bit registers) Maximum clock rate: 25 MHz Add/subtract: 80 ns Multiply/divide: 560 ns High-speed operation * * * 16-Mbyte address space Instruction features * * * * * Memory 8/16/32-bit data transfer, arithmetic, and logic instructions Signed and unsigned multiply instructions (8 bits x 8 bits, 16 bits x 16 bits) Signed and unsigned divide instructions (16 bits / 8 bits, 32 bits / 16 bits) Bit accumulator function Bit manipulation instructions with register-indirect specification of bit positions ROM: 512 kbytes RAM: 16 kbytes Seven external interrupt pins: NMI, IRQ0 to IRQ5 36 internal interrupts Three selectable interrupt priority levels Address space can be partitioned into eight areas, with independent bus specifications in each area Chip select output available for areas 0 to 7 8-bit access or 16-bit access selectable for each area Two-state or three-state access selectable for each area Selection of two wait modes Number of program wait states selectable for each area Direct connection of burst ROM Direct connection of up to 8-Mbyte DRAM (or DRAM interface can be used as interval timer) Bus arbitration function H8/3029 * * Interrupt controller Bus controller * * * * * * * * * * * * Rev. 2.0, 06/04, page 3 of 980 Feature DMA controller (DMAC) Description Short address mode * * * Maximum four channels available Selection of I/O mode, idle mode, or repeat mode Can be activated by compare match/input capture A interrupts from 16-bit timer channels 0 to 2, conversion-end interrupts from the A/D converter, transmit-data-empty and receive-data-full interrupts from the SCI, or external requests Maximum two channels available Selection of normal mode or block transfer mode Can be activated by compare match/input capture A interrupts from 16-bit timer channels 0 to 2, conversion-end interrupts from the A/D converter, external requests, or auto-request Three 16-bit timer channels, capable of processing up to six pulse outputs or six pulse inputs 16-bit timer counter (channels 0 to 2) Two multiplexed output compare/input capture pins (channels 0 to 2) Operation can be synchronized (channels 0 to 2) PWM mode available (channels 0 to 2) Phase counting mode available (channel 2) DMAC can be activated by compare match/input capture A interrupts (channels 0 to 2) 8-bit up-counter (external event count capability) Two time constant registers Two channels can be connected Maximum 16-bit pulse output, using 16-bit timer as time base Up to four 4-bit pulse output groups (or one 16-bit group, or two 8-bit groups) Non-overlap mode available Output data can be transferred by DMAC Reset signal can be generated by overflow Usable as an interval timer Selection of asynchronous or synchronous mode Full duplex: can transmit and receive simultaneously On-chip baud-rate generator Smart card interface functions added Full address mode * * * 16-bit timer, 3 channels * * * * * * * 8-bit timer, 4 channels * * * * * * * Programmable timing pattern controller (TPC) Watchdog timer (WDT), 1 channel Serial communication interface (SCI), 3 channels * * * * * * Rev. 2.0, 06/04, page 4 of 980 Feature A/D converter Description * * * * * * Resolution: 10 bits Eight channels, with selection of single or scan mode Variable analog conversion voltage range Sample-and-hold function A/D conversion can be started by an external trigger or 8-bit timer comparematch DMAC can be activated by an A/D conversion end interrupt Resolution: 8 bits Two channels D/A outputs can be sustained in software standby mode 70 input/output pins 9 input-only pins Six MCU operating modes Mode Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 7 Address Space 1 Mbyte 1 Mbyte 16 Mbytes 16 Mbytes 16 Mbytes 1 Mbyte Address Pins A19 to A0 A19 to A0 A23 to A0 A23 to A0 A23 to A0 -- Initial Bus Width 8 bits 16 bits 8 bits 16 bits 8 bits -- Max. Bus Width 16 bits 16 bits 16 bits 16 bits 16 bits -- D/A converter * * * I/O ports * * Operating modes * * Power-down state * * * * * Other features * On-chip ROM is disabled in modes 1 to 4 Sleep mode Software standby mode Hardware standby mode Module standby function Programmable system clock frequency division On-chip clock pulse generator Rev. 2.0, 06/04, page 5 of 980 Feature Product lineup Description Product Code (Catalog Product Code) HD64F3029F25 Regular product code (Internal Product Code) HD64F3029F25 Package (Renesas Package Code) Classification 100-pin QFP (FP-100B) Product Type H8/3029 Regular specifications with on-chip flash memory Wide-range specifications with on-chip flash memory Standard characteristic specifications with on-chip flash memory HD64F3029F25W HD64F3029F25W HD64F3029FBL25 HD64F3029FBL25 HD64F3029TE25 HD64F3029X25 100-pin TQFP (TFP-100B) Regular specifications with on-chip flash memory Wide-range specifications with on-chip flash memory Standard characteristic specifications with on-chip flash memory HD64F3029TE25W HD64F3029X25W HD64F3029TEBL25 HD64F3029XBL25 Rev. 2.0, 06/04, page 6 of 980 1.2 Block Diagram Figure 1.1 shows an internal block diagram. P37 /D15 P36 /D14 P35 /D13 P34 /D12 P33 /D11 P32 /D10 P31 /D9 P30 /D8 P47 /D7 P46 /D6 P45 /D5 P44 /D4 P43 /D3 P42 /D2 P41 /D1 P40 /D0 VCC VCC VSS VSS VSS VSS VSS VSS VCL Port 3 Address bus Port 4 P53 /A 19 Port 5 Port 2 Bus controller Port 1 Port 9 MD2 MD1 MD0 EXTAL XTAL STBY RES FWE NMI /P67 LWR/P66 HWR/P65 RD/P64 AS/P63 BACK/P62 BREQ/P61 WAIT/P60 RAM CS0/P84 CS2/IRQ2/P82 CS3/IRQ1/P81 RFSH/IRQ0/P80 Port 8 Port 6 Clock pulse generator Data bus (upper) Data bus (lower) P52 /A 18 P51 /A 17 P50 /A 16 P27 /A 15 H8/300H CPU P26 /A 14 P25 /A 13 P24 /A 12 P23 /A 11 P22 /A 10 P21 /A 9 P20 /A 8 P17 /A 7 P16 /A 6 P15 /A 5 P14 /A 4 P13 /A 3 P12 /A 2 P11 /A 1 Watchdog timer (WDT) P10 /A 0 Interrupt controller DMA controller (DMAC) ROM (flash memory) ADTRG/CS1/IRQ3/P83 16-bit timer unit Serial communication interface (SCI) x 3 channels P95 /SCK 1 /IRQ 5 Programmable timing pattern controller (TPC) A/D converter D/A converter P94 /SCK 0 /IRQ 4 P93 /RxD1 P92 /RxD0 P91 /TxD 1 P90 /TxD 0 8-bit timer unit Port B CS6/DREQ0/TMIO1/TP9/PB1 CS4/DREQ1/TMIO3/TP11/PB3 SCK2/LCAS/TP13/PB5 CS7/TMO0/TP8/PB0 UCAS/TP12/PB4 A20/TIOCB2/TP7/PA7 A21/TIOCA2/TP6/PA6 A22/TIOCB1/TP5/PA5 CS5/TMO2/TP10/PB2 RxD2/TP15/PB7 TxD2/TP14/PB6 Port A AVCC TCLKD/TIOCB0/TP3/PA3 TCLKC/TIOCA0/TP2/PA2 TEND1/TCLKB/TP1/PA1 TEND0/TCLKA/TP0/PA0 A23/TIOCA1/TP4/PA4 AVSS VREF DA1/AN7/P77 DA0/AN6/P76 AN5/P75 Port 7 AN4/P74 AN3/P73 AN2/P72 AN1/P71 AN0/P70 Figure 1.1 Block Diagram Rev. 2.0, 06/04, page 7 of 980 1.3 1.3.1 Pin Description Pin Arrangement The pin arrangement of the H8/3029 FP-100B and TFP-100B packages is shown in figure 1.2. P61 /BREQ P62 /BACK P60 /WAIT P65 /HWR P66 /LWR P53 /A 19 P52 /A 18 P51 /A 17 P50 /A 16 53 P27 /A 15 52 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 AVCC VREF AN0/P70 AN1/P71 AN2/P72 AN3/P73 AN4/P74 AN5/P75 AN6/DA0/P76 AN7/DA1/P77 AVSS IRQ0/RFSH/P80 IRQ1/CS3/P81 IRQ2/CS2/P82 IRQ3/CS1/ADTRG/P83 CS0/P84 VSS TP0/TCLKA/TEND0/PA0 TP1/TCLKB/TEND1/PA1 TP2/TIOCA0/TCLKC/PA2 TP3/TIOCB0/TCLKD/PA3 TP4/TIOCA1/A23/PA4 TP5/TIOCB1/A22/PA5 TP6/TIOCA2/A21/PA6 TP7/TIOCB2/A20/PA7 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Top view (FP-100B, TFP-100B) 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 P26 /A 14 P64 /RD P63 /AS EXTAL STBY P67/ XTAL RES MD2 MD1 MD0 VCC NMI VSS VSS P25/A13 P24/A12 P23/A11 P22/A10 P21/A9 P20/A8 VSS P17/A7 P16/A6 P15/A5 P14/A4 P13/A3 P12/A2 P11/A1 P10/A0 VCC P37/D15 P36/D14 P35/D13 P34/D12 P33/D11 P32/D10 P31/D9 P30/D8 P47/D7 10 12 13 14 15 16 17 18 19 20 21 22 23 D4 /P44 24 D5 /P45 VCL* TxD0 /P90 TxD1 /P91 RxD0 /P92 RxD1 /P93 IRQ4 /SCK0 /P94 IRQ5 /SCK1 /P95 D0 /P40 D1 /P41 D2 /P42 CS7/TMO0/TP8/PB0 CS6/DREQ0/TMIO1/TP9/PB1 CS5/TMO2/TP10/PB2 CS4/DREQ1/TMIO3/TP11/PB3 UCAS/TP12/PB4 SCK2/LCAS/TP13/PB5 TxD2/TP14/PB6 RxD2/TP15/PB7 D3 /P43 VSS D6 /P46 1 0.1 F Note: * When functioning as VCL pin, the connection of an external capacitor is required. Figure 1.2 Pin Arrangement (FP-100B or TFP-100B, Top View) Rev. 2.0, 06/04, page 8 of 980 FWE VSS 25 11 1 2 3 4 5 6 7 8 9 1.3.2 Pin Functions Table 1.2 summarizes the pin functions. Table 1.2 Pin Functions Pin No. Type Power Symbol VCC VSS Internal step-down pin VCL FP-100B TFP-100B I/O 35, 68 Input Name and Function Power: For connection to the power supply. Connect all VCC pins to the system power supply. Ground: For connection to ground (0 V). Connect all VSS pins to the 0-V system power supply. 11, 22, 44, Input 57, 65, 92 1 Output Connect an external capacitor between this pin and GND (0 V). Do not connect to VCC. VCL 0.1 F Clock XTAL 67 Input For connection to a crystal resonator. For examples of crystal resonator and external clock input, see section 19, Clock Pulse Generator. For connection to a crystal resonator or input of an external clock signal. For examples of crystal resonator and external clock input, see section 19, Clock Pulse Generator. EXTAL 66 Input 61 Output System clock: Supplies the system clock to external devices. Rev. 2.0, 06/04, page 9 of 980 Pin No. Type Operating mode control Symbol MD2 to MD0 FP-100B TFP-100B I/O 75 to 73 Input Name and Function Mode 2 to mode 0: For setting the operating mode, as follows. The H8/3029 can be used only in modes 1 to 5, 7. The inputs at the mode pins must select one of these six modes. Inputs at these pins must not be changed during operation. MD2 0 0 0 0 1 1 1 1 MD1 0 0 1 1 0 0 1 1 MD0 0 1 0 1 0 1 0 1 Operating Mode -- Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 -- Mode 7 System control RES FWE STBY BREQ BACK 63 10 62 59 60 64 17, 16, 90 to 87 97 to 100, 56 to 45, 43 to 36 Input Input Input Input Reset input: When driven low, this pin resets the chip Write enable signal: Flash memory write control signal Standby: When driven low, this pin forces a transition to hardware standby mode Bus request: Used by an external bus master to request the bus right Output Bus request acknowledge: Indicates that the bus has been granted to an external bus master Input Input Nonmaskable interrupt: Requests a nonmaskable interrupt Interrupt request 5 to 0: Maskable interrupt request pins Interrupts NMI IRQ5 to IRQ0 Address bus A23 to A0 Output Address bus: Outputs address signals Rev. 2.0, 06/04, page 10 of 980 Pin No. Type Data bus Symbol D15 to D0 FP-100B TFP-100B I/O 34 to 23, 21 to 18 2 to 5, 88 to 91 69 70 71 Input/ output Name and Function Data bus: Bidirectional data bus Bus control CS7 to CS0 AS RD HWR Output Chip select: Select signals for areas 7 to 0 Output Address strobe: Goes low to indicate valid address output on the address bus Output Read: Goes low to indicate reading from the external address space Output High write: Goes low to indicate writing to the external address space; indicates valid data on the upper data bus (D15 to D8). Output Low write: Goes low to indicate writing to the external address space; indicates valid data on the lower data bus (D7 to D0). Input Wait: Requests insertion of wait states in bus cycles during access to the external address space LWR 72 WAIT DRAM interface RFSH CS2 to CS5 RD HWR UCAS LWR LCAS DMA controller (DMAC) DREQ1, DREQ0 TEND1, TEND0 58 87 89, 88, 5, 4 70 71 6 72 7 5, 3 94, 93 Output Refresh: Indicates a refresh cycle Output Row address strobe RAS Row address strobe RAS: signal for DRAM Output Write enable WE Write enable signal for DRAM WE: Output Upper column address strobe UCAS Column UCAS: address strobe signal for DRAM Output Lower column address strobe LCAS Column LCAS: address strobe signal for DRAM Input DMA request 1 and 0: DMAC activation requests Output Transfer end 1 and 0: These signals indicate that the DMAC has ended a data transfer Rev. 2.0, 06/04, page 11 of 980 Pin No. Type Symbol FP-100B TFP-100B I/O Input Input/ output Input/ output Name and Function Clock input D to A: External clock inputs Input capture/output compare A2 to A0: GRA2 to GRA0 output compare or input capture, or PWM output Input capture/output compare B2 to B0: GRB2 to GRB0 output compare or input capture, or PWM output 16-bit timer TCLKD to 96 to 93 TCLKA TIOCA2 to 99, 97, 95 TIOCA0 TIOCB2 to 100, 98, 96 TIOCB0 8-bit timer TMO0, TMO2 TMIO1, TMIO3 2, 4 3, 5 Output Compare match output: Compare match output pins Input/ output Input Input capture input/compare match output: Input capture input or compare match output pins Counter external clock input: These pins input an external clock to the counters. TCLKD to 96 to 93 TCLKA Programmable timing pattern controller (TPC) Serial communication interface (SCI) TP15 to TP0 9 to 2, 100 to 93 Output TPC output 15 to 0: Pulse output TxD2 to TxD0 RxD2 to RxD0 SCK2 to SCK0 8, 13, 12 9, 15, 14 7, 17, 16 85 to 78 90 85, 84 Output Transmit data (channels 0, 1, 2): SCI data output Input Input/ output Input Input Receive data (channels 0, 1, 2): SCI data input Serial clock (channels 0, 1, 2): SCI clock input/output Analog 7 to 0: Analog input pins A/D conversion external trigger input: External trigger input for starting A/D conversion A/D converter AN7 to AN0 ADTRG D/A converter DA1, DA0 Output Analog output: Analog output from the D/A converter Rev. 2.0, 06/04, page 12 of 980 Pin No. Type A/D and D/A converters Symbol AVCC FP-100B TFP-100B I/O 76 Input Name and Function Power supply pin for the A/D and D/A converters. Connect to the system power supply when not using the A/D and D/A converters. Ground pin for the A/D and D/A converters. Connect to system ground (0 V). Reference voltage input pin for the A/D and D/A converters. Connect to the system power supply when not using the A/D and D/A converters. Port 1: Eight input/output pins. The direction of each pin can be selected in the port 1 data direction register (P1DDR). Port 2: Eight input/output pins. The direction of each pin can be selected in the port 2 data direction register (P2DDR). Port 3: Eight input/output pins. The direction of each pin can be selected in the port 3 data direction register (P3DDR). Port 4: Eight input/output pins. The direction of each pin can be selected in the port 4 data direction register (P4DDR). Port 5: Four input/output pins. The direction of each pin can be selected in the port 5 data direction register (P5DDR). Port 6: Seven input/output pins and one input pin. The direction of each pin can be selected in the port 6 data direction register (P6DDR). Port 7: Eight input pins Port 8: Five input/output pins. The direction of each pin can be selected in the port 8 data direction register (P8DDR). Port 9: Six input/output pins. The direction of each pin can be selected in the port 9 data direction register (P9DDR). Port A: Eight input/output pins. The direction of each pin can be selected in the port A data direction register (PADDR). Port B: Eight input/output pins. The direction of each pin can be selected in the port B data direction register (PBDDR). AVSS VREF 86 77 Input Input I/O ports P17 to P10 43 to 36 Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input Input/ output Input/ output Input/ output Input/ output P27 to P20 52 to 45 P37 to P30 34 to 27 P47 to P40 26 to 23, 21 to 18 P53 to P50 56 to 53 P67 to P60 61, 72 to 69, 60 to 58 P77 to P70 85 to 78 P84 to P80 91 to 87 P95 to P90 17 to 12 PA7 to PA0 100 to 93 PB7 to PB0 9 to 2 Rev. 2.0, 06/04, page 13 of 980 1.3.3 Pin Assignments in Each Mode Table 1.3 lists the pin assignments in each mode. Table 1.3 Pin No. FP-100B TFP-100B 1 2 3 Mode 1 VCL PB0/TP8/ TMO0/CS7 PB1/TP9/ TMIO1/ DREQ0/ CS6 PB2/TP10/ TMO2/CS5 PB3/TP11/ TMIO3/ DREQ1/ CS4 PB4/TP12/ UCAS PB5/TP13/ LCAS/ SCK2 PB6/TP14/ TxD2 PB7/TP15/ RxD2 FWE VSS P90/TxD0 P91/TxD1 P92/RxD0 P93/RxD1 P94/IRQ4/ SCK0 P95/IRQ5/ SCK1 P40/D0*1 P41/D1* 1 Pin Assignments in Each Mode (FP-100B or TFP-100B) Pin Name Mode 2 VCL PB0/TP8/ TMO0/CS7 PB1/TP9/ TMIO1/ DREQ0/ CS6 PB2/TP10/ TMO2/CS5 PB3/TP11/ TMIO3/ DREQ1/ CS4 PB4/TP12/ UCAS PB5/TP13/ LCAS/ SCK2 PB6/TP14/ TxD2 PB7/TP15/ RxD2 FWE VSS P90/TxD0 P91/TxD1 P92/RxD0 P93/RxD1 P94/IRQ4/ SCK0 P95/IRQ5/ SCK1 P40/D0*2 P41/D1* 2 Mode 3 VCL PB0/TP8/ TMO0/CS7 PB1/TP9/ TMIO1/ DREQ0/ CS6 PB2/TP10/ TMO2/CS5 PB3/TP11/ TMIO3/ DREQ1/ CS4 PB4/TP12/ UCAS PB5/TP13/ LCAS/ SCK2 PB6/TP14/ TxD2 PB7/TP15/ RxD2 FWE VSS P90/TxD0 P91/TxD1 P92/RxD0 P93/RxD1 P94/IRQ4/ SCK0 P95/IRQ5/ SCK1 P40/D0*1 P41/D1* 1 Mode 4 VCL PB0/TP8/ TMO0/CS7 PB1/TP9/ TMIO1/ DREQ0/ CS6 PB2/TP10/ TMO2/CS5 PB3/TP11/ TMIO3/ DREQ1/ CS4 PB4/TP12/ UCAS PB5/TP13/ LCAS/ SCK2 PB6/TP14/ TxD2 PB7/TP15/ RxD2 FWE VSS P90/TxD0 P91/TxD1 P92/RxD0 P93/RxD1 P94/IRQ4/ SCK0 P95/IRQ5/ SCK1 P40/D0*2 P41/D1* 2 Mode 5 VCL PB0/TP8/ TMO0/CS7 PB1/TP9/ TMIO1/ DREQ0/ CS6 PB2/TP10/ TMO2/CS5 PB3/TP11/ TMIO3/ DREQ1/ CS4 PB4/TP12/ UCAS PB5/TP13/ LCAS/ SCK2 PB6/TP14/ TxD2 PB7/TP15/ RxD2 FWE VSS P90/TxD0 P91/TxD1 P92/RxD0 P93/RxD1 P94/IRQ4/ SCK0 P95/IRQ5/ SCK1 P40/D0*1 P41/D1* 1 Mode 7 VCL PB0/TP8/ TMO0 PB1/TP9/ TMIO1/ DREQ0 PB2/TP10/ TMO2 PB3/TP11/ TMIO3/ DREQ1 PB4/TP12 PB5/TP13/ SCK2 PB6/TP14/ TxD2 PB7/TP15/ RxD2 FWE VSS P90/TxD0 P91/TxD1 P92/RxD0 P93/RxD1 P94/IRQ4/ SCK0 P95/IRQ5/ SCK1 P40 P41 P42 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 P42/D2*1 P42/D2*2 P42/D2*1 P42/D2*2 P42/D2*1 Rev. 2.0, 06/04, page 14 of 980 Pin No. FP-100B TFP-100B Mode 1 P43/D3*1 VSS P44/D4*1 P45/D5* P47/D7* D8 D9 D10 D11 D12 D13 D14 D15 VCC A0 A1 A2 A3 A4 A5 A6 A7 VSS A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 1 Pin Name Mode 2 P43/D3*2 VSS P44/D4*2 P45/D5* P47/D7* D8 D9 D10 D11 D12 D13 D14 D15 VCC A0 A1 A2 A3 A4 A5 A6 A7 VSS A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 2 Mode 3 P43/D3*1 VSS P44/D4*1 P45/D5* P47/D7* D8 D9 D10 D11 D12 D13 D14 D15 VCC A0 A1 A2 A3 A4 A5 A6 A7 VSS A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 1 Mode 4 P43/D3*2 VSS P44/D4*2 P45/D5* P47/D7* D8 D9 D10 D11 D12 D13 D14 D15 VCC A0 A1 A2 A3 A4 A5 A6 A7 VSS A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 2 Mode 5 P43/D3*1 VSS P44/D4*1 P45/D5* P47/D7* D8 D9 D10 D11 D12 D13 D14 D15 VCC P10/A0 P11/A1 P12/A2 P13/A3 P14/A4 P15/A5 P16/A6 P17/A7 VSS P20/A8 P21/A9 P22/A10 P23/A11 P24/A12 P25/A13 P26/A14 P27/A15 P50/A16 P51/A17 1 Mode 7 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 P43 VSS P44 P45 P46 P47 P30 P31 P32 P33 P34 P35 P36 P37 VCC P10 P11 P12 P13 P14 P15 P16 P17 VSS P20 P21 P22 P23 P24 P25 P26 P27 P50 P51 P46/D6*1 1 P46/D6*2 2 P46/D6*1 1 P46/D6*2 2 P46/D6*1 1 Rev. 2.0, 06/04, page 15 of 980 Pin No. FP-100B TFP-100B 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 Mode 1 A18 A19 VSS P60/WAIT P61/BREQ P62/BACK P67/*3 STBY RES NMI VSS EXTAL XTAL VCC AS RD HWR LWR MD0 MD1 MD2 AVCC VREF P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/ DA0 P77/AN7/ DA1 AVSS Mode 2 A18 A19 VSS P60/WAIT P61/BREQ P62/BACK P67/*3 STBY RES NMI VSS EXTAL XTAL VCC AS RD HWR LWR MD0 MD1 MD2 AVCC VREF P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/ DA0 P77/AN7/ DA1 AVSS Mode 3 A18 A19 VSS P60/WAIT Pin Name Mode 4 A18 A19 VSS P60/WAIT P61/BREQ P62/BACK P67/*3 STBY RES NMI VSS EXTAL XTAL VCC AS RD HWR LWR MD0 MD1 MD2 AVCC VREF P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/ DA0 P77/AN7/ DA1 AVSS Mode 5 P52/A18 P53/A19 VSS P60/WAIT P61/BREQ P62/BACK P67/*3 STBY RES NMI VSS EXTAL XTAL VCC AS RD HWR LWR MD0 MD1 MD2 AVCC VREF P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/ DA0 P77/AN7/ DA1 AVSS Mode 7 P52 P53 VSS P60 P61 P62 P67/*4 STBY RES NMI VSS EXTAL XTAL VCC P63 P64 P65 P66 MD0 MD1 MD2 AVCC VREF P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/ DA0 P77/AN7/ DA1 AVSS P61/BREQ P62/BACK P67/*3 STBY RES NMI VSS EXTAL XTAL VCC AS RD HWR LWR MD0 MD1 MD2 AVCC VREF P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/ DA0 P77/AN7/ DA1 AVSS Rev. 2.0, 06/04, page 16 of 980 Pin No. FP-100B TFP-100B 87 88 89 90 91 92 93 Mode 1 P80/IRQ0/ RFSH P81/IRQ1/ CS3 P82/IRQ2/ CS2 P83/IRQ3/ CS1/ ADTRG P84/CS0 VSS PA0/TP0/ TCLKA/ TEND0 PA1/TP1/ TCLKB/ TEND1 PA2/TP2/ TIOCA0/ TCLKC PA3/TP3/ TIOCB0/ TCLKD PA4/TP4/ TIOCA1 PA5/TP5/ TIOCB1 PA6/TP6/ TIOCA2 PA7/TP7/ TIOCB2 Mode 2 P80/IRQ0/ RFSH P81/IRQ1/ CS3 P82/IRQ2/ CS2 P83/IRQ3/ CS1/ ADTRG P84/CS0 VSS PA0/TP0/ TCLKA/ TEND0 PA1/TP1/ TCLKB/ TEND1 PA2/TP2/ TIOCA0/ TCLKC PA3/TP3/ TIOCB0/ TCLKD PA4/TP4/ TIOCA1 PA5/TP5/ TIOCB1 PA6/TP6/ TIOCA2 PA7/TP7/ TIOCB2 Mode 3 P80/IRQ0/ RFSH P81/IRQ1/ CS3 P82/IRQ2/ CS2 Pin Name Mode 4 P80/IRQ0/ RFSH P81/IRQ1/ CS3 P82/IRQ2/ CS2 P83/IRQ3/ CS1/ ADTRG P84/CS0 VSS PA0/TP0/ TCLKA/ TEND0 PA1/TP1/ TCLKB/ TEND1 PA2/TP2/ TIOCA0/ TCLKC PA3/TP3/ TIOCB0/ TCLKD PA4/TP4/ TIOCA1/ A23 PA5/TP5/ TIOCB1/ A22 PA6/TP6/ TIOCA2/ A21 A20 Mode 5 P80/IRQ0/ RFSH P81/IRQ1/ CS3 P82/IRQ2/ CS2 P83/IRQ3/ CS1/ ADTRG P84/CS0 VSS PA0/TP0/ TCLKA/ TEND0 PA1/TP1/ TCLKB/ TEND1 PA2/TP2/ TIOCA0/ TCLKC PA3/TP3/ TIOCB0/ TCLKD PA4/TP4/ TIOCA1/ A23 PA5/TP5/ TIOCB1/ A22 PA6/TP6/ TIOCA2/ A21 PA7/TP7/ TIOCB2/ A20 Mode 7 P80/IRQ0 P81/IRQ1 P82/IRQ2 P83/IRQ3/ ADTRG P84 VSS PA0/TP0/ TCLKA/ TEND0 PA1/TP1/ TCLKB/ TEND1 PA2/TP2/ TIOCA0/ TCLKC PA3/TP3/ TIOCB0/ TCLKD PA4/TP4/ TIOCA1 PA5/TP5/ TIOCB1 PA6/TP6/ TIOCA2 PA7/TP7/ TIOCB2 P83/IRQ3/ CS1/ ADTRG P84/CS0 VSS PA0/TP0/ TCLKA/ TEND0 PA1/TP1 /TCLKB/ TEND1 PA2/TP2/ TIOCA0/ TCLKC PA3/TP3/ TIOCB0/ TCLKD PA4/TP4/ TIOCA1/ A23 PA5/TP5/ TIOCB1/ A22 PA6/TP6/ TIOCA2/ A21 A20 94 95 96 97 98 99 100 Notes: *1 In modes 1, 3, 5 the P40 to P47 functions of pins P40/D0 to P47/D7 are selected after a reset, but they can be changed by software. *2 In modes 2 and 4 the D0 to D7 functions of pins P40/D0 to P47/D7 are selected after a reset, but they can be changed by software. *3 In modes 1 to 5 the P67/ pin is the pin after a reset, but it can be changed by software. *4 In mode 7 the P67/ pin is set as the P67 pin after a reset, but it can be changed by software. Rev. 2.0, 06/04, page 17 of 980 Rev. 2.0, 06/04, page 18 of 980 Section 2 CPU 2.1 Overview The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. 2.1.1 Features The H8/300H CPU has the following features. * Upward compatibility with H8/300 CPU Can execute H8/300 Series object programs * General-register architecture Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) * Sixty-two basic instructions 8/16/32-bit arithmetic and logic instructions Multiply and divide instructions Powerful bit-manipulation instructions * Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16, ERn) or @(d:24, ERn)] Register indirect with post-increment or pre-decrement [@ERn+ or @-ERn] Absolute address [@aa:8, @aa:16, or @aa:24] Immediate [#xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8, PC) or @(d:16, PC)] Memory indirect [@@aa:8] * 16-Mbyte linear address space Rev. 2.0, 06/04, page 19 of 980 * High-speed operation All frequently-used instructions execute in two to four states Maximum clock frequency: 8 x 8-bit register-register multiply: 16 / 8-bit register-register divide: 16 x 16-bit register-register multiply: 32 / 16-bit register-register divide: * Two CPU operating modes Normal mode Advanced mode * Low-power mode Transition to power-down state by SLEEP instruction 2.1.2 Differences from H8/300 CPU 25 MHz 560 ns 560 ns 880 ns 880 ns 8/16/32-bit register-register add/subtract: 80 ns In comparison to the H8/300 CPU, the H8/300H has the following enhancements. * More general registers Eight 16-bit registers have been added. * Expanded address space Advanced mode supports a maximum 16-Mbyte address space. Normal mode supports the same 64-kbyte address space as the H8/300 CPU. (Normal mode cannot be selected in the H8/3029.) * Enhanced addressing The addressing modes have been enhanced to make effective use of the 16-Mbyte address space. * Enhanced instructions Data transfer, arithmetic, and logic instructions can operate on 32-bit data. Signed multiply/divide instructions and other instructions have been added. Rev. 2.0, 06/04, page 20 of 980 2.2 CPU Operating Modes The H8/300H CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports up to 16 Mbytes. Maximum 64 kbytes, program and data areas combined Normal mode* CPU operating modes Maximum 16 Mbytes, program and data areas combined Advanced mode Note: * Cannot be selected in H8/3029 Figure 2.1 CPU Operating Modes Rev. 2.0, 06/04, page 21 of 980 2.3 Address Space Figure 2.2 shows a simple memory map for the H8/3029. The H8/300H CPU can address a linear address space with a maximum size of 64 kbytes in normal mode, and 16 Mbytes in advanced mode. For further details see section 3.6, Memory Map in Each Operating Mode. The 1-Mbyte operating modes use 20-bit addressing. The upper 4 bits of effective addresses are ignored. H'0000 H'FFFF H'00000 H'000000 H'FFFFF H'FFFFFF a. 1-Mbyte mode Normal mode* Note: * Cannot be selected in H8/3029 b. 16-Mbyte mode Advanced mode Figure 2.2 Memory Map Rev. 2.0, 06/04, page 22 of 980 2.4 2.4.1 Register Configuration Overview The H8/300H CPU has the internal registers shown in figure 2.3. There are two types of registers: general registers and control registers. General Registers (ERn) 15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 Control Registers (CR) 23 PC 76543210 CCR I UI H U N Z V C Legend SP: Stack pointer PC: Program counter CCR: Condition code register Interrupt mask bit I: User bit or interrupt mask bit UI: Half-carry flag H: User bit U: Negative flag N: Zero flag Z: Overflow flag V: Carry flag C: 0 E0 E1 E2 E3 E4 E5 E6 E7 (SP) 07 R0H R1H R2H R3H R4H R5H R6H R7H 07 R0L R1L R2L R3L R4L R5L R6L R7L 0 Figure 2.3 CPU Registers Rev. 2.0, 06/04, page 23 of 980 2.4.2 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used without distinction between data registers and address registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or as address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers. Figure 2.4 illustrates the usage of the general registers. The usage of each register can be selected independently. * Address registers * 32-bit registers * 16-bit registers E registers (extended registers) E0 to E7 * 8-bit registers ER registers ER0 to ER7 R registers R0 to R7 RH registers R0H to R7H RL registers R0L to R7L Figure 2.4 Usage of General Registers Rev. 2.0, 06/04, page 24 of 980 General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.5 shows the stack. Free area SP (ER7) Stack area Figure 2.5 Stack 2.4.3 Control Registers The control registers are the 24-bit program counter (PC) and the 8-bit condition code register (CCR). Program Counter (PC): This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. When an instruction is fetched, the least significant PC bit is regarded as 0. Condition Code Register (CCR): This 8-bit register contains internal CPU status information, including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Bit 7--Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence. Bit 6--User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask bit. For details see section 5, Interrupt Controller. Bit 5--Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. Rev. 2.0, 06/04, page 25 of 980 Bit 4--User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. Bit 3--Negative Flag (N): Stores the value of the most significant bit of data, regarded as the sign bit. Bit 2--Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. Bit 1--Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Bit 0--Carry Flag (C): Set to 1 when a carry is generated by execution of an operation, and cleared to 0 otherwise. Used by: * Add instructions, to indicate a carry * Subtract instructions, to indicate a borrow * Shift and rotate instructions The carry flag is also used as a bit accumulator by bit manipulation instructions. Some instructions leave flag bits unchanged. Operations can be performed on CCR by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used by conditional branch (Bcc) instructions. For the action of each instruction on the flag bits, see appendix A.1, Instruction List. For the I and UI bits, see section 5, Interrupt Controller. 2.4.4 Initial CPU Register Values In reset exception handling, PC is initialized to a value loaded from the vector table, and the I bit in CCR is set to 1. The other CCR bits and the general registers are not initialized. In particular, the initial value of the stack pointer (ER7) is also undefined. The stack pointer (ER7) must therefore be initialized by an MOV.L instruction executed immediately after a reset. Rev. 2.0, 06/04, page 26 of 980 2.5 Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats Figures 2.6 and 2.7 show the data formats in general registers. General Register Data Type Data Format 7 0 Don't care 7 0 1-bit data RnH 76543210 1-bit data RnL 7 Don't care 43 0 76543210 4-bit BCD data RnH Upper digit Lower digit Don't care 7 43 0 4-bit BCD data RnL 7 Don't care 0 Upper digit Lower digit Byte data RnH MSB LSB 7 Don't care 0 LSB Byte data RnL Don't care MSB Legend RnH: General register RH RnL: General register RL Figure 2.6 General Register Data Formats Rev. 2.0, 06/04, page 27 of 980 Data Type General Register Data Format 15 0 LSB Word data Rn MSB 15 0 LSB 16 15 0 LSB Word data En MSB 31 Longword data ERn MSB Legend ERn: General register En: General register E Rn: General register R MSB: Most significant bit LSB: Least significant bit Figure 2.7 General Register Data Formats Rev. 2.0, 06/04, page 28 of 980 2.5.2 Memory Data Formats Figure 2.8 shows the data formats on memory. The H8/300H CPU can access word data and longword data on memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches. Data Type Address Data Format 7 1-bit data Byte data Word data Address L Address L Address 2M Address 2M + 1 Address 2N Longword data Address 2N + 1 Address 2N + 2 Address 2N + 3 MSB 0 6 5 4 3 2 1 0 LSB 7 MSB MSB LSB LSB Figure 2.8 Memory Data Formats When ER7 (SP) is used as an address register to access the stack, the operand size should be word size or longword size. Rev. 2.0, 06/04, page 29 of 980 2.6 2.6.1 Instruction Set Instruction Set Overview The H8/300H CPU has 62 types of instructions, which are classified in table 2.1. Table 2.1 Function Data transfer Instruction Classification Instruction MOV, PUSH* , POP* , MOVTPE* , MOVFPE* 1 1 2 2 Types 3 Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, 18 MULXU, MULXS, DIVXU, DIVXS, CMP, NEG, EXTS, EXTU Logic operations Shift operations Bit manipulation Branch System control Block data transfer AND, OR, XOR, NOT SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR 4 8 BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, 14 BIXOR, BLD, BILD, BST, BIST Bcc* , JMP, BSR, JSR, RTS TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP EEPMOV 3 5 9 1 Total 62 types Notes: *1 POP.W Rn is identical to MOV.W @SP+, Rn. PUSH.W Rn is identical to MOV.W Rn, @-SP. POP.L ERn is identical to MOV.L @SP+, Rn. PUSH.L ERn is identical to MOV.L Rn, @-SP. *2 Not available in the H8/3029. *3 Bcc is a generic branching instruction. Rev. 2.0, 06/04, page 30 of 980 2.6.2 Instructions and Addressing Modes Table 2.2 indicates the instructions available in the H8/300H CPU. Table 2.2 Instructions and Addressing Modes Addressing Modes @ (d:16, ERn) BWL -- -- @ (d:24, ERn) BWL -- -- @ (d:8, PC) -- -- -- @ (d:16, PC) -- -- -- Function Data transfer Instruction MOV POP, PUSH MOVFPE, MOVTPE #xx BWL -- -- Rn BWL -- -- @ERn BWL -- -- @ERn+/ @-ERn BWL -- -- @ aa:8 B -- -- @ aa:16 BWL -- -- @ aa:24 BWL -- -- @@ aa:8 -- -- -- -- -- WL -- Arithmetic operations ADD, CMP SUB ADDX, SUBX ADDS, SUBS INC, DEC DAA, DAS MULXU, MULXS, DIVXU, DIVXS NEG EXTU, EXTS BWL WL B -- -- -- -- BWL BWL B L BWL B BW -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BWL WL BWL BWL BWL B -- -- -- -- -- -- B B -- -- -- -- -- -- -- -- B -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- W W -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- W W -- -- -- -- -- -- -- -- B -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- W W -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Logic operations AND, OR, XOR -- NOT -- -- -- -- -- -- -- -- -- B -- B -- -- Shift instructions Bit manipulation Branch Bcc, BSR JMP, JSR RTS System control TRAPA RTE SLEEP LDC STC ANDC, ORC, XORC NOP Block data transfer -- -- -- -- W W -- -- -- -- -- -- -- W W -- -- -- -- -- -- -- W W -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BW Rev. 2.0, 06/04, page 31 of 980 2.6.3 Tables of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The operation notation used in these tables is defined next. Operation Notation Rd Rs Rn ERn (EAd) (EAs) CCR N Z V C PC SP #IMM disp + - x / :3/:8/:16/:24 Note: * General register (destination)* General register (source)* General register* General register (32-bit register or address register) Destination operand Source operand Condition code register N (negative) flag of CCR Z (zero) flag of CCR V (overflow) flag of CCR C (carry) flag of CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division AND logical OR logical Exclusive OR logical Move NOT (logical complement) 3-, 8-, 16-, or 24-bit length General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit data or address registers (ER0 to ER7). Rev. 2.0, 06/04, page 32 of 980 Table 2.3 Data Transfer Instructions Function (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. Instruction Size* MOV B/W/L MOVFPE MOVTPE POP B B W/L (EAs) Rd Cannot be used in this LSI. Rs (EAs) Cannot be used in this LSI. @SP+ Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. Similarly, POP.L ERn is identical to MOV.L @SP+, ERn. PUSH W/L Rn @-SP Pushes a general register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @-SP. Similarly, PUSH.L ERn is identical to MOV.L ERn, @-SP. Note: * Size refers to the operand size. B: Byte W: Word L: Longword Rev. 2.0, 06/04, page 33 of 980 Table 2.4 Arithmetic Operation Instructions Function Rd Rs Rd, Rd #IMM Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from data in a general register. Use the SUBX or ADD instruction.) Instruction Size* ADD,SUB B/W/L ADDX, SUBX INC, DEC ADDS, SUBS DAA, DAS MULXU B Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry or borrow on data in two general registers, or on immediate data and data in a general register. B/W/L Rd 1 Rd, Rd 2 Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) L B Rd 1 Rd, Rd 2 Rd, Rd 4 Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. Rd decimal adjust Rd Decimal-adjusts an addition or subtraction result in a general register by referring to CCR to produce 4-bit BCD data. B/W Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. MULXS B/W Rd x Rs Rd Performs signed multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. DIVXU B/W Rd / Rs Rd Performs unsigned division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder DIVXS B/W Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder, or 32 bits / 16 bits 16-bit quotient and 16-bit remainder CMP B/W/L Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR according to the result. NEG B/W/L 0 - Rd Rd Takes the two's complement (arithmetic complement) of data in a general register. Rev. 2.0, 06/04, page 34 of 980 Instruction Size* EXTS W/L Function Rd (sign extension) Rd Extends byte data in the lower 8 bits of a 16-bit register to word data, or extends word data in the lower 16 bits of a 32-bit register to longword data, by extending the sign bit. EXTU W/L Rd (zero extension) Rd Extends byte data in the lower 8 bits of a 16-bit register to word data, or extends word data in the lower 16 bits of a 32-bit register to longword data, by padding with zeros. Note: * Size refers to the operand size. B: Byte W: Word L: Longword Table 2.5 Logic Operation Instructions Function Rd Rs Rd, Rd #IMM Rd Performs a logical AND operation on a general register and another general register or immediate data. Instruction Size* AND B/W/L OR B/W/L Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data. XOR B/W/L Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. NOT B/W/L Rd Rd Takes the one's complement (logical complement) of general register contents. Note: * Size refers to the operand size. B: Byte W: Word L: Longword Rev. 2.0, 06/04, page 35 of 980 Table 2.6 Shift Instructions Function Rd (shift) Rd Performs an arithmetic shift on general register contents. B/W/L B/W/L B/W/L Rd (shift) Rd Performs a logical shift on general register contents. Rd (rotate) Rd Rotates general register contents. Rd (rotate) Rd Rotates general register contents, including the carry bit. Size refers to the operand size. B: Byte W: Word L: Longword Instruction Size* SHAL, SHAR SHLL, SHLR ROTL, ROTR ROTXL, ROTXR Note: * B/W/L Rev. 2.0, 06/04, page 36 of 980 Table 2.7 Bit Manipulation Instructions Function 1 ( Instruction Size* BSET B BCLR B 0 ( BNOT B ( BTST B ( BAND B C ( BIAND B C [ ( BOR B C ( BIOR B C [ ( BXOR B C ( BIXOR B C [ ( Rev. 2.0, 06/04, page 37 of 980 Instruction Size* BLD B Function ( BILD B ( BST B C ( BIST B C ( Note: * Size refers to the operand size. B: Byte Rev. 2.0, 06/04, page 38 of 980 Table 2.8 Branching Instructions Function Branches to a specified address if address specified condition is met. The branching conditions are listed below. Mnemonic BRA (BT) BRN (BF) BHI BLS Bcc (BHS) BCS (BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE Description Always (true) Never (false) High Low or same Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal Condition Always Never CZ=0 CZ=1 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z (N V) = 0 Z (N V) = 1 Instruction Size Bcc -- Carry clear (high or same) C = 0 JMP BSR JSR RTS -- -- -- -- Branches unconditionally to a specified address Branches to a subroutine at a specified address Branches to a subroutine at a specified address Returns from a subroutine Rev. 2.0, 06/04, page 39 of 980 Table 2.9 System Control Instructions Function Starts trap-instruction exception handling Returns from an exception-handling routine Causes a transition to the power-down state (EAs) CCR Moves the source operand contents to the condition code register. The condition code register size is one byte, but in transfer from memory, data is read by word access. Instruction Size* TRAPA RTE SLEEP LDC -- -- -- B/W STC B/W CCR (EAd) Transfers the CCR contents to a destination location. The condition code register size is one byte, but in transfer to memory, data is written by word access. ANDC ORC XORC NOP Note: * B B B -- CCR #IMM CCR Logically ANDs the condition code register with immediate data. CCR #IMM CCR Logically ORs the condition code register with immediate data. CCR #IMM CCR Logically exclusive-ORs the condition code register with immediate data. PC + 2 PC Only increments the program counter. Size refers to the operand size. B: Byte W: Word Rev. 2.0, 06/04, page 40 of 980 Table 2.10 Block Transfer Instruction Instruction EEPMOV.B Size -- Function if R4L 0 then repeat @ER5+ @ER6+, R4L - 1 R4L until R4L = 0 else next; if R4 0 then repeat @ER5+ @ER6+, R4 - 1 R4 until R4 = 0 else next; Block transfer instruction. This instruction transfers the number of data bytes specified by R4L or R4, starting from the address indicated by ER5, to the location starting at the address indicated by ER6. At the end of the transfer, the next instruction is executed. EEPMOV.W -- 2.6.4 Basic Instruction Formats The H8/300H instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (OP field), a register field (r field), an effective address extension (EA field), and a condition field (cc field). Operation Field: Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first 4 bits of the instruction. Some instructions have two operation fields. Register Field: Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. Effective Address Extension: 8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. A 24-bit address or displacement is treated as 32-bit data in which the first 8 bits are 0 (H'00). Condition Field: Specifies the branching condition of Bcc instructions. Figure 2.9 shows examples of instruction formats. Rev. 2.0, 06/04, page 41 of 980 Operation field only op Operation field and register fields op rn rm ADD.B Rn, Rm, etc. NOP, RTS, etc. Operation field, register fields, and effective address extension op EA (disp) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:8 rn rm MOV.B @(d:16, Rn), Rm Figure 2.9 Instruction Formats 2.6.5 Notes on Use of Bit Manipulation Instructions The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, modify a bit in the byte, then write the byte back. Care is required when these instructions are used to access registers with write-only bits, or to access ports. Step 1 2 3 Read Modify Write Description Read one data byte at the specified address Modify one bit in the data byte Write the modified data byte back to the specified address Example 1: BCLR is executed to clear bit 0 in the port 4 data direction register (P4DDR) under the following conditions. P47, P46: Input pins P45 - P40: Output pins The intended purpose of this BCLR instruction is to switch P40 from output to input. Before Execution of BCLR Instruction P47 Input/output DDR Input 0 P46 Input 0 P45 Output 1 P44 Output 1 P43 Output 1 P42 Output 1 P41 Output 1 P40 Output 1 Rev. 2.0, 06/04, page 42 of 980 Execution of BCLR Instruction BCLR #0, @P4DDR ;Clear bit 0 in data direction register After Execution of BCLR Instruction P47 Input/output DDR Output 1 P46 Output 1 P45 Output 1 P44 Output 1 P43 Output 1 P42 Output 1 P41 Output 1 P40 Input 0 Explanation: To execute the BCLR instruction, the CPU begins by reading P4DDR. Since P4DDR is a write-only register, it is read as H'FF, even though its true value is H'3F. Next the CPU clears bit 0 of the read data, changing the value to H'FE. Finally, the CPU writes this value (H'FE) back to P4DDR to complete the BCLR instruction. As a result, P40DDR is cleared to 0, making P40 an input pin. In addition, P47DDR and P46DDR are set to 1, making P47 and P46 output pins. The BCLR instruction can be used to clear flags in the on-chip registers to 0. In an interrupthandling routine, for example, if it is known that the flag is set to 1, it is not necessary to read the flag ahead of time. Rev. 2.0, 06/04, page 43 of 980 2.7 2.7.1 Addressing Modes and Effective Address Calculation Addressing Modes The H8/300H CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except programcounter relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or absolute (@aa:8) addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2.11 Addressing Modes No. 1 2 3 4 5 6 7 8 Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol Rn @ERn @(d:16, ERn)/@(d:24, ERn) @ERn+ @-ERn @aa:8/@aa:16/@aa:24 #xx:8/#xx:16/#xx:32 @(d:8, PC)/@(d:16, PC) @@aa:8 1 Register Direct--Rn: The register field of the instruction code specifies an 8-, 16-, or 32-bit register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. 2 Register Indirect--@ERn: The register field of the instruction code specifies an address register (ERn), the lower 24 bits of which contain the address of the operand. 3 Register Indirect with Displacement--@(d:16, ERn) or @(d:24, ERn): A 16-bit or 24-bit displacement contained in the instruction code is added to the contents of an address register (ERn) specified by the register field of the instruction, and the lower 24 bits of the sum specify the address of a memory operand. A 16-bit displacement is sign-extended when added. Rev. 2.0, 06/04, page 44 of 980 4 Register Indirect with Post-Increment or Pre-Decrement--@ERn+ or @-ERn: * Register indirect with post-increment--@ERn+ The register field of the instruction code specifies an address register (ERn) the lower 24 bits of which contain the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents (32 bits) and the sum is stored in the address register. The value added is 1 for byte access, 2 for word access, or 4 for longword access. For word or longword access, the register value should be even. * Register indirect with pre-decrement--@-ERn The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the lower 24 bits of the result become the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. For word or longword access, the resulting register value should be even. 5 Absolute Address--@aa:8, @aa:16, or @aa:24: The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), or 24 bits long (@aa:24). For an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 8 bits are a sign extension. A 24-bit absolute address can access the entire address space. Table 2.12 indicates the accessible address ranges. Table 2.12 Absolute Address Access Ranges Absolute Address 8 bits (@aa:8) 16 bits (@aa:16) 1-Mbyte Modes H'FFF00 to H'FFFFF (1048320 to 1048575) H'00000 to H'07FFF, H'F8000 to H'FFFFF (0 to 32767, 1015808 to 1048575) H'00000 to H'FFFFF (0 to 1048575) 16-Mbyte Modes H'FFFF00 to H'FFFFFF (16776960 to 16777215) H'000000 to H'007FFF, H'FF8000 to H'FFFFFF (0 to 32767, 16744448 to 16777215) H'000000 to H'FFFFFF (0 to 16777215) 24 bits (@aa:24) 6 Immediate--#xx:8, #xx:16, or #xx:32: The instruction code contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The instruction codes of the ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. The instruction codes of some bit manipulation instructions contain 3-bit immediate data specifying a bit number. The TRAPA instruction code contains 2-bit immediate data specifying a vector address. Rev. 2.0, 06/04, page 45 of 980 7 Program-Counter Relative--@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is signextended to 24 bits and added to the 24-bit PC contents to generate a 24-bit branch address. The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is -126 to +128 bytes (-63 to +64 words) or -32766 to +32768 bytes (-16383 to +16384 words) from the branch instruction. The resulting value should be an even number. 8 Memory Indirect--@@aa:8: This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The memory operand is accessed by longword access. The first byte of the memory operand is ignored, generating a 24-bit branch address. See figure 2.10. The upper bits of the 8-bit absolute address are assumed to be 0 (H'0000), so the address range is 0 to 255 (H'000000 to H'0000FF). Note that the first part of this range is also the exception vector area. For further details see section 5, Interrupt Controller. Specified by @aa:8 Reserved Branch address Figure 2.10 Memory-Indirect Branch Address Specification When a word-size or longword-size memory operand is specified, or when a branch address is specified, if the specified memory address is odd, the least significant bit is regarded as 0. The accessed data or instruction code therefore begins at the preceding address. See section 2.5.2, Memory Data Formats. 2.7.2 Effective Address Calculation Table 2.13 explains how an effective address is calculated in each addressing mode. In the 1-Mbyte operating modes the upper 4 bits of the calculated address are ignored in order to generate a 20-bit effective address. Rev. 2.0, 06/04, page 46 of 980 Table 2.13 Effective Address Calculation Addressing Mode and Instruction Format Effective Address Calculation Register direct (Rn) op Register indirect (@ERn) General register contents op Register indirect with displacement @(d:16, ERn)/@(d:24, ERn) 31 General register contents 0 23 disp 0 r 31 0 23 rm rn 0 Effective Address Operand is general register contents No. 1 2 3 op Sign extension r 4 Register indirect with post-increment @ERn+ 31 Register indirect with post-increment or pre-decrement 0 General register contents 23 0 op r 31 1, 2, or 4 0 General register contents 23 1, 2, or 4 1 for a byte operand, 2 for a word operand, 4 for a longword operand 0 Register indirect with pre-decrement @-ERn Rev. 2.0, 06/04, page 47 of 980 op r No. 23 H'FFFF 87 Addressing Mode and Instruction Format Effective Address Calculation Effective Address 5 abs 23 op abs 23 op abs 16 15 Absolute address @aa:8 0 op Sign extension 0 Rev. 2.0, 06/04, page 48 of 980 Operand is immediate data op IMM 23 PC contents 0 23 Sign extension @aa:16 0 @aa:24 6 Immediate #xx:8, #xx:16, or #xx:32 7 Program-counter relative @(d:8, PC) or @(d:16, PC) 0 disp op disp No. Addressing Mode and Instruction Format Effective Address Calculation Effective Address 8 Memory indirect @@aa:8 Normal mode abs 23 H'0000 15 0 Memory contents abs 23 16 15 H'00 0 87 0 op Advanced mode abs 23 H'0000 31 Memory contents 87 abs 0 23 0 0 op Legend r, rm, rn: op: disp: IMM: abs: Rev. 2.0, 06/04, page 49 of 980 Register field Operation field Displacement Immediate data Absolute address 2.8 2.8.1 Processing States Overview The H8/300H CPU has five processing states: the program execution state, exception-handling state, power-down state, reset state, and bus-released state. The power-down state includes sleep mode, software standby mode, and hardware standby mode. Figure 2.11 classifies the processing states. Figure 2.13 indicates the state transitions. Processing states Program execution state The CPU executes program instructions in sequence Exception-handling state A transient state in which the CPU executes a hardware sequence (saving PC and CCR, fetching a vector, etc.) in response to a reset, interrupt, or other exception Bus-released state The external bus has been released in response to a bus request signal from a bus master other than the CPU Reset state The CPU and all on-chip supporting modules are initialized and halted Power-down state The CPU is halted to conserve power Sleep mode Software standby mode Hardware standby mode Figure 2.11 Processing States Rev. 2.0, 06/04, page 50 of 980 2.8.2 Program Execution State In this state the CPU executes program instructions in normal sequence. 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal program flow due to a reset, interrupt, or trap instruction. The CPU fetches a starting address from the exception vector table and branches to that address. In interrupt and trap exception handling the CPU references the stack pointer (ER7) and saves the program counter and condition code register. Types of Exception Handling and Their Priority: Exception handling is performed for resets, interrupts, and trap instructions. Table 2.14 indicates the types of exception handling and their priority. Trap instruction exceptions are accepted at all times in the program execution state. Table 2.14 Exception Handling Types and Priority Priority High Type of Exception Detection Timing Reset Interrupt Synchronized with clock End of instruction execution or end of exception handling* Start of Exception Handling Exception handling starts immediately when 4-5 changes from low to high When an interrupt is requested, exception handling starts at the end of the current instruction or current exception-handling sequence Trap instruction Low When TRAPA instruction Exception handling starts when a trap is executed (TRAPA) instruction is executed Note: * Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions, or immediately after reset exception handling. Figure 2.12 classifies the exception sources. For further details about exception sources, vector numbers, and vector addresses, see section 4, Exception Handling, and section 5, Interrupt Controller. Reset External interrupts Exception sources Interrupt Internal interrupts (from on-chip supporting modules) Trap instruction Figure 2.12 Classification of Exception Sources Rev. 2.0, 06/04, page 51 of 980 Bus request End of bus release Program execution state End of bus release Bus request Exception handling source Bus-released state End of exception handling Exception-handling state SLEEP instruction with SSBY = 0 Sleep mode Interrupt source NMI, IRQ 0 , IRQ 1, or IRQ 2 interrupt SLEEP instruction with SSBY = 1 Software standby mode RES = "High" STBY="High", RES ="Low" Reset state *1 Hardware standby mode Power-down state *2 Notes: *1 From any state except hardware standby mode, a transition to the reset state occurs whenever 4-5 goes low. *2 From any state, a transition to hardware standby mode occurs when 56*; goes low. Figure 2.13 State Transitions Rev. 2.0, 06/04, page 52 of 980 2.8.4 Exception-Handling Sequences Reset Exception Handling: Reset exception handling has the highest priority. The reset state is entered when the RES signal goes low. Reset exception handling starts after that, when RES changes from low to high. When reset exception handling starts the CPU fetches a start address from the exception vector table and starts program execution from that address. All interrupts, including NMI, are disabled during the reset exception-handling sequence and immediately after it ends. Interrupt Exception Handling and Trap Instruction Exception Handling: When these exception-handling sequences begin, the CPU references the stack pointer (ER7) and pushes the program counter and condition code register on the stack. Next, if the UE bit in the system control register (SYSCR) is set to 1, the CPU sets the I bit in the condition code register to 1. If the UE bit is cleared to 0, the CPU sets both the I bit and the UI bit in the condition code register to 1. Then the CPU fetches a start address from the exception vector table and execution branches to that address. Figure 2.14 shows the stack after the exception-handling sequence. SP-4 SP-3 SP-2 SP-1 SP (ER7) Stack area SP (ER7) SP+1 SP+2 SP+3 SP+4 CCR PC Even address Before exception handling starts Legend CCR: Condition code register SP: Stack pointer Pushed on stack After exception handling ends Notes: 1. PC is the address of the first instruction executed after the return from the exception-handling routine. 2. Registers must be saved and restored by word access or longword access, starting at an even address. Figure 2.14 Stack Structure after Exception Handling Rev. 2.0, 06/04, page 53 of 980 2.8.5 Bus-Released State In this state the bus is released to a bus master other than the CPU, in response to a bus request. The bus masters other than the CPU are the DMA controller, the DRAM interface, and an external bus master. While the bus is released, the CPU halts except for internal operations. Interrupt requests are not accepted. For details see section 6.10, Bus Arbiter. 2.8.6 Reset State When the RES input goes low all current processing stops and the CPU enters the reset state. The I bit in the condition code register is set to 1 by a reset. All interrupts are masked in the reset state. Reset exception handling starts when the RES signal changes from low to high. The reset state can also be entered by a watchdog timer overflow. For details see section 12, Watchdog Timer. 2.8.7 Power-Down State In the power-down state the CPU stops operating to conserve power. There are three modes: sleep mode, software standby mode, and hardware standby mode. Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while the SSBY bit is cleared to 0 in the system control register (SYSCR). CPU operations stop immediately after execution of the SLEEP instruction, but the contents of CPU registers are retained. Software Standby Mode: A transition to software standby mode is made if the SLEEP instruction is executed while the SSBY bit is set to 1 in SYSCR. The CPU and clock halt and all on-chip supporting modules stop operating. The on-chip supporting modules are reset, but as long as a specified voltage is supplied the contents of CPU registers and on-chip RAM are retained. The I/O ports also remain in their existing states. Hardware Standby Mode: A transition to hardware standby mode is made when the STBY input goes low. As in software standby mode, the CPU and all clocks halt and the on-chip supporting modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are retained. For further information see section 20, Power-Down State. Rev. 2.0, 06/04, page 54 of 980 2.9 2.9.1 Basic Operational Timing Overview The H8/300H CPU operates according to the system clock (o). The interval from one rise of the system clock to the next rise is referred to as a "state." A memory cycle or bus cycle consists of two or three states. The CPU uses different methods to access on-chip memory, the on-chip supporting modules, and the external address space. Access to the external address space can be controlled by the bus controller. 2.9.2 On-Chip Memory Access Timing On-chip memory is accessed in two states. The data bus is 16 bits wide, permitting both byte and word access. Figure 2.15 shows the on-chip memory access cycle. Figure 2.16 indicates the pin states. Bus cycle T1 state Internal address bus Internal read signal Internal data bus (read access) Internal write signal Internal data bus (write access) Write data Read data Address T2 state Figure 2.15 On-Chip Memory Access Cycle Rev. 2.0, 06/04, page 55 of 980 T1 Address bus Address T2 AS , RD, HWR , LWR High High impedance D15 to D0 Figure 2.16 Pin States during On-Chip Memory Access 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in three states. The data bus is 8 or 16 bits wide, depending on the internal I/O register being accessed. Figure 2.17 shows the on-chip supporting module access timing. Figure 2.18 indicates the pin states. Bus cycle T1 state Address bus Internal read signal Internal data bus Address T2 state T3 state Read access Read data Internal write signal Write access Internal data bus Write data Figure 2.17 Access Cycle for On-Chip Supporting Modules Rev. 2.0, 06/04, page 56 of 980 T1 Address bus AS , RD, HWR , LWR T2 T3 Address High High impedance D15 to D0 Figure 2.18 Pin States during Access to On-Chip Supporting Modules 2.9.4 Access to External Address Space The external address space is divided into eight areas (areas 0 to 7). Bus-controller settings determine whether each area is accessed via an 8-bit or 16-bit bus, and whether it is accessed in two or three states. For details see section 6, Bus Controller. Rev. 2.0, 06/04, page 57 of 980 Rev. 2.0, 06/04, page 58 of 980 Section 3 MCU Operating Modes 3.1 3.1.1 Overview Operating Mode Selection The H8/3029 has six operating modes (modes 1 to 5, 7) that are selected by the mode pins (MD2 to MD0) as indicated in table 3.1. The input at these pins determines the size of the address space and the initial bus mode. Table 3.1 Operating Mode Selection Description Mode Pins Operating Mode MD2 MD1 MD0 -- Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 -- Mode 7 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Initial Bus On-Chip 1 Mode* ROM -- 8 bits 16 bits 8 bits 16 bits 8 bits -- -- -- Disabled Disabled Disabled Disabled Enabled -- Enabled On-Chip RAM -- Enabled* Enabled* Enabled* Enabled* Enabled* -- Enabled 2 2 2 2 2 Address Space -- Expanded mode Expanded mode Expanded mode Expanded mode Expanded mode -- Single-chip advanced mode Notes: *1 In modes 1 to 5, an 8-bit or 16-bit data bus can be selected on a per-area basis by settings made in the area bus width control register (ABWCR). For details see section 6, Bus Controller. *2 If the RAME bit in SYSCR is cleared to 0, these addresses become external addresses. For the address space size there are two choices: 1 Mbyte or 16 Mbyte.The external data bus is either 8 or 16 bits wide depending on ABWCR settings. If 8-bit access is selected for all areas, 8bit bus mode is used. For details see section 6, Bus Controller. Modes 1 to 4 are externally expanded modes that enable access to external memory and peripheral devices and disable access to the on-chip ROM. Modes 1 and 2 support a maximum address space of 1 Mbyte. Modes 3 and 4 support a maximum address space of 16 Mbytes. Rev. 2.0, 06/04, page 59 of 980 Mode 5 is an externally expanded mode that enables access to external memory and peripheral devices and also enables access to the on-chip ROM. Mode 5 supports a maximum address space of 16 Mbytes. Mode 7 are single-chip modes that operate using the on-chip ROM, RAM, and registers, and makes all I/O ports available. Mode 7 supports a maximum address space of 1 Mbyte. The H8/3029 can be used only in modes 1 to 5, 7. The inputs at the mode pins must select one of these six modes. The inputs at the mode pins must not be changed during operation. 3.1.2 Register Configuration The H8/3029 has a mode control register (MDCR) that indicates the inputs at the mode pins (MD2 to MD0), and a system control register (SYSCR). Table 3.2 summarizes these registers. Table 3.2 Address* H'EE011 H'EE012 Note: * Registers Name Mode control register System control register Abbreviation MDCR SYSCR R/W R R/W Initial Value Undetermined H'09 Lower 20 bits of the address in advanced mode. Rev. 2.0, 06/04, page 60 of 980 3.2 Mode Control Register (MDCR) MDCR is an 8-bit read-only register that indicates the current operating mode of the H8/3029. Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 0 -- 4 -- 0 -- Reserved bits 3 -- 0 -- 2 MDS2 --* R 1 MDS1 --* R 0 MDS0 --* R Reserved bits Mode select 2 to 0 Bits indicating the current operating mode Note: * Determined by pins MD 2 to MD 0 . Bits 7 and 6--Reserved: These bits can not be modified and are always read as 1. Bits 5 to 3--Reserved: These bits can not be modified and are always read as 0. Bits 2 to 0--Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the logic levels at pins MD2 to MD0 (the current operating mode). MDS2 to MDS0 correspond to MD2 to MD0. MDS2 to MDS0 are read-only bits. The mode pin (MD2 to MD0) levels are latched into these bits when MDCR is read. Note: A product with on-chip flash memory can operate in boot mode in which flash memory can be programmed. In boot mode, the MDS2 bit indicates the logic level at pin MD2. Rev. 2.0, 06/04, page 61 of 980 3.3 System Control Register (SYSCR) SYSCR is an 8-bit register that controls the operation of the H8/3029. Bit Initial value Read/Write 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 UE 1 R/W 2 NMIEG 0 R/W 1 SSOE 0 R/W 0 RAME 1 R/W RAM enable Enables or disables on-chip RAM Software standby output port enable Selects the output state of the address bus and bus control signals in software standby mode NMI edge select Selects the valid edge of the NMI input User bit enable Selects whether to use the UI bit in CCR as a user bit or an interrupt mask bit Standby timer select 2 to 0 These bits select the waiting time at recovery from software standby mode Software standby Enables transition to software standby mode Bit 7--Software Standby (SSBY): Enables transition to software standby mode. (For further information about software standby mode see section 20, Power-Down State.) When software standby mode is exited by an external interrupt, this bit remains set to 1. To clear this bit, write 0. Bit 7 SSBY 0 1 Description SLEEP instruction causes transition to sleep mode SLEEP instruction causes transition to software standby mode (Initial value) Rev. 2.0, 06/04, page 62 of 980 Bits 6 to 4--Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the length of time the CPU and on-chip supporting modules wait for the internal clock oscillator to settle when software standby mode is exited by an external interrupt. When using a crystal oscillator, set these bits so that the waiting time will be at least 7 ms at the system clock rate. For further information about waiting time selection, see section 20.4.3, Selection of Waiting Time for Exit from Software Standby Mode. Bit 6 STS2 0 0 0 0 1 1 1 1 Bit 5 STS1 0 0 1 1 0 0 1 1 Bit 4 STS0 0 1 0 1 0 1 0 1 Description Waiting time = 8,192 states Waiting time = 16,384 states Waiting time = 32,768 states Waiting time = 65,536 states Waiting time = 131,072 states Waiting time = 262,144 states Waiting time = 1,024 states Illegal setting (Initial value) Bit 3--User Bit Enable (UE): Selects whether to use the UI bit in the condition code register as a user bit or an interrupt mask bit. Bit 3 UE 0 1 Description UI bit in CCR is used as an interrupt mask bit UI bit in CCR is used as a user bit (Initial value) Bit 2--NMI Edge Select (NMIEG): Selects the valid edge of the NMI input. Bit 2 NMIEG 0 1 Description An interrupt is requested at the falling edge of NMI An interrupt is requested at the rising edge of NMI (Initial value) Rev. 2.0, 06/04, page 63 of 980 Bit 1--Software Standby Output Port Enable (SSOE): Specifies whether the address bus and bus control signals (CS0 to CS7, AS, RD, HWR, LWR, UCAS, LCAS, and RFSH) are kept as outputs or fixed high, or placed in the high-impedance state in software standby mode. Bit 1 SSOE 0 1 Description In software standby mode, the address bus and bus control signals are all highimpedance (Initial value) In software standby mode, the address bus retains its output state and bus control signals are fixed high Bit 0--RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized by the rising edge of the RES signal. It is not initialized in software standby mode. Bit 0 RAME 0 1 Description On-chip RAM is disabled On-chip RAM is enabled (Initial value) 3.4 3.4.1 Operating Mode Descriptions Mode 1 Ports 1, 2, and 5 function as address pins A19 to A0, permitting access to a maximum 1-Mbyte address space. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least one area is designated for 16-bit access in ABWCR, the bus mode switches to 16 bits. 3.4.2 Mode 2 Ports 1, 2, and 5 function as address pins A19 to A0, permitting access to a maximum 1-Mbyte address space. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. If all areas are designated for 8-bit access in ABWCR, the bus mode switches to 8 bits. 3.4.3 Mode 3 Ports 1, 2, 5, and part of port A function as address pins A23 to A0, permitting access to a maximum 16-Mbyte address space. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least one area is designated for 16-bit access in ABWCR, the bus mode switches to 16 bits. A23 to A21 are valid when 0 is written in bits 7 to 5 of the bus release control register (BRCR). (In this mode A20 is always used for address output.) Rev. 2.0, 06/04, page 64 of 980 3.4.4 Mode 4 Ports 1, 2, 5, and part of port A function as address pins A23 to A0, permitting access to a maximum 16-Mbyte address space. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. If all areas are designated for 8-bit access in ABWCR, the bus mode switches to 8 bits. A23 to A21 are valid when 0 is written in bits 7 to 5 of BRCR. (In this mode A20 is always used for address output.) 3.4.5 Mode 5 Ports 1, 2, 5, and part of port A can function as address pins A23 to A0, permitting access to a maximum 16-Mbyte address space, but following a reset they are input ports. To use ports 1, 2, and 5 as an address bus, the corresponding bits in their data direction registers (P1DDR, P2DDR, and P5DDR) must be set to 1. For A23 to A20 output, write 0 in bits 7 to 4 of BRCR. Products with on-chip flash memory support on-board programming which enables programming of the flash memory. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least one area is designated for 16-bit access in ABWCR, the bus mode switches to 16 bits. 3.4.6 Mode 7 This mode operates using the on-chip ROM, RAM, and registers. All I/O ports are available. Mode 7 supports a 1-Mbyte address space. Products with on-chip flash memory support on-board programming which enables programming of the flash memory. Rev. 2.0, 06/04, page 65 of 980 3.5 Pin Functions in Each Operating Mode The pin functions of ports 1 to 5, A and port 67 vary depending on the operating mode. Table 3.3 indicates their functions in each operating mode. Table 3.3 Port Port 1 Port 2 Port 3 Port 4 Port 5 Port 67 Port A Pin Functions in Each Mode Mode 2 A7 to A0 A15 to A8 D15 to D8 D7 to D0*1 A19 to A16 * 5 Mode 1 A7 to A0 A15 to A8 D15 to D8 P47 to P40*1 A19 to A16 * 5 Mode 3 A7 to A0 A15 to A8 D15 to D8 P47 to P40*1 A19 to A16 * 5 Mode 4 A7 to A0 A15 to A8 D15 to D8 D7 to D0*1 A19 to A16 * 5 Mode 5 P17 to P10* D15 to D8 P47 to P40*1 P53 to P50*2 *5 PA7 to PA4*4 2 Mode 7 P17 to P10 P27 to P20 P37 to P30 P47 to P40 P53 to P50 P67 *5 PA7 to PA4 P27 to P20*2 PA7 to PA4 PA7 to PA4 PA6 to PA4, A20*3 PA6 to PA4, A20*3 Notes: *1 Initial state. The bus mode can be switched by settings in ABWCR. These pins function as P47 to P40 in 8-bit bus mode, and as D7 to D0 in 16-bit bus mode. *2 Initial state. These pins become address output pins when the corresponding bits in the data direction registers (P1DDR, P2DDR, P5DDR) are set to 1. *3 Initial state. A20 is always an address output pin. PA6 to PA4 are switched over to A23 to A21 output by writing 0 in bits 7 to 5 of BRCR. *4 Initial state. PA7 to PA4 are switched over to A23 to A20 output by writing 0 in bits 7 to 4 of BRCR. *5 Initial state. In modes 1 to 5 12 can be set as P67 by writing 1 to bit 7 in MSTCRH. In mode 7 P67 can be set to output by writing 0 to bit 7 in MSTCRH. Rev. 2.0, 06/04, page 66 of 980 3.6 Memory Map in Each Operating Mode Figures 3.1 and 3.2 show memory maps of the H8/3029. The address space is divided into eight areas. The EMC bit in BCR can be read and written to select either of the two memory maps. For details, see section 6.2.5, Bus Control Register (BCR). The initial bus mode differs between modes 1 and 2, and also between modes 3 and 4. The address locations of the on-chip RAM and on-chip registers differ between the 1-Mbyte modes (modes 1, 2, and 7), and the 16-Mbyte modes (modes 3, 4, and 5). The address range specifiable by the CPU in the 8- and 16-bit absolute addressing modes (@aa:8 and @aa:16) also differs. 3.6.1 Note on Reserved Areas The H8/3029 memory map includes reserved areas to which read/write access is prohibited. Note that normal operation is not guaranteed if the following reserved areas are accessed. * The reserved area in the internal I/O register space. The H8/3029 internal I/O register space includes a reserved area to which access is prohibited. For details see appendix B, Internal I/O Registers. Rev. 2.0, 06/04, page 67 of 980 Modes 1 and 2 (1-Mbyte expanded modes with on-chip ROM disabled) Memory-indirect branch addresses Modes 3 and 4 (16-Mbyte expanded modes with on-chip ROM disabled) Vector area Memory-indirect branch addresses H'00000 16-bit absolute addresses H'000FF H'0000FF H'07FFF H'007FFF H'1FFFF H'20000 H'3FFFF H'40000 H'5FFFF H'60000 External address space H'7FFFF H'80000 H'9FFFF H'A0000 H'BFFFF H'C0000 H'DFFFF H'E0000 H'EE000 H'EE0FF H'F8000 H'FBF1F H'FBF20 H'FFF00 H'FFF1F H'FFF20 H'FFFE9 H'FFFEA H'FFFFF Internal I/O registers (2) External address space Internal I/O registers (1) External address space Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 H'7FFFFF H'800000 H'9FFFFF H'A00000 H'5FFFFF H'600000 External address space H'3FFFFF H'400000 H'1FFFFF H'200000 Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 8-bit absolute addresses 16-bit absolute addresses H'BFFFFF H'C00000 Area 6 H'DFFFFF H'E00000 H'FEE000 H'FEE0FF H'FF8000 H'FFBF1F H'FFBF20 H'FFFF00 H'FFFF1F H'FFFF20 H'FFFFE9 H'FFFFEA H'FFFFFF 8-bit absolute addresses External address space On-chip RAM* Area 7 Internal I/O registers (1) On-chip RAM* Internal I/O registers (2) External address space Note: * External addresses can be accessed by disabling on-chip RAM. Figure 3.1(1) H8/3029 Memory Map in Each Operating Mode (EMC = 1) Rev. 2.0, 06/04, page 68 of 980 16-bit absolute addresses 16-bit absolute addresses Vector area H'000000 Mode 5 (16-Mbyte expanded mode with on-chip ROM enabled) Memory-indirect branch addresses Mode 7 (single-chip advanced mode) H'00000 16-bit absolute addresses H'0000FF On-chip ROM H'007FFF H'07FFFF H'080000 H'1FFFFF H'200000 H'3FFFFF H'400000 H'5FFFFF H'600000 External address space H'7FFFFF H'800000 H'9FFFFF H'A00000 H'BFFFFF H'C00000 H'DFFFFF H'E00000 H'FEE000 H'FEE0FF H'FF8000 External address space*2 H'000FF On-chip ROM H'07FFF H'7FFFF Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 H'EE000 H'EE0FF Internal I/O registers (1) On-chip RAM H'FFF00 8-bit absolute addresses 16-bit absolute addresses H'FFBF1F H'FFBF20 On-chip RAM*1 H'FFFF00 H'FFFF1F H'FFFF20 H'FFFFE9 H'FFFFEA Internal I/O registers (2) External address space H'FFF1F H'FFF20 H'FFFE9 Internal I/O registers(2) H'FFFFF H'FFFFFF Note: *1 External addresses can be accessed by disabling on-chip RAM. *2 User cannot use the address area from H'FF7000 to H'FF7FFF in 16-Mbyte address mode because this address area (H'FF7000 to H'FF7FFF ) is used by the E10T. Figure 3.1(2) H8/3029 Memory Map in Each Operating Mode (EMC = 1) Rev. 2.0, 06/04, page 69 of 980 8-bit absolute addresses H'FBF20 16-bit absolute addresses Internal I/O registers (1) H'F8000 16-bit absolute addresses Vector area Vector area Memory-indirect branch addresses H'000000 Modes 1 and 2 (1-Mbyte expanded modes with on-chip ROM disabled) Modes 3 and 4 (16-Mbyte expanded modes with on-chip ROM disabled) Memory-indirect branch addresses Memory-indirect branch addresses Area 0 Area 1 Area 2 Area 4 Area 5 Area 6 Area 7 H'000FF 16-bit absolute addresses Vector area Vector area H'0000FF H'07FFF H'007FFF H'1FFFF H'20000 H'3FFFF H'40000 H'5FFFF H'60000 H'7FFFF H'80000 H'9FFFF H'A0000 H'BFFFF H'C0000 H'DFFFF H'E0000 H'EE000 Area 0 Area 1 Area 2 External address space H'1FFFFF H'200000 H'3FFFFF H'400000 H'5FFFFF H'600000 External address Area 3 space H'7FFFFF H'800000 H'9FFFFF H'A00000 H'BFFFFF H'C00000 Area 3 Area 4 Area 5 Area 6 Area 7 Internal I/O registers (1) H'EE0FF H'F8000 External address space On-chip RAM* H'FFE7F H'FFE80 Internal I/O registers (2) 16-bit absolute addresses H'FBEDF H'FBEE0 H'DFFFFF H'E00000 H'FEE000 H'FEE0FF H'FF8000 H'FFBEDF H'FFBEE0 On-chip RAM* Internal I/O registers (2) H'FFFEFF H'FFFF00 External address space H'FFFF7F H'FFFF80 On-chip RAM* H'FFFFDF Internal I/O H'FFFFE0 registers (3) H'FFFFFF 8-bit absolute addresses H'FFEFF H'FFF00 External address space H'FFF7F H'FFF80 On-chip RAM* H'FFFDF H'FFFE0 H'FFFFF Internal I/O registers (3) Internal I/O registers (1) External address space Note: * This area becomes external address space when on-chip RAM is disabled. Figure 3.2(1) H8/3029 Memory Map in Each Operating Mode (EMC = 0) Rev. 2.0, 06/04, page 70 of 980 8-bit absolute addresses H'FFFE7F H'FFFE80 16-bit absolute addresses 16-bit absolute addresses H'00000 H'000000 Mode 5 (16-Mbyte expanded mode with on-chip ROM enabled) Mode 7 (single-chip advanced mode) Memory-indirect branch addresses H'0000FF On-chip ROM H'007FFF H'07FFFF H'080000 H'000FF On-chip ROM H'07FFF Area 0 H'1FFFFF H'200000 Area 1 H'3FFFFF H'400000 External address Area 2 space H'5FFFFF H'600000 Area 3 H'7FFFFF H'800000 Area 4 H'9FFFFF H'A00000 Area 5 H'BFFFFF H'C00000 Area 6 H'DFFFFF H'E00000 Area 7 H'FEE000 H'FEE0FF H'FF8000 H'FFBEDF H'FFBEE0 On-chip RAM*1 Internal I/O registers (2) Internal I/O registers (1) External address space*2 H'7FFFF H'EE000 H'EE0FF H'F8000 Internal I/O registers (1) On-chip RAM*1 H'FFE7F H'FFE80 H'FFEFF H'FFF80 On-chip RAM*1 H'FFFDF H'FFFE0 H'FFFFF Internal I/O registers (3) Internal I/O registers (2) H'FFFEFF H'FFFF00 External address space H'FFFF7F H'FFFF80 On-chip RAM*1 H'FFFFDF H'FFFFE0 Internal I/O registers (3) H'FFFFFF Note: *1 This area becomes external address space when on-chip RAM is disabled. *2 User cannot use the address area from H'FF7000 to H'FF7FFF in 16-Mbyte address mode because this address area (H'FF7000 to H'FF7FFF ) is used by the E10T. Figure 3.2(2) H8/3029 Memory Map in Each Operating Mode (EMC = 0) Rev. 2.0, 06/04, page 71 of 980 8-bit absolute addresses H'FFFE7F H'FFFE80 16-bit absolute addresses 8-bit absolute addresses 16-bit absolute addresses H'FBEE0 16-bit absolute addresses Vector area Vector area Memory-indirect branch addresses 16-bit absolute addresses H'000000 H'00000 Rev. 2.0, 06/04, page 72 of 980 Section 4 Exception Handling 4.1 4.1.1 Overview Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in priority order. Trap instruction exceptions are accepted at all times in the program execution state. Table 4.1 Exception Types and Priority Start of Exception Handling Starts immediately after a low-to-high transition at the RES pin Interrupt requests are handled when execution of the current instruction or handling of the current exception is completed Priority Exception Type High Reset Interrupt Low Trap instruction (TRAPA) Started by execution of a trap instruction (TRAPA) 4.1.2 Exception Handling Operation Exceptions originate from various sources. Trap instructions and interrupts are handled as follows. 1. The program counter (PC) and condition code register (CCR) are pushed onto the stack. 2. The CCR interrupt mask bit is set to 1. 3. A vector address corresponding to the exception source is generated, and program execution starts from that address. Note: For a reset exception, steps 2 and 3 above are carried out. Rev. 2.0, 06/04, page 73 of 980 4.1.3 Exception Vector Table The exception sources are classified as shown in figure 4.1. Different vectors are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. * Reset External interrupts: NMI, IRQ 0 to IRQ5 Exception sources * Interrupts * Trap instruction Internal interrupts: 36 interrupts from on-chip supporting modules Figure 4.1 Exception Sources Rev. 2.0, 06/04, page 74 of 980 Table 4.2 Exception Vector Table Vector Address*1 Exception Source Reset Reserved for system use Vector Number 0 1 2 3 4 5 6 Advanced Mode H'0000 to H'0003 H'0004 to H'0007 H'0008 to H'000B H'000C to H'000F H'0010 to H'0013 H'0014 to H'0017 H'0018 to H'001B H'001C to H'001F H'0020 to H'0023 H'0024 to H'0027 H'0028 to H'002B H'002C to H'002F H'0030 to H'0033 H'0034 to H'0037 H'0038 to H'003B H'003C to H'003F H'0040 to H'0043 H'0044 to H'0047 H'0048 to H'004B H'004C to H'004F H'0050 to H'0053 to H'00FC to H'00FF Normal Mode*3 H'0000 to H'0001 H'0002 to H'0003 H'0004 to H'0005 H'0006 to H'0007 H'0008 to H'0009 H'000A to H'000B H'000C to H'000D H'000E to H'000F H'0010 to H'0011 H'0012 to H'0013 H'0014 to H'0015 H'0016 to H'0017 H'0018 to H'0019 H'001A to H'001B H'001C to H'001D H'001E to H'001F H'0020 to H'0021 H'0022 to H'0023 H'0024 to H'0025 H'0026 to H'0027 H'0028 to H'0029 to H'007E to H'007F External interrupt (NMI) Trap instruction (4 sources) 7 8 9 10 11 External interrupt IRQ0 External interrupt IRQ1 External interrupt IRQ2 External interrupt IRQ3 External interrupt IRQ4 External interrupt IRQ5 Reserved for system use 12 13 14 15 16 17 18 19 Internal interrupts* 2 20 to 63 Notes: *1 Lower 16 bits of the address. *2 For the internal interrupt vectors, see section 5.3.3, Interrupt Vector Table. *3 Cannot be selected in H8/3029. Rev. 2.0, 06/04, page 75 of 980 4.2 4.2.1 Reset Overview A reset is the highest-priority exception. When the RES pin goes low, all processing halts and the chip enters the reset state. A reset initializes the internal state of the CPU and the registers of the on-chip supporting modules. Reset exception handling begins when the RES pin changes from low to high. The chip can also be reset by overflow of the watchdog timer. For details see section 12, Watchdog Timer. 4.2.2 Reset Sequence The chip enters the reset state when the RES pin goes low. To ensure that the chip is reset, hold the RES pin low for at least 20 ms at power-up. To reset the chip during operation, hold the RES pin low for at least 20 system clock () cycles. See appendix D.2, Pin States at Reset, for the states of the pins in the reset state. When the RES pin goes high after being held low for the necessary time, the chip starts reset exception handling as follows. * The internal state of the CPU and the registers of the on-chip supporting modules are initialized, and the I bit is set to 1 in CCR. * The contents of the reset vector address (H'0000 to H'0003 in advanced mode, H'0000 to H'0001 in normal mode) are read, and program execution starts from the address indicated in the vector address. Note : The normal mode cannot be selected in the H8/3029 Figure 4.2 shows the reset sequence in modes 1 and 3. Figure 4.3 shows the reset sequence in modes 2 and 4. * After power is turned on, hold the RES pin low and the STBY pin high. Rev. 2.0, 06/04, page 76 of 980 Vector fetch Internal processing Prefetch of first program instruction RES Address bus (1) (3) (5) (7) (9) RD HWR , LWR (2) (4) High (6) (8) (10) Figure 4.2 Reset Sequence (Modes 1 and 3) D15 to D8 (1), (3), (5), (7) (2), (4), (6), (8) (9) (10) Address of reset vector: (1) = H'000000, (3) = H'000001, (5) = H'000002, (7) = H'000003 Start address (contents of reset exception handling vector address) Start address First instruction of program Rev. 2.0, 06/04, page 77 of 980 Note: After a reset, the wait-state controller inserts three wait states in every bus cycle. Vector fetch Internal processing Prefetch of first program instruction RES Address bus (1) (3) (5) RD HWR , LWR D15 to D0 High (2) (4) (6) (1), (3) (2), (4) (5) (6) Address of reset vector: (1) = H'000000, (3) = H'000002 Start address (contents of reset exception handling vector address) Start address First instruction of program Note: After a reset, the wait-state controller inserts three wait states in every bus cycle. Figure 4.3 Reset Sequence (Modes 2 and 4) 4.2.3 Interrupts after Reset If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. The first instruction of the program is always executed immediately after the reset state ends. This instruction should initialize the stack pointer (example: MOV.L #xx:32, SP). Rev. 2.0, 06/04, page 78 of 980 4.3 Interrupts Interrupt exception handling can be requested by seven external sources (NMI, IRQ0 to IRQ5), and 36 internal sources in the on-chip supporting modules. Figure 4.4 classifies the interrupt sources and indicates the number of interrupts of each type. The on-chip supporting modules that can request interrupts are the watchdog timer (WDT), DRAM interface, 16-bit timer, 8-bit timer, DMA controller (DMAC), serial communication interface (SCI), and A/D converter. Each interrupt source has a separate vector address. NMI is the highest-priority interrupt and is always accepted*. Interrupts are controlled by the interrupt controller. The interrupt controller can assign interrupts other than NMI to two priority levels, and arbitrate between simultaneous interrupts. Interrupt priorities are assigned in interrupt priority registers A and B (IPRA and IPRB) in the interrupt controller. Note: * NMI input is sometimes disabled when flash memory is being programmed or erased. For details see section 18.4.5 Flash Vector Address Control Register (FVACR). For details on interrupts see section 5, Interrupt Controller. NMI (1) IRQ 0 to IRQ 5 (6) WDT*1 (1) DRAM interface*2 (1) 16-bit timer (9) 8-bit timer (8) DMAC (4) SCI (12) A/D converter (1) External interrupts Interrupts Internal interrupts Notes: Numbers in parentheses are the number of interrupt sources. *1 When the watchdog timer is used as an interval timer, it generates an interrupt request at every counter overflow. *2 When the DRAM interface is used as an interval timer, it generates an interrupt request at compare match. Figure 4.4 Interrupt Sources and Number of Interrupts Rev. 2.0, 06/04, page 79 of 980 4.4 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. If the UE bit is set to 1 in the system control register (SYSCR), the exception handling sequence sets the I bit to 1 in CCR. If the UE bit is 0, the I and UI bits are both set to 1. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, which is specified in the instruction code. Rev. 2.0, 06/04, page 80 of 980 4.5 Stack Status after Exception Handling Figure 4.5 shows the stack after completion of trap instruction exception handling and interrupt exception handling. SP-4 SP-3 SP-2 SP-1 SP (ER7) Stack area SP (ER7) SP+1 SP+2 SP+3 SP+4 CCR CCR*2 PC H PC L Even address Before exception handling Pushed on stack a. Normal mode*1 After exception handling SP-4 SP-3 SP-2 SP-1 SP (ER7) Stack area SP (ER7) SP+1 SP+2 SP+3 SP+4 CCR PC E PC H PC L Even address Before exception handling Pushed on stack b. Advanced mode Legend PCE: Bits 23 to 16 of program counter (PC) PCH: Bits 15 to 8 of program counter (PC) PCL: Bits 7 to 0 of program counter (PC) CCR: Condition code register SP: Stack pointer Notes: *1 Cannot be selected in H8/3029 After exception handling *2 Ignored at return. 1. PC indicates the address of the first instruction that will be executed after return. 2. Registers must be saved in word or longword size at even addresses. Figure 4.5 Stack after Completion of Exception Handling Rev. 2.0, 06/04, page 81 of 980 4.6 Notes on Stack Usage When accessing word data or longword data, the H8/3029 regards the lowest address bit as 0. The stack should always be accessed by word access or longword access, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W Rn PUSH.L ERn (or MOV.W Rn, @-SP) (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.W Rn POP.L ERn (or MOV.W @SP+, Rn) (or MOV.L @SP+, ERn) Setting SP to an odd value may lead to a malfunction. Figure 4.6 shows an example of what happens when the SP value is odd. Rev. 2.0, 06/04, page 82 of 980 CCR SP PC SP R1L H'FFFEFA H'FFFEFB PC H'FFFEFC H'FFFEFD H'FFFEFF SP TRAPA instruction executed MOV. B R1L, @-ER7 SP set to H'FFFEFF Legend CCR: Condition code register PC: Program counter R1L: General register R1L SP: Stack pointer Data saved above SP CCR contents lost Note: The diagram illustrates modes 3 and 4. Figure 4.6 Operation when SP Value is Odd Rev. 2.0, 06/04, page 83 of 980 Rev. 2.0, 06/04, page 84 of 980 Section 5 Interrupt Controller 5.1 5.1.1 Overview Features The interrupt controller has the following features: * Interrupt priority registers (IPRs) for setting interrupt priorities Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis in interrupt priority registers A and B (IPRA and IPRB). * Three-level masking by the I and UI bits in the CPU condition code register (CCR) * Seven external interrupt pins NMI has the highest priority and is always accepted*; either the rising or falling edge can be selected. For each of IRQ0 to IRQ5, sensing of the falling edge or level sensing can be selected independently. Note: * NMI input is sometimes disabled when flash memory is being programmed or erased. For details see section 18.4.5 Flash Vector Address Control Register (FVACR). Rev. 2.0, 06/04, page 85 of 980 5.1.2 Block Diagram Figure 5.1 shows a block diagram of the interrupt controller. CPU ISCR NMI input IRQ input OVF TME . . . . . . . TEI TEIE IRQ input section ISR Priority decision logic IER IPRA, IPRB Interrupt request Vector number . . . I Interrupt controller UE SYSCR Legend ISCR: IER: ISR: IPRA: IPRB: SYSCR: IRQ sense control register IRQ enable register IRQ status register Interrupt priority register A Interrupt priority register B System control register UI CCR Figure 5.1 Interrupt Controller Block Diagram Rev. 2.0, 06/04, page 86 of 980 5.1.3 Pin Configuration Table 5.1 lists the interrupt pins. Table 5.1 Name Nonmaskable interrupt External interrupt request 5 to 0 Note: * Interrupt Pins Abbreviation I/O NMI IRQ5 to IRQ0 Function Input Nonmaskable interrupt*, rising edge or falling edge selectable Input Maskable interrupts, falling edge or level sensing selectable NMI input is sometimes disabled when flash memory is being programmed or erased. For details see section 18.4.5, Flash Vector Address Control Register (FVACR). 5.1.4 Register Configuration Table 5.2 lists the registers of the interrupt controller. Table 5.2 Address* H'EE012 H'EE014 H'EE015 H'EE016 H'EE018 H'EE019 1 Interrupt Controller Registers Name System control register IRQ sense control register IRQ enable register IRQ status register Interrupt priority register A Interrupt priority register B Abbreviation SYSCR ISCR IER ISR IPRA IPRB R/W R/W R/W R/W R/(W)* R/W R/W 2 Initial Value H'09 H'00 H'00 H'00 H'00 H'00 Notes: *1 Lower 20 bits of the address in advanced mode. *2 Only 0 can be written, to clear flags. Rev. 2.0, 06/04, page 87 of 980 5.2 5.2.1 Register Descriptions System Control Register (SYSCR) SYSCR is an 8-bit readable/writable register that controls software standby mode, selects the action of the UI bit in CCR, selects the NMI edge, and enables or disables the on-chip RAM. Only bits 3 and 2 are described here. For the other bits, see section 3.3, System Control Register (SYSCR). SYSCR is initialized to H'09 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit Initial value Read/Write 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 UE 1 R/W 2 NMIEG 0 R/W 1 SSOE 0 R/W 0 RAME 1 R/W RAM enable Software standby output port enable Standby timer select 2 to 0 Software standby NMI edge select Selects the NMI input edge User bit enable Selects whether to use the UI bit in CCR as a user bit or interrupt mask bit Rev. 2.0, 06/04, page 88 of 980 Bit 3--User Bit Enable (UE): Selects whether to use the UI bit in CCR as a user bit or an interrupt mask bit. Bit 3 UE 0 1 Description UI bit in CCR is used as interrupt mask bit UI bit in CCR is used as user bit (Initial value) Bit 2--NMI Edge Select (NMIEG): Selects the NMI input edge. Bit 2 NMIEG 0 1 Description Interrupt is requested at falling edge of NMI input Interrupt is requested at rising edge of NMI input (Initial value) 5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB) IPRA and IPRB are 8-bit readable/writable registers that control interrupt priority. Rev. 2.0, 06/04, page 89 of 980 Interrupt Priority Register A (IPRA): IPRA is an 8-bit readable/writable register in which interrupt priority levels can be set. Bit Initial value Read/Write 7 IPRA7 0 R/W 6 IPRA6 0 R/W 5 IPRA5 0 R/W 4 IPRA4 0 R/W 3 IPRA3 0 R/W 2 IPRA2 0 R/W 1 IPRA1 0 R/W 0 IPRA0 0 R/W Priority level A0 Selects the priority level of 16-bit timer channel 2 interrupt requests Priority level A1 Selects the priority level of 16-bit timer channel 1 interrupt requests Priority level A2 Selects the priority level of 16-bit timer channel 0 interrupt requests Priority level A3 Selects the priority level of WDT, DRAM interface, and A/D converter interrupt requests Priority level A4 Selects the priority level of IRQ 4 and IRQ 5 interrupt requests Priority level A5 Selects the priority level of IRQ 2 and IRQ 3 interrupt requests Priority level A6 Selects the priority level of IRQ 1 interrupt requests Priority level A7 Selects the priority level of IRQ 0 interrupt requests IPRA is initialized to H'00 by a reset and in hardware standby mode. Rev. 2.0, 06/04, page 90 of 980 Bit 7--Priority Level A7 (IPRA7): Selects the priority level of IRQ0 interrupt requests. Bit 7 IPRA7 0 1 Description IRQ0 interrupt requests have priority level 0 (low priority) IRQ0 interrupt requests have priority level 1 (high priority) (Initial value) Bit 6--Priority Level A6 (IPRA6): Selects the priority level of IRQ1 interrupt requests. Bit 6 IPRA6 0 1 Description IRQ1 interrupt requests have priority level 0 (low priority) IRQ1 interrupt requests have priority level 1 (high priority) (Initial value) Bit 5--Priority Level A5 (IPRA5): Selects the priority level of IRQ2 and IRQ3 interrupt requests. Bit 5 IPRA5 0 1 Description IRQ2 and IRQ3 interrupt requests have priority level 0 (low priority) IRQ2 and IRQ3 interrupt requests have priority level 1 (high priority) (Initial value) Bit 4--Priority Level A4 (IPRA4): Selects the priority level of IRQ4 and IRQ5 interrupt requests. Bit 4 IPRA4 0 1 Description IRQ4 and IRQ5 interrupt requests have priority level 0 (low priority) IRQ4 and IRQ5 interrupt requests have priority level 1 (high priority) (Initial value) Rev. 2.0, 06/04, page 91 of 980 Bit 3--Priority Level A3 (IPRA3): Selects the priority level of WDT, DRAM interface, and A/D converter interrupt requests. Bit 3 IPRA3 0 1 Description WDT, DRAM interface, and A/D converter interrupt requests have priority level 0 (low priority) (Initial value) WDT, DRAM interface, and A/D converter interrupt requests have priority level 1 (high priority) Bit 2--Priority Level A2 (IPRA2): Selects the priority level of 16-bit timer channel 0 interrupt requests. Bit 2 IPRA2 0 1 Description 16-bit timer channel 0 interrupt requests have priority level 0 (low priority) (Initial value) 16-bit timer channel 0 interrupt requests have priority level 1 (high priority) Bit 1--Priority Level A1 (IPRA1): Selects the priority level of 16-bit timer channel 1 interrupt requests. Bit 1 IPRA1 0 1 Description 16-bit timer channel 1 interrupt requests have priority level 0 (low priority) (Initial value) 16-bit timer channel 1 interrupt requests have priority level 1 (high priority) Bit 0--Priority Level A0 (IPRA0): Selects the priority level of 16-bit timer channel 2 interrupt requests. Bit 0 IPRA0 0 1 Description 16-bit timer channel 2 interrupt requests have priority level 0 (low priority) (Initial value) 16-bit timer channel 2 interrupt requests have priority level 1 (high priority) Rev. 2.0, 06/04, page 92 of 980 Interrupt Priority Register B (IPRB): IPRB is an 8-bit readable/writable register in which interrupt priority levels can be set. Bit Initial value Read/Write 7 IPRB7 0 R/W 6 IPRB6 0 R/W 5 IPRB5 0 R/W 4 -- 0 R/W 3 IPRB3 0 R/W 2 IPRB2 0 R/W 1 IPRB1 0 R/W 0 -- 0 R/W Reserved bit Priority level B1 Selects the priority level of SCI channel 2 interrupt requests Priority level B2 Selects the priority level of SCI channel 1 interrupt requests Priority level B3 Selects the priority level of SCI channel 0 interrupt requests Reserved bit Priority level B5 Selects the priority level of DMAC interrupt requests (channels 0 and 1) Priority level B6 Selects the priority level of 8-bit timer channel 2, 3 interrupt requests Priority level B7 Selects the priority level of 8-bit timer channel 0, 1 interrupt requests IPRB is initialized to H'00 by a reset and in hardware standby mode. Rev. 2.0, 06/04, page 93 of 980 Bit 7--Priority Level B7 (IPRB7): Selects the priority level of 8-bit timer channel 0, 1 interrupt requests. Bit 7 IPRB7 0 1 Description 8-bit timer channel 0, 1 interrupt requests have priority level 0 (low priority)(Initial value) 8-bit timer channel 0, 1 interrupt requests have priority level 1 (high priority) Bit 6--Priority Level B6 (IPRB6): Selects the priority level of 8-bit timer channel 2, 3 interrupt requests. Bit 6 IPRB6 0 1 Description 8-bit timer channel 2, 3 interrupt requests have priority level 0 (low priority)(Initial value) 8-bit timer channel 2, 3 interrupt requests have priority level 1 (high priority) Bit 5--Priority Level B5 (IPRB5): Selects the priority level of DMAC interrupt requests (channels 0 and 1). Bit 5 IPRB5 0 1 Description DMAC interrupt requests (channels 0 and 1) have priority level 0 (low priority) (Initial value) DMAC interrupt requests (channels 0 and 1) have priority level 1 (high priority) Bit 4--Reserved: This bit can be written and read, but it does not affect interrupt priority. Rev. 2.0, 06/04, page 94 of 980 Bit 3--Priority Level B3 (IPRB3): Selects the priority level of SCI channel 0 interrupt requests. Bit 3 IPRB3 0 1 Description SCI channel 0 interrupt requests have priority level 0 (low priority) SCI channel 0 interrupt requests have priority level 1 (high priority) (Initial value) Bit 2--Priority Level B2 (IPRB2): Selects the priority level of SCI channel 1 interrupt requests. Bit 2 IPRB2 0 1 Description SCI channel 1 interrupt requests have priority level 0 (low priority) SCI channel 1 interrupt requests have priority level 1 (high priority) (Initial value) Bit 1--Priority Level B1 (IPRB1): Selects the priority level of SCI channel 2 interrupt requests. Bit 1 IPRB1 0 1 Description SCI channel 2 interrupt requests have priority level 0 (low priority) SCI channel 2 interrupt requests have priority level 1 (high priority) (Initial value) Bit 0--Reserved: This bit can be written and read, but it does not affect interrupt priority. Rev. 2.0, 06/04, page 95 of 980 5.2.3 IRQ Status Register (ISR) ISR is an 8-bit readable/writable register that indicates the status of IRQ0 to IRQ5 interrupt requests. Bit Initial value Read/Write 7 -- 0 -- 6 -- 0 -- 5 IRQ5F 0 R/(W)* 4 IRQ4F 0 R/(W)* 3 IRQ3F 0 R/(W)* 2 IRQ2F 0 R/(W)* 1 IRQ1F 0 R/(W)* 0 IRQ0F 0 R/(W)* Reserved bits IRQ 5 to IRQ0 flags These bits indicate IRQ 5 to IRQ 0 interrupt request status Note: * Only 0 can be written, to clear flags. ISR is initialized to H'00 by a reset and in hardware standby mode. Bits 7 and 6--Reserved: These bits can not be modified and are always read as 0. Bits 5 to 0--IRQ5 to IRQ0 Flags (IRQ5F to IRQ0F): These bits indicate the status of IRQ5 to IRQ0 interrupt requests. Bits 5 to 0 IRQ5F to IRQ0F Description 0 [Clearing conditions] (Initial value) 0 is written in IRQnF after reading the IRQnF flag when IRQnF = 1. IRQnSC = 0, IRQn input is high, and interrupt exception handling is carried out. IRQnSC = 1 and IRQn interrupt exception handling is carried out. [Setting conditions] IRQnSC = 0 and IRQn input is low. IRQnSC = 1 and IRQn input changes from high to low. 1 Note: n = 5 to 0 Rev. 2.0, 06/04, page 96 of 980 5.2.4 IRQ Enable Register (IER) IER is an 8-bit readable/writable register that enables or disables IRQ5 to IRQ0 interrupt requests. Bit Initial value Read/Write 7 -- 0 R/W 6 -- 0 R/W 5 IRQ5E 0 R/W 4 IRQ4E 0 R/W 3 IRQ3E 0 R/W 2 IRQ2E 0 R/W 1 IRQ1E 0 R/W 0 IRQ0E 0 R/W Reserved bits IRQ 5 to IRQ0 enable These bits enable or disable IRQ 5 to IRQ 0 interrupts IER is initialized to H'00 by a reset and in hardware standby mode. Bits 7 and 6--Reserved: These bits can be written and read, but they do not enable or disable interrupts. Bits 5 to 0--IRQ5 to IRQ0 Enable (IRQ5E to IRQ0E): These bits enable or disable IRQ5 to IRQ0 interrupts. Bits 5 to 0 IRQ5E to IRQ0E Description 0 1 IRQ5 to IRQ0 interrupts are disabled IRQ5 to IRQ0 interrupts are enabled (Initial value) Rev. 2.0, 06/04, page 97 of 980 5.2.5 IRQ Sense Control Register (ISCR) ISCR is an 8-bit readable/writable register that selects level sensing or falling-edge sensing of the inputs at pins IRQ5 to IRQ0. Bit Initial value Read/Write 7 -- 0 R/W 6 -- 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC Reserved bits IRQ 5 to IRQ0 sense control These bits select level sensing or falling-edge sensing for IRQ 5 to IRQ 0 interrupts ISCR is initialized to H'00 by a reset and in hardware standby mode. Bits 7 and 6--Reserved: These bits can be written and read, but they do not select level or falling-edge sensing. Bits 5 to 0--IRQ5 to IRQ0 Sense Control (IRQ5SC to IRQ0SC): These bits select whether interrupts IRQ5 to IRQ0 are requested by level sensing of pins IRQ5 to IRQ0, or by falling-edge sensing. Bits 5 to 0 IRQ5SC to IRQ0SC Description 0 1 Interrupts are requested when IRQ5 to IRQ0 inputs are low Interrupts are requested by falling-edge input at IRQ5 to IRQ0 (Initial value) Rev. 2.0, 06/04, page 98 of 980 5.3 Interrupt Sources The interrupt sources include external interrupts (NMI, IRQ0 to IRQ5) and 36 internal interrupts. 5.3.1 External Interrupts There are seven external interrupts: NMI and IRQ0 to IRQ5. Of these, NMI, IRQ0, IRQ1, and IRQ2 can be used to exit software standby mode. NMI: NMI is the highest-priority interrupt and is always accepted, regardless of the states of the I and UI bits in CCR*. The NMIEG bit in SYSCR selects whether an interrupt is requested by the rising or falling edge of the input at the NMI pin. NMI interrupt exception handling has vector number 7. Note: * NMI input is sometimes disabled when flash memory is being programmed or erased. For details see section 18.4.5, Flash Vector Address Control Register (FVACR). IRQ0 to IRQ5 Interrupts: These interrupts are requested by input signals at pins IRQ0 to IRQ5. The IRQ0 to IRQ5 interrupts have the following features. * ISCR settings can select whether an interrupt is requested by the low level of the input at pins IRQ0 to IRQ5, or by the falling edge. * IER settings can enable or disable the IRQ0 to IRQ5 interrupts. Interrupt priority levels can be assigned by four bits in IPRA (IPRA7 to IPRA4). * The status of IRQ0 to IRQ5 interrupt requests is indicated in ISR. The ISR flags can be cleared to 0 by software. Figure 5.2 shows a block diagram of interrupts IRQ0 to IRQ5. IRQnSC IRQnF Edge/level sense circuit IRQn IRQnE S R Clear signal Q IRQn interrupt request input Note: n = 5 to 0 Figure 5.2 Block Diagram of Interrupts IRQ0 to IRQ5 Rev. 2.0, 06/04, page 99 of 980 Figure 5.3 shows the timing of the setting of the interrupt flags (IRQnF). IRQn input pin IRQnF Note: n = 5 to 0 Figure 5.3 Timing of Setting of IRQnF Interrupts IRQ0 to IRQ5 have vector numbers 12 to 17. These interrupts are detected regardless of whether the corresponding pin is set for input or output. When using a pin for external interrupt input, clear its DDR bit to 0 and do not use the pin for chip select output, refresh output, SCI input/output, or A/D external trigger input. 5.3.2 Internal Interrupts Thirty-Six internal interrupts are requested from the on-chip supporting modules. * Each on-chip supporting module has status flags for indicating interrupt status, and enable bits for enabling or disabling interrupts. * Interrupt priority levels can be assigned in IPRA and IPRB. * 16-bit timer, SCI, and A/D converter interrupt requests can activate the DMAC, in which case no interrupt request is sent to the interrupt controller, and the I and UI bits are disregarded. 5.3.3 Interrupt Vector Table Table 5.3 lists the interrupt sources, their vector addresses, and their default priority order. In the default priority order, smaller vector numbers have higher priority. The priority of interrupts other than NMI can be changed in IPRA and IPRB. The priority order after a reset is the default order shown in table 5.3. Rev. 2.0, 06/04, page 100 of 980 Table 5.3 Interrupt Sources, Vector Addresses, and Priority Vector Address*1 Vector Number Advanced Mode Normal Mode*2 7 12 13 14 15 16 17 -- Watchdog timer DRAM interface -- A/D 18 19 20 21 22 23 Interrupt Source NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 Reserved WOVI (interval timer) CMI (compare match) Reserved ADI (A/D end) IMIA0 (compare match/ input capture A0) IMIB0 (compare match/ input capture B0) OVI0 (overflow 0) Reserved IMIA1 (compare match/ inputcapture A1) IMIB1 (compare match/ input capture B1) OVI1 (overflow 1) Reserved Origin External pins IPR Priority High H'001C to H'001F H'000E to H'000F -- H'0030 to H'0033 H'0034 to H0037 H'0018 to H'0019 IPRA7 H'001A to H'001B IPRA6 H'0038 to H'003B H'001C to H'001D IPRA5 H'003C to H'003F H'001E to H'001F H'0040 to H'0043 H'0044 to H'0047 H'0020 to H'0021 H'0022 to H'0023 IPRA4 H'0048 to H'004B H'0024 to H'0025 H'004C to H'004F H'0026 to H'0027 H'0050 to H'0053 H'0054 to H'0057 H'0028 to H'0029 H'002A to H'002B IPRA3 H'0058 to H'005B H'002C to H'002D H'005C to H'005F H'002E to H'002F H'0060 to H'0063 H'0030 to H'0031 IPRA2 16-bit timer 24 channel 0 25 H'0064 to H'0067 H'0032 to H'0033 26 -- 27 H'0068 to H'006B H'0034 to H'0035 H'006C to H'006F H'0036 to H'0037 H'0070 to H'0073 H'0038 to H'0039 IPRA1 16-bit timer 28 channel 1 29 H'0074 to H'0077 H'003A to H'003B 30 -- 31 H'0078 to H'007B H'003C to H'003D H'007C to H'007F H'003E to H'003F Low Notes: *1 Lower 16 bits of the address. *2 Cannot be selected in H8/3029. Rev. 2.0, 06/04, page 101 of 980 Interrupt Source IMIA2 (compare match/ input capture A2) IMIB2 (compare match/ input capture B2) OVI2 (overflow 2) Reserved CMIA0 (compare match A0) CMIB0 (compare match B0) CMIA1/CMIB1 (compare match A1/B1) TOVI0/TOVI1 (overflow 0/1) CMIA2 (compare match A2) CMIB2 (compare match B2) CMIA3/CMIB3 (compare match A3/B3) TOVI2/TOVI3 (overflow 2/3) DEND0A DEND0B DEND1A DEND1B Reserved Origin Vector Address*1 Vector Number Advanced Mode Normal Mode*2 H'0080 to H'0083 H'0040 to H'0041 IPR IPRA0 Priority High 16-bit timer 32 channel 2 33 H'0084 to H'0087 H'0042 to H'0043 34 -- 35 H'0088 to H'008B H'0044 to H'0045 H'008C to H'008F H'0046 to H'0047 H'0090 to H'0093 H'0048 to H'0049 IPRB7 8-bit timer 36 channel 0/1 37 H'0094 to H'0097 H'004A to H'004B 38 H'0098 to H'009B H'004C to H'004D 39 8-bit timer 40 channel 2/3 41 H'009C to H'009F H'004E to H'004F H'00A0 to H'00A3 H'0050 to H'0051 IPRB6 H'00A4 to H'00A7 H'0052 to H'0053 42 H'00A8 to H'00AB H'0054 to H'0055 43 DMAC 44 45 46 47 48 49 50 51 H'00AC to H'00AF H'0056 to H'0057 H'00B0 to H'00B3 H'00B4 to H'00B7 H'00B8 to H'00BB H'00BC to H'00BF H'00C0 to H'00C3 H'00C4 to H'00C7 H'00C8 to H'00CB H'00CC to H'00CF H'0058 to H'0059 IPRB5 H'005A to H'005B H'005C to H'005D H'005E to H'005F H'0060 to H'0061 -- H'0062 to H'0063 H'0064 to H'0065 H'0066 to H'0067 -- Low Notes: *1 Lower 16 bits of the address. *2 Cannot be selected in H8/3029. Rev. 2.0, 06/04, page 102 of 980 Interrupt Source ERI0 (receive error 0) RXI0 (receive data full 0) TXI0 (transmit data empty 0) TEI0 (transmit end 0) ERI1 (receive error 1) RXI1 (receive data full 1) TXI1 (transmit data empty 1) TEI1 (transmit end 1) ERI2 (receive error 2) RXI2 (receive data full 2) TXI2 (transmit data empty 2) TEI2 (transmit end 2) Origin SCI channel 0 Vector Address*1 Vector Number Advanced Mode Normal Mode*2 52 53 54 55 H'00D0 to H'00D3 H'0068 to H'0069 H'00D4 to H'00D7 H'006A to H'006B H'00D8 to H'00DB H'006C to H'006D H'00DC to H'00DF H'006E to H'006F H'00E0 to H'00E3 H'0070 to H'0071 H'00E4 to H'00E7 H'0072 to H'0073 H'00E8 to H'00EB H'0074 to H'0075 H'00EC to H'00EF H'0076 to H'0077 H'00F0 to H'00F3 H'0078 to H'0079 H'00F4 to H'00F7 H'007A to H'007B H'00F8 to H'00FB H'007C to H'007D H'00FC to H'00FF H'007E to H'007F IPR IPRB3 Priority High SCI channel 1 56 57 58 59 IPRB2 SCI channel 2 60 61 62 63 IPRB1 Low Notes: *1 Lower 16 bits of the address. *2 Cannot be selected in H8/3029. Rev. 2.0, 06/04, page 103 of 980 5.4 5.4.1 Interrupt Operation Interrupt Handling Process The H8/3029 handles interrupts differently depending on the setting of the UE bit. When UE = 1, interrupts are controlled by the I bit. When UE = 0, interrupts are controlled by the I and UI bits. Table 5.4 indicates how interrupts are handled for all setting combinations of the UE, I, and UI bits. NMI interrupts are always accepted except in the reset and hardware standby states*. IRQ interrupts and interrupts from the on-chip supporting modules have their own enable bits. Interrupt requests are ignored when the enable bits are cleared to 0. Note: * NMI input is sometimes disabled. For details see section 18.4.5, Flash Vector Address Control Register (FVACR). Table 5.4 SYSCR UE 1 I 0 1 0 0 1 UE, I, and UI Bit Settings and Interrupt Handling CCR UI -- -- -- 0 1 Description All interrupts are accepted. Interrupts with priority level 1 have higher priority. No interrupts are accepted except NMI. All interrupts are accepted. Interrupts with priority level 1 have higher priority. NMI and interrupts with priority level 1 are accepted. No interrupts are accepted except NMI. UE = 1: Interrupts IRQ0 to IRQ5 and interrupts from the on-chip supporting modules can all be masked by the I bit in the CPU's CCR. Interrupts are masked when the I bit is set to 1, and unmasked when the I bit is cleared to 0. Interrupts with priority level 1 have higher priority. Figure 5.4 is a flowchart showing how interrupts are accepted when UE = 1. Rev. 2.0, 06/04, page 104 of 980 Program execution state No Interrupt requested? Yes Yes NMI No No Priority level 1? Yes No No Pending IRQ 0 Yes IRQ 0 No Yes IRQ 1 Yes IRQ 1 Yes No TEI2 Yes TEI2 Yes No I=0 Yes Save PC and CCR I 1 Read vector address Branch to interrupt service routine Figure 5.4 Process Up to Interrupt Acceptance when UE = 1 Rev. 2.0, 06/04, page 105 of 980 * If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. * When the interrupt controller receives one or more interrupt requests, it selects the highestpriority request, following the IPR interrupt priority settings, and holds other requests pending. If two or more interrupts with the same IPR setting are requested simultaneously, the interrupt controller follows the priority order shown in table 5.3. * The interrupt controller checks the I bit. If the I bit is cleared to 0, the selected interrupt request is accepted. If the I bit is set to 1, only NMI is accepted; other interrupt requests are held pending. * When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. * In interrupt exception handling, PC and CCR are saved to the stack area. The PC value that is saved indicates the address of the first instruction that will be executed after the return from the interrupt service routine. * Next the I bit is set to 1 in CCR, masking all interrupts except NMI. * The vector address of the accepted interrupt is generated, and the interrupt service routine starts executing from the address indicated by the contents of the vector address. UE = 0: The I and UI bits in the CPU's CCR and the IPR bits enable three-level masking of IRQ0 to IRQ5 interrupts and interrupts from the on-chip supporting modules. * Interrupt requests with priority level 0 are masked when the I bit is set to 1, and are unmasked when the I bit is cleared to 0. * Interrupt requests with priority level 1 are masked when the I and UI bits are both set to 1, and are unmasked when either the I bit or the UI bit is cleared to 0. For example, if the interrupt enable bits of all interrupt requests are set to 1, IPRA is set to H'20, and IPRB is set to H'00 (giving IRQ2 and IRQ3 interrupt requests priority over other interrupts), interrupts are masked as follows: a. If I = 0, all interrupts are unmasked (priority order: NMI > IRQ2 > IRQ3 >IRQ0 ...). b. If I = 1 and UI = 0, only NMI, IRQ2, and IRQ3 are unmasked. c. If I = 1 and UI = 1, all interrupts are masked except NMI. Rev. 2.0, 06/04, page 106 of 980 Figure 5.5 shows the transitions among the above states. I0 a. All interrupts are unmasked I 1, UI 0 b. Only NMI, IRQ 2 , and IRQ 3 are unmasked I0 Exception handling, or I 1, UI 1 UI 0 Exception handling, or UI 1 c. All interrupts are masked except NMI Figure 5.5 Interrupt Masking State Transitions (Example) Figure 5.6 is a flowchart showing how interrupts are accepted when UE = 0. * If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. * When the interrupt controller receives one or more interrupt requests, it selects the highestpriority request, following the IPR interrupt priority settings, and holds other requests pending. If two or more interrupts with the same IPR setting are requested simultaneously, the interrupt controller follows the priority order shown in table 5.3. * The interrupt controller checks the I bit. If the I bit is cleared to 0, the selected interrupt request is accepted regardless of its IPR setting, and regardless of the UI bit. If the I bit is set to 1 and the UI bit is cleared to 0, only NMI and interrupts with priority level 1 are accepted; interrupt requests with priority level 0 are held pending. If the I bit and UI bit are both set to 1, only NMI is accepted; all other interrupt requests are held pending. * When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. * In interrupt exception handling, PC and CCR are saved to the stack area. The PC value that is saved indicates the address of the first instruction that will be executed after the return from the interrupt service routine. * The I and UI bits are set to 1 in CCR, masking all interrupts except NMI. * The vector address of the accepted interrupt is generated, and the interrupt service routine starts executing from the address indicated by the contents of the vector address. Rev. 2.0, 06/04, page 107 of 980 Program execution state No Interrupt requested? Yes Yes NMI No No Priority level 1? Yes No No Pending IRQ 0 Yes IRQ 0 No Yes IRQ 1 Yes IRQ 1 Yes No TEI2 Yes TEI2 Yes No I=0 Yes No UI = 0 Yes I=0 Yes No Save PC and CCR I 1, UI 1 Read vector address Branch to interrupt service routine Figure 5.6 Process Up to Interrupt Acceptance when UE = 0 Rev. 2.0, 06/04, page 108 of 980 5.4.2 Interrupt accepted Interrupt level decision and wait for end of instruction Instruction Internal prefetch processing Stack Vector fetch Prefetch of interrupt Internal service routine processing instruction Interrupt Sequence Interrupt request signal (1) (3) (5) (7) (9) (11) (13) Address bus RD High (2) (4) (6) (8) (10) (12) (14) HWR , LWR Figure 5.7 shows the interrupt sequence in mode 2 when the program code and stack are in an external memory area accessed in two states via a 16-bit bus. Figure 5.7 Interrupt Sequence D15 to D0 (1) Instruction prefetch address (not executed; return address, same as PC contents) (2), (4) Instruction code (not executed) Instruction prefetch address (not executed) (3) SP - 2 (5) SP - 4 (7) (6), (8) PC and CCR saved to stack (9), (11) Vector address (10), (12) Starting address of interrupt service routine (contents of vector address) (13) Starting address of interrupt service routine; (13) = (10), (12) (14) First instruction of interrupt service routine Rev. 2.0, 06/04, page 109 of 980 Note: Mode 2, with program code and stack in external memory area accessed in two states via 16-bit bus. 5.4.3 Interrupt Response Time Table 5.5 indicates the interrupt response time from the occurrence of an interrupt request until the first instruction of the interrupt service routine is executed. Table 5.5 Interrupt Response Time External Memory On-Chip Memory 2* 1 8-Bit Bus 2 States 2* 1 16-Bit Bus 2 States 2* 4, 6 1 No. 1 2 Item Interrupt priority decision Maximum number of states until end of current instruction Saving PC and CCR to stack Vector fetch Instruction prefetch* Internal processing* 2 3 3 States 2* 1 3 States 2* 1 1 to 23* 5 1 to 27* * 5, 6 1 to 41* * 1 to 23* 5 1 to 25* * 4, 5 3 4 5 6 Total 4 4 4 4 19 to 41 8 8 8 4 31 to 57 12* 12* 12* 4 4 4 4 4 4 19 to 41 6* 6* 6* 4 4 4 4 4 4 43 to 83 25 to 49 Notes: *1 1 state for internal interrupts. *2 Prefetch after the interrupt is accepted and prefetch of the first instruction in the interrupt service routine. *3 Internal processing after the interrupt is accepted and internal processing after vector fetch. *4 The number of states increases if wait states are inserted in external memory access. *5 The examples of DIVXS.W Rs,ERd, MULXS.W Rs,ERd. *6 The examples of MOV.L @(d:24,ERs), ERd, MOV.L ERs,@(d:24,ERd). Rev. 2.0, 06/04, page 110 of 980 5.5 5.5.1 Usage Notes Contention between Interrupt and Interrupt-Disabling Instruction When an instruction clears an interrupt enable bit to 0 to disable the interrupt, the interrupt is not disabled until after execution of the instruction is completed. If an interrupt occurs while a BCLR, MOV, or other instruction is being executed to clear its interrupt enable bit to 0, at the instant when execution of the instruction ends the interrupt is still enabled, so its interrupt exception handling is carried out. If a higher-priority interrupt is also requested, however, interrupt exception handling for the higher-priority interrupt is carried out, and the lower-priority interrupt is ignored. This also applies to the clearing of an interrupt flag to 0. Figure 5.8 shows an example in which an IMIEA bit is cleared to 0 in the 16-bit timer's TISRA register. TISRA write cycle by CPU Internal address bus Internal write signal IMIEA IMIA exception handling TISRA address IMIA IMFA interrupt signal Figure 5.8 Contention between Interrupt and Interrupt-Disabling Instruction This type of contention will not occur if the interrupt is masked when the interrupt enable bit or flag is cleared to 0. Rev. 2.0, 06/04, page 111 of 980 5.5.2 Instructions that Inhibit Interrupts The LDC, ANDC, ORC, and XORC instructions inhibit interrupts. When an interrupt occurs, after determining the interrupt priority, the interrupt controller requests a CPU interrupt. If the CPU is currently executing one of these interrupt-inhibiting instructions, however, when the instruction is completed the CPU always continues by executing the next instruction. 5.5.3 Interrupts during EEPMOV Instruction Execution The EEPMOV.B and EEPMOV.W instructions differ in their reaction to interrupt requests. When the EEPMOV.B instruction is executing a transfer, no interrupts are accepted until the transfer is completed, not even NMI. When the EEPMOV.W instruction is executing a transfer, interrupt requests other than NMI are not accepted until the transfer is completed. If NMI is requested, NMI exception handling starts at a transfer cycle boundary. The PC value saved on the stack is the address of the next instruction. Programs should be coded as follows to allow for NMI interrupts during EEPMOV.W execution: L1: EEPMOV.W MOV.W R4,R4 BNE L1 Rev. 2.0, 06/04, page 112 of 980 Section 6 Bus Controller 6.1 Overview The H8/3029 has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily. The bus controller also has a bus arbitration function that controls the operation of the internal bus masters-the CPU, DMA controller (DMAC), and DRAM interface and can release the bus to an external device. 6.1.1 Features The features of the bus controller are listed below. * Manages external address space in area units Manages the external space as eight areas (0 to 7) of 128 kbytes in 1-Mbyte modes, or 2 Mbytes in 16-Mbyte modes Bus specifications can be set independently for each area DRAM/burst ROM interfaces can be set * Basic bus interface Chip select (CS0 to CS7) can be output for areas 0 to 7 8-bit access or 16-bit access can be selected for each area Two-state access or three-state access can be selected for each area Program wait states can be inserted for each area Pin wait insertion capability is provided * DRAM interface DRAM interface can be set for areas 2 to 5 Row address/column address multiplexed output (8/9/10 bits) 2-CAS byte access mode Burst operation (fast page mode) TP cycle insertion to secure RAS precharging time Choice of CAS-before-RAS refreshing or self-refreshing * Burst ROM interface Burst ROM interface can be set for area 0 Selection of two- or three-state burst access Rev. 2.0, 06/04, page 113 of 980 * Idle cycle insertion An idle cycle can be inserted in case of an external read cycle between different areas An idle cycle can be inserted when an external read cycle is immediately followed by an external write cycle * Bus arbitration function A built-in bus arbiter grants the bus right to the CPU, DMAC, DRAM interface, or an external bus master * Other features Refresh counter (refresh timer) can be used as interval timer Choice of two address update modes Rev. 2.0, 06/04, page 114 of 980 6.1.2 Block Diagram Figure 6.1 shows a block diagram of the bus controller. CS0 to CS7 ABWCR ASTCR BCR Internal address bus Area decoder CSCR Chip select control signals Internal signals Bus mode control signal Bus size control signal Access state control signal Internal data bus ADRCR Bus control circuit Wait request signal WAIT Internal signals CPU bus request signal DMAC bus request signal DRAM interface bus request signal CPU bus acknowledge signal DMAC bus acknowledge signal DRAM interface bus acknowledge signal Wait state controller WCRH WCRL BRCR Bus arbiter BACK BREQ DRAM interface DRAM control DRCRA DRCRB RTMCSR RTCNT Legend ABWCR ASTCR WCRH WCRL BRCR CSCR DRCRA DRCRB RTMCSR RTCNT RTCOR ADRCR BCR : Bus width control register : Access state control register : Wait control register H : Wait control register L : Bus release control register : Chip select control register : DRAM control register A : DRAM control register B : Refresh timer control/status register : Refresh timer counter : Refresh time constant register : Address control register : Bus control register RTCOR Figure 6.1 Block Diagram of Bus Controller Rev. 2.0, 06/04, page 115 of 980 6.1.3 Pin Configuration Table 6.1 summarizes the input/output pins of the bus controller. Table 6.1 Name Chip select 0 to 7 Address strobe Read High write Bus Controller Pins Abbreviation CS0 to CS7 AS RD HWR I/O Output Output Output Output Function Strobe signals selecting areas 0 to 7 Strobe signal indicating valid address output on the address bus Strobe signal indicating reading from the external address space Strobe signal indicating writing to the external address space, with valid data on the upper data bus (D15 to D8) Strobe signal indicating writing to the external address space, with valid data on the lower data bus (D7 to D0) Wait request signal for access to external three-state access areas Request signal for releasing the bus to an external device Acknowledge signal indicating release of the bus to an external device Low write LWR Output Wait Bus request Bus acknowledge WAIT BREQ BACK Input Input Output Rev. 2.0, 06/04, page 116 of 980 6.1.4 Register Configuration Table 6.2 summarizes the bus controller's registers. Table 6.2 Address* H'EE020 H'EE021 H'EE022 H'EE023 H'EE013 H'EE01F H'EE01E H'EE024 H'EE026 H'EE027 H'EE028 H'EE029 H'EE02A Notes: *1 *2 *3 *4 1 Bus Controller Registers Name Bus width control register Access state control register Wait control register H Wait control register L Bus release control register Chip select control register Address control register Bus control register DRAM control register A DRAM control register B Refresh timer control/status register Refresh timer counter Refresh time constant register Abbreviation ABWCR ASTCR WCRH WCRL BRCR CSCR ADRCR BCR DRCRA DRCRB RTMCSR RTCNT RTCOR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R(W)* R/W R/W 4 Initial Value H'FF* H'FF H'FF H'FF H'FE* H'0F H'FF H'C6 H'10 H'08 H'07 H'00 H'FF 3 2 Lower 20 bits of the address in advanced mode. In modes 2 and 4, the initial value is H'00. In modes 3 and 4, the initial value is H'EE. For Bit 7, only 0 can be written to clear the flag. Rev. 2.0, 06/04, page 117 of 980 6.2 6.2.1 Register Descriptions Bus Width Control Register (ABWCR) ABWCR is an 8-bit readable/writable register that selects 8-bit or 16-bit access for each area. Bit Modes 1, 3, 5, and 7 Modes 2 and 4 Initial value Initial value 7 ABW7 1 0 Read/Write R/W Read/Write R/W 6 ABW6 1 R/W 0 R/W 5 ABW5 1 R/W 0 R/W 4 ABW4 1 R/W 0 R/W 3 ABW3 1 R/W 0 R/W 2 ABW2 1 R/W 0 R/W 1 ABW1 1 R/W 0 R/W 0 ABW0 1 R/W 0 R/W When ABWCR contains H'FF (selecting 8-bit access for all areas), the chip operates in 8-bit bus mode: the upper data bus (D15 to D8) is valid, and port 4 is an input/output port. When at least one bit is cleared to 0 in ABWCR, the chip operates in 16-bit bus mode with a 16-bit data bus (D15 to D0). In modes 1, 3, 5, and 7, ABWCR is initialized to H'FF by a reset and in hardware standby mode. In modes 2 and 4, ABWCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 0--Area 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select 8-bit access or 16-bit access for the corresponding areas. Bits 7 to 0 ABW7 to ABW0 0 1 Description Areas 7 to 0 are 16-bit access areas Areas 7 to 0 are 8-bit access areas ABWCR specifies the data bus width of external memory areas. The data bus width of on-chip memory and registers is fixed, and does not depend on ABWCR settings. These settings are therefore meaningless in the single-chip modes (mode 7). Rev. 2.0, 06/04, page 118 of 980 6.2.2 Access State Control Register (ASTCR) ASTCR is an 8-bit readable/writable register that selects whether each area is accessed in two states or three states. Bit 7 AST7 Initial value Read/Write 1 R/W 6 AST6 1 R/W 5 AST5 1 R/W 4 AST4 1 R/W 3 AST3 1 R/W 2 AST2 1 R/W 1 AST1 1 R/W 0 AST0 1 R/W Bits selecting number of states for access to each area ASTCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 0--Area 7 to 0 Access State Control (AST7 to AST0): These bits select whether the corresponding area is accessed in two or three states. Bits 7 to 0 AST7 to AST0 0 1 Description Areas 7 to 0 are accessed in two states Areas 7 to 0 are accessed in three states (Initial value) ASTCR specifies the number of states in which external areas are accessed. On-chip memory and registers are accessed in a fixed number of states that does not depend on ASTCR settings. These settings are therefore meaningless in the single-chip modes (mode 7). When the corresponding area is designated as DRAM space by bits DRAS2 to DRAS0 in DRAM control register A (DRCRA), the number of access states does not depend on the AST bit setting. When an AST bit is cleared to 0, programmable wait insertion is not performed. 6.2.3 Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. On-chip memory and registers are accessed in a fixed number of states that does not depend on WCRH/WCRL settings. WCRH and WCRL are initialized to H'FF by a reset and in hardware standby mode. They are not initialized in software standby mode. Rev. 2.0, 06/04, page 119 of 980 WCRH Bit 7 W71 Initial value Read/Write 1 R/W 6 W70 1 R/W 5 W61 1 R/W 4 W60 1 R/W 3 W51 1 R/W 2 W50 1 R/W 1 W41 1 R/W 0 W40 1 R/W Bits 7 and 6--Area 7 Wait Control 1 and 0 (W71, W70): These bits select the number of program wait states when area 7 in external space is accessed while the AST7 bit in ASTCR is set to 1. Bit 7 W71 0 1 Bit 6 W70 0 1 0 1 Description Program wait not inserted when external space area 7 is accessed 1 program wait state inserted when external space area 7 is accessed 2 program wait states inserted when external space area 7 is accessed 3 program wait states inserted when external space area 7 is accessed (Initial value) Bits 5 and 4--Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is set to 1. Bit 5 W61 0 1 Bit 4 W60 0 1 0 1 Description Program wait not inserted when external space area 6 is accessed 1 program wait state inserted when external space area 6 is accessed 2 program wait states inserted when external space area 6 is accessed 3 program wait states inserted when external space area 6 is accessed (Initial value) Bits 3 and 2--Area 5 Wait Control 1 and 0 (W51, W50): These bits select the number of program wait states when area 5 in external space is accessed while the AST5 bit in ASTCR is set to 1. Rev. 2.0, 06/04, page 120 of 980 Bit 3 W51 0 1 Bit 2 W50 0 1 0 1 Description Program wait not inserted when external space area 5 is accessed 1 program wait state inserted when external space area 5 is accessed 2 program wait states inserted when external space area 5 is accessed 3 program wait states inserted when external space area 5 is accessed (Initial value) Bits 1 and 0--Area 4 Wait Control 1 and 0 (W41, W40): These bits select the number of program wait states when area 4 in external space is accessed while the AST4 bit in ASTCR is set to 1. Bit 1 W41 0 1 Bit 0 W40 0 1 0 1 Description Program wait not inserted when external space area 4 is accessed 1 program wait state inserted when external space area 4 is accessed 2 program wait states inserted when external space area 4 is accessed 3 program wait states inserted when external space area 4 is accessed (Initial value) WCRL Bit 7 W31 Initial value Read/Write 1 R/W 6 W30 1 R/W 5 W21 1 R/W 4 W20 1 R/W 3 W11 1 R/W 2 W10 1 R/W 1 W01 1 R/W 0 W00 1 R/W Bits 7 and 6--Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set to 1. Bit 7 W31 0 1 Bit 6 W30 0 1 0 1 Description Program wait not inserted when external space area 3 is accessed 1 program wait state inserted when external space area 3 is accessed 2 program wait states inserted when external space area 3 is accessed 3 program wait states inserted when external space area 3 is accessed (Initial value) Rev. 2.0, 06/04, page 121 of 980 Bits 5 and 4--Area 2 Wait Control 1 and 0 (W21, W20): These bits select the number of program wait states when area 2 in external space is accessed while the AST2 bit in ASTCR is set to 1. Bit 5 W21 0 1 Bit 4 W20 0 1 0 1 Description Program wait not inserted when external space area 2 is accessed 1 program wait state inserted when external space area 2 is accessed 2 program wait states inserted when external space area 2 is accessed 3 program wait states inserted when external space area 2 is accessed (Initial value) Bits 3 and 2--Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set to 1. Bit 3 W11 0 1 Bit 2 W10 0 1 0 1 Description Program wait not inserted when external space area 1 is accessed 1 program wait state inserted when external space area 1 is accessed 2 program wait states inserted when external space area 1 is accessed 3 program wait states inserted when external space area 1 is accessed (Initial value) Bits 1 and 0--Area 0 Wait Control 1 and 0 (W01, W00): These bits select the number of program wait states when area 0 in external space is accessed while the AST0 bit in ASTCR is set to 1. Bit 1 W01 0 1 Bit 0 W00 0 1 0 1 Description Program wait not inserted when external space area 0 is accessed 1 program wait state inserted when external space area 0 is accessed 2 program wait states inserted when external space area 0 is accessed 3 program wait states inserted when external space area 0 is accessed (Initial value) Rev. 2.0, 06/04, page 122 of 980 6.2.4 Bus Release Control Register (BRCR) BRCR is an 8-bit readable/writable register that enables address output on bus lines A23 to A20 and enables or disables release of the bus to an external device. Bit Modes 1, 2, and 7 Initial value 7 A23E 1 Read/Write -- 6 A22E 1 -- 1 R/W 1 R/W 5 A21E 1 -- 1 R/W 1 R/W 4 A20E 1 -- 0 -- 1 R/W 3 -- 1 -- 1 -- 1 -- 2 -- 1 -- 1 -- 1 -- 1 -- 1 -- 1 -- 1 -- 0 BRLE 0 R/W 0 R/W 0 R/W Modes Initial value 1 3 and 4 Read/Write R/W Mode 5 Initial value 1 Read/Write R/W Reserved bits Address 23 to 20 enable These bits enable PA7 to PA4 to be used for A23 to A20 address output Bus release enable Enables or disables release of the bus to an external device BRCR is initialized to H'FE in modes 1, 2, 5, and 7, and to H'EE in modes 3 and 4, by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7--Address 23 Enable (A23E): Enables PA4 to be used as the A23 address output pin. Writing 0 in this bit enables A23 output from PA4. In modes other than 3, 4, and 5, this bit cannot be modified and PA4 has its ordinary port functions. Bit 7 A23E 0 1 Description PA4 is the A23 address output pin PA4 is an input/output pin (Initial value) Bit 6--Address 22 Enable (A22E): Enables PA5 to be used as the A22 address output pin. Writing 0 in this bit enables A22 output from PA5. In modes other than 3, 4, and 5, this bit cannot be modified and PA5 has its ordinary port functions. Bit 6 A22E 0 1 Description PA5 is the A22 address output pin PA5 is an input/output pin (Initial value) Rev. 2.0, 06/04, page 123 of 980 Bit 5--Address 21 Enable (A21E): Enables PA6 to be used as the A21 address output pin. Writing 0 in this bit enables A21 output from PA6. In modes other than 3, 4, and 5, this bit cannot be modified and PA6 has its ordinary port functions. Bit 5 A21E 0 1 Description PA6 is the A21 address output pin PA6 is an input/output pin (Initial value) Bit 4--Address 20 Enable (A20E): Enables PA7 to be used as the A20 address output pin. Writing 0 in this bit enables A20 output from PA7. This bit can only be modified in mode 5. Bit 4 A20E 0 1 Description PA7 is the A20 address output pin (Initial value when in mode 3 or 4) PA7 is an input/output pin (Initial value when in mode 1, 2, 5, or 7) Bits 3 to 1--Reserved: These bits cannot be modified and are always read as 1. Bit 0--Bus Release Enable (BRLE): Enables or disables release of the bus to an external device. Bit 0 BRLE 0 1 Description The bus cannot be released to an external device BREQ and BACK can be used as input/output pins The bus can be released to an external device (Initial value) 6.2.5 Bit Bus Control Register (BCR) 7 ICIS1 6 ICIS0 1 R/W 5 4 3 2 EMC 1 R/W 1 RDEA 1 R/W 0 WAITE 0 R/W BROME BRSTS1 BRSTS0 0 R/W 0 R/W 0 R/W Initial value Read/Write 1 R/W BCR is an 8-bit readable/writable register that enables or disables idle cycle insertion, selects the address map, selects the area division unit, and enables or disables WAIT pin input. BCR is initialized to H'C6 by a reset and in hardware standby mode. It is not initialized in software standby mode. Rev. 2.0, 06/04, page 124 of 980 Bit 7--Idle Cycle Insertion 1 (ICIS1): Selects whether one idle cycle state is to be inserted between bus cycles in case of consecutive external read cycles for different areas. Bit 7 ICIS1 0 1 Description No idle cycle inserted in case of consecutive external read cycles for different areas Idle cycle inserted in case of consecutive external read cycles for different areas (Initial value) Bit 6--Idle Cycle Insertion 0 (ICIS0): Selects whether one idle cycle state is to be inserted between bus cycles in case of consecutive external read and write cycles. Bit 6 ICIS0 0 1 Description No idle cycle inserted in case of consecutive external read and write cycles Idle cycle inserted in case of consecutive external read and write cycles (Initial value) Bit 5--Burst ROM Enable (BROME): Selects whether area 0 is a burst ROM interface area. Bit 5 BROME 0 1 Description Area 0 is a basic bus interface area Area 0 is a burst ROM interface area (Initial value) Bit 4--Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycle states for the burst ROM interface. Bit 4 BRSTS1 0 1 Description Burst access cycle comprises 2 states Burst access cycle comprises 3 states (Initial value) Rev. 2.0, 06/04, page 125 of 980 Bit 3--Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a burst ROM interface burst access. Bit 3 BRSTS0 0 1 Description Max. 4 words in burst access (burst access on match of address bits above A3) (Initial value) Max. 8 words in burst access (burst access on match of address bits above A4) Bit 2--Expansion Memory Map Control (EMC): Selects either of the two memory maps. Bit 2 EMC 0 1 Description Selects the memory map shown in figure 3.2: see section 3.6, Memory Map* in Each Operating Mode Selects the memory map shown in figure 3.1: see section 3.6, Memory Map* in Each Operating Mode (Initial value) Note: * When the memory map is switched using EMC, the following area combinations in the on-chip RAM area cannot be used. (EMC bit = 1) Mode 1 or 2 (1) (2) (3) Mode 3 or 4 (1) (2) (3) Mode 5 (1) (2) (3) Mode 7 (1) (2) (3) H'FDEE0 to H'FDF1F H'FFE80 to H'FFEDF H'FFEE0 to H'FFF1F H'FFDEE0 to H'FFDF1F H'FFFE80 to H'FFFEDF H'FFFEE0 to H'FFFF1F H'FFDEE0 to H'FFDF1F H'FFFE80 to H'FFFEDF H'FFFEE0 to H'FFFF1F H'FDEE0 to H'FDF1F H'FFE80 to H'FFEDF H'FFEE0 to H'FFF1F (EMC bit = 0) H'FBEE0 to H'FBF1F H'FFF80 to H'FFFDF H'FDEE0 to H'FDF1F H'FFBEE0 to H'FFBF1F H'FFFF80 to H'FFFFDF H'FFDEE0 to H'FFDF1F H'FFBEE0 to H'FFBF1F H'FFFF80 to H'FFFFDF H'FFDEE0 to H'FFDF1F H'FBEE0 to H'FBF1F H'FFF80 to H'FFFDF H'FDEE0 to H'FDF1F Rev. 2.0, 06/04, page 126 of 980 When EMC is cleared to 0, addresses of some internal I/O registers are moved. For details, refer to appendix B.2, Addresses (EMC = 0). When the RDEA bit is 0, EMC must not be cleared to 0. Bit 1--Area Division Unit Select (RDEA): Selects the memory map area division units. This bit is valid in modes 3, 4, and 5, and is invalid in modes 1, 2, and 7. When the EMC bit is 0, RDEA must not be cleared to 0. Bit 1 RDEA 0 Description Area divisions are as follows: Area 0: 2 Mbytes Area 1: 2 Mbytes Area 2: 8 Mbytes Area 3: 2 Mbytes 1 Areas 0 to 7 are the same size (2 Mbytes) Area 4: 1.93 Mbytes Area 5: 4 kbytes Area 6: 23.75 kbytes Area 7: 22 bytes (Initial value) Bit 0--WAIT Pin Enable (WAITE): Enables or disables wait insertion by means of the WAIT pin. Bit 0 WAITE 0 1 Description WAIT pin wait input is disabled, and the WAIT pin can be used as an input/output port (Initial value) WAIT pin wait input is enabled Rev. 2.0, 06/04, page 127 of 980 6.2.6 Chip Select Control Register (CSCR) CSCR is an 8-bit readable/writable register that enables or disables output of chip select signals (CS7 to CS4). If output of a chip select signal is enabled by a setting in this register, the corresponding pin functions as a chip select signal (CS7 to CS4) output regardless of any other settings. CSCR cannot be modified in single-chip mode. Bit 7 CS7E Initial value Read/Write 0 R/W 6 CS6E 0 R/W 5 CS5E 0 R/W 4 CS4E 0 R/W 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Chip select 7 to 4 enable These bits enable or disable chip select signal output Reserved bits CSCR is initialized to H'0F by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 4--Chip Select 7 to 4 Enable (CS7E to CS4E): These bits enable or disable output of the corresponding chip select signal. Bit n CSnE 0 1 Note: n = 7 to 4 Description Output of chip select signal CSn is disabled Output of chip select signal CSn is enabled (Initial value) Bits 3 to 0--Reserved: These bits cannot be modified and are always read as 1. Rev. 2.0, 06/04, page 128 of 980 6.2.7 Bit DRAM Control Register A (DRCRA) 7 DRAS2 6 DRAS1 0 R/W 5 DRAS0 0 R/W 4 -- 1 -- 3 BE 0 R/W 2 RDM 0 R/W 1 SRFMD 0 R/W 0 RFSHE 0 R/W Initial value Read/Write 0 R/W DRCRA is an 8-bit readable/writable register that selects the areas that have a DRAM interface function, and the access mode, and enables or disables self-refreshing and refresh pin output. DRCRA is initialized to H'10 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 5--DRAM Area Select (DRAS2 to DRAS0): These bits select which of areas 2 to 5 are to function as DRAM interface areas (DRAM space) in expanded mode, and at the same time select the RAS output pin corresponding to each DRAM space. Description Bit 7 Bit 6 Bit 5 DRAS2 DRAS1 DRAS0 Area 5 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Note: * Normal Normal Normal Normal Normal DRAM space (CS5) DRAM space (CS4)* DRAM space (CS2)* Area 4 Normal Normal Normal Normal DRAM space (CS4) DRAM space (CS4) DRAM space (CS4)* DRAM space (CS2)* Area 3 Normal Normal DRAM space (CS3) DRAM space (CS2)* DRAM space (CS3) DRAM space (CS3) DRAM space (CS2)* DRAM space (CS2)* Area 2 Normal DRAM space (CS2) DRAM space (CS2) DRAM space (CS2)* DRAM space (CS2) DRAM space (CS2) DRAM space (CS2)* DRAM space (CS2)* A single CSn pin serves as a common RAS output pin for a number of areas. Unused CSn pins can be used as input/output ports. When any of bits DRAS2 to DRAS0 is set to 1 in expanded mode, it is not possible to write to DRCRB, RTMCSR, RTCNT, or RTCOR. However, 0 can be written to the CMF flag in RTMCSR to clear the flag. Rev. 2.0, 06/04, page 129 of 980 When an arbitrary value has been set in DRAS2 to DRAS0, a write of a different value other than 000 must not be performed. Bit 4--Reserved: This bit cannot be modified and is always read as 1. Bit 3--Burst Access Enable (BE): Enables or disables burst access to DRAM space. DRAM space burst access is performed in fast page mode. Bit 3 BE 0 1 Description Burst disabled (always full access) DRAM space access performed in fast page mode (Initial value) Bit 2--RAS Down Mode (RDM): Selects whether to wait for the next DRAM access with the RAS signal held low (RAS down mode), or to drive the RAS signal high again (RAS up mode), when burst access is enabled for DRAM space (BE = 1), and access to DRAM is interrupted. Caution is required when the HWR and LWR are used as the UCAS and LCAS output pins. For details, see RAS Down Mode and RAS Up Mode in section 6.5.10, Burst Operation. Bit 2 RDM 0 1 Description DRAM interface: RAS up mode selected DRAM interface: RAS down mode selected (Initial value) Bit 1--Self-Refresh Mode (SRFMD): Specifies DRAM self-refreshing in software standby mode. When any of areas 2 to 5 is designated as DRAM space, DRAM self-refreshing is possible when a transition is made to software standby mode after the SRFMD bit has been set to 1. The normal access state is restored when software standby mode is exited, regardless of the SRFMD setting. Bit 1 SRFMD 0 1 Description DRAM self-refreshing disabled in software standby mode DRAM self-refreshing enabled in software standby mode (Initial value) Rev. 2.0, 06/04, page 130 of 980 Bit 0--Refresh Pin Enable (RFSHE): Enables or disables RFSH pin refresh signal output. If areas 2 to 5 are not designated as DRAM space, this bit should not be set to 1. Bit 0 RFSHE 0 1 Description RFSH pin refresh signal output disabled (RFSH pin can be used as input/output port) RFSH pin refresh signal output enabled (Initial value) 6.2.8 Bit DRAM Control Register B (DRCRB) 7 MXC1 6 MXC0 0 R/W 5 CSEL 0 R/W 4 RCYCE 0 R/W 3 -- 1 -- 2 TPC 0 R/W 1 RCW 0 R/W 0 RLW 0 R/W Initial value Read/Write 0 R/W DRCRB is an 8-bit readable/writable register that selects the number of address multiplex column address bits for the DRAM interface, the column address strobe output pin, enabling or disabling of refresh cycle insertion, the number of precharge cycles, enabling or disabling of wait state insertion between RAS and CAS, and enabling or disabling of wait state insertion in refresh cycles. DRCRB is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in software standby mode. The settings in this register are invalid when bits DRAS2 to DRAS0 in DRCRA are all 0. Bits 7 and 6--Multiplex Control 1 and 0 (MXC1, MXC0): These bits select the row address/column address multiplexing method used on the DRAM interface. In burst operation, the row address used for comparison is determined by the setting of these bits and the bus width of the relevant area set in ABWCR. Rev. 2.0, 06/04, page 131 of 980 Bit 7 MXC1 0 Bit 6 MXC0 0 Description Column address: 8 bits Compared address: Modes 1, 2 Modes 3, 4, 5 8-bit access space 16-bit access space 8-bit access space 16-bit access space A19 to A8 A19 to A9 A23 to A8 A23 to A9 1 Column address: 9 bits Compared address: Modes 1, 2 Modes 3, 4, 5 8-bit access space 16-bit access space 8-bit access space 16-bit access space A19 to A9 A19 to A10 A23 to A9 A23 to A10 1 0 Column address: 10 bits Compared address: Modes 1, 2 Modes 3, 4, 5 8-bit access space 16-bit access space 8-bit access space 16-bit access space A19 to A10 A19 to A11 A23 to A10 A23 to A11 1 Illegal setting Bit 5--CAS Output Pin Select (CSEL): Selects the UCAS and LCAS output pins when areas 2 CAS to 5 are designated as DRAM space. Bit 5 CSEL 0 1 Description PB4 and PB5 selected as UCAS and LCAS output pins HWR and LWR selected as UCAS and LCAS output pins (Initial value) Bit 4--Refresh Cycle Enable (RCYCE): Enables or disables CAS-before-RAS refresh cycle insertion. When none of areas 2 to 5 has been designated as DRAM space, refresh cycles are not inserted regardless of the setting of this bit. Bit 4 RCYCE 0 1 Description Refresh cycles disabled DRAM refresh cycles enabled (Initial value) Rev. 2.0, 06/04, page 132 of 980 Bit 3--Reserved: This bit cannot be modified and is always read as 1. Bit 2--TP Cycle Control (TPC): Selects whether a 1-state or two-state precharge cycle (TP) is to be used for DRAM read/write cycles and CAS-before-RAS refresh cycles. The setting of this bit does not affect the self-refresh function. Bit 2 TPC 0 1 Description 1-state precharge cycle inserted 2-state precharge cycle inserted (Initial value) RAS-CAS Bit 1--RAS CAS Wait (RCW): Controls wait state (Trw) insertion between Tr and Tc1 in DRAM RAS read/write cycles. The setting of this bit does not affect refresh cycles. Bit 1 RCW 0 1 Description Wait state (Trw) insertion disabled One wait state (Trw) inserted (Initial value) Bit 0--Refresh Cycle Wait Control (RLW): Controls wait state (TRW) insertion for CAS-beforeRAS refresh cycles. The setting of this bit does not affect DRAM read/write cycles. Bit 0 RLW 0 1 Description Wait state (TRW) insertion disabled One wait state (TRW) inserted (Initial value) 6.2.9 Bit Refresh Timer Control/Status Register (RTMCSR) 7 CMF 6 CMIE 0 R/W 5 CKS2 0 R/W 4 CKS1 0 R/W 3 CKS0 0 R/W 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Initial value Read/Write 0 R(W)* RTMCSR is an 8-bit readable/writable register that selects the refresh timer counter clock. When the refresh timer is used as an interval timer, RTMCSR also enables or disables interrupt requests. Bits 7 and 6 of RTMCSR are initialized to 0 by a reset and in the standby modes. Bits 5 to 3 are initialized to 0 by a reset and in hardware standby mode; they are not initialized in software standby mode. Rev. 2.0, 06/04, page 133 of 980 Note: * Only 0 can be written to clear the flag. Bit 7--Compare Match Flag (CMF): Status flag that indicates a match between the values of RTCNT and RTCOR. Bit 7 CMF 0 Description [Clearing conditions] When the chip is reset and in standby mode Read CMF when CMF = 1, then write 0 in CMF [Setting condition] When RTCNT = RTCOR (Initial value) 1 Bit 6--Compare Match Interrupt Enable (CMIE): Enables or disables the CMI interrupt requested when the CMF flag is set to 1 in RTMCSR. The CMIE bit is always cleared to 0 when any of areas 2 to 5 is designated as DRAM space. Bit 6 CMIE 0 1 Description The CMI interrupt requested by CMF is disabled The CMI interrupt requested by CMF is enabled (Initial value) Bits 5 to 3--Refresh Counter Clock Select (CKS2 to CKS0): These bits select the clock to be input to RTCNT from among 7 clocks obtained by dividing the system clock (). When the input clock is selected with bits CKS2 to CKS0, RTCNT begins counting up. Bit 5 Bit 4 Bit 3 CKS2 CKS1 CKS0 Description 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Count operation halted /2 used as counter clock /8 used as counter clock /32 used as counter clock /128 used as counter clock /512 used as counter clock /2048 used as counter clock /4096 used as counter clock (Initial value) Bits 2 to 0--Reserved: These bits cannot be modified and are always read as 1. Rev. 2.0, 06/04, page 134 of 980 6.2.10 Bit Refresh Timer Counter (RTCNT) 7 6 5 4 3 2 1 0 Initial value Read/Write 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W RTCNT is an 8-bit readable/writable up-counter. RTCNT is incremented by an internal clock selected by bits CKS2 to CKS0 in RTMCSR. When RTCNT matches RTCOR (compare match), the CMF flag in RTMCSR is set to 1 and RTCNT is cleared to H'00. If the RCYCE bit in DRCRB is set to 1 at this time, a refresh cycle is started. Also, if the CMIE bit in RTMCSR is set to 1, a compare match interrupt (CMI) is generated. RTCNT is initialized to H'00 by a reset and in standby mode. 6.2.11 Bit Refresh Time Constant Register (RTCOR) 7 6 5 4 3 2 1 0 Initial value Read/Write 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W RTCOR is an 8-bit readable/writable register that determines the interval at which RTCNT is cleared. RTCOR and RTCNT are constantly compared. When their values match, the CMF flag is set to 1 in RTMCSR, and RTCNT is simultaneously cleared to H'00. RTCOR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software standby mode. Note: Only byte access can be used on this register. Rev. 2.0, 06/04, page 135 of 980 6.2.12 Address Control Register (ADRCR) ADRCR is an 8-bit readable/writable register that selects either address update mode 1 or address update mode 2 as the address output method. Bit 7 -- Initial value R/W 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 ADRCTL 1 R/W Reserved bits Address control Selects address update mode 1 or address update mode 2 ADRCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 1--Reserved: Read-only bits, always read as 1. Bit 0--Address Control (ADRCTL): Selects the address output method. Bit 0 ADRCTL 0 1 Description Address update mode 2 is selected Address update mode 1 is selected (Initial value) Rev. 2.0, 06/04, page 136 of 980 6.3 6.3.1 Operation Area Division The external address space is divided into areas 0 to 7. Each area has a size of 128 kbytes in the 1-Mbyte modes, or 2-Mbytes in the 16-Mbyte modes. Figure 6.2 shows a general view of the memory map. H'00000 Area 0 (128 kbytes) H'1FFFF H'20000 Area 1 (128 kbytes) H'3FFFF H'40000 Area 2 (128 kbytes) H'5FFFF H'60000 Area 3 (128 kbytes) H'7FFFF H'80000 Area 4 (128 kbytes) H'9FFFF H'A0000 Area 5 (128 kbytes) H'BFFFF H'C0000 H'DFFFF H'E0000 Area 7 (128 kbytes) H'FFFFF Area 6 (128 kbytes) H'000000 Area 0 (2 Mbytes) H'1FFFFF H'200000 Area 1 (2 Mbytes) H'3FFFFF H'400000 Area 2 (2 Mbytes) H'5FFFFF H'600000 Area 3 (2 Mbytes) H'7FFFFF H'800000 Area 4 (2 Mbytes) H'9FFFFF H'A00000 Area 5 (2 Mbytes) H'BFFFFF H'C00000 H'DFFFFF H'E00000 Area 7 (2 Mbytes) H'FFFFFF Area 6 (2 Mbytes) (a) 1-Mbyte modes (modes 1 and 2) (b) 16-Mbyte modes (modes 3, 4, and 5) Figure 6.2 Access Area Map for Each Operating Mode Chip select signals (CS0 to CS7) can be output for areas 0 to 7. The bus specifications for each area are selected in ABWCR, ASTCR, WCRH, and WCRL. In 16-Mbyte mode, the area division units can be selected with the RDEA bit in BCR. Rev. 2.0, 06/04, page 137 of 980 Area 0 2 Mbytes H'1FFFFF H'200000 Area 1 2 Mbytes H'3FFFFF H'400000 Area 2 2 Mbytes H'5FFFFF H'600000 Area 3 2 Mbytes H'7FFFFF H'800000 Area 4 2 Mbytes H'9FFFFF H'A00000 Area 5 2 Mbytes H'BFFFFF H'C00000 Area 6 2 Mbytes H'DFFFFF H'E00000 Area 7 1.93 Mbytes Area 0 2 Mbytes Area 1 2 Mbytes Area 2 8 Mbytes Area 3 2 Mbytes Area 4 1.93 Mbytes H'FEE000 On-chip registers (1) H'FEE0FF H'FEE100 Reserved 39.75 kbytes H'FF7FFF H'FF8000 H'FF8FFF H'FF9000 Area 5 4 kbytes On-chip registers (1) H'FFEF1F H'FFEF20 On-chip RAM 4 kbytes On-chip RAM 4 kbytes* H'FFFEFF H'FFFF00 H'FFFF1F H'FFFF20 On-chip registers (2) H'FFFFE9 H'FFFFEA H'FFFFFF Area 7 22 bytes (A) Memory map when RDEA = 1 Note: * Area 6 when the RAME bit is cleared. On-chip registers (2) Area 7 22 bytes (b) Memory map when RDEA = 0 Absolute address 8 bits Figure 6.3 Memory Map in 16-Mbyte Mode Rev. 2.0, 06/04, page 138 of 980 Absolute address 16 bits 2 Mbytes Area 7 67.5 kbytes Area 6 23.75 kbytes 2 Mbytes 2 Mbytes 2 Mbytes 2 Mbytes 2 Mbytes 2 Mbytes 2 Mbytes H'000000 6.3.2 Bus Specifications The external space bus specifications consist of three elements: (1) bus width, (2) number of access states, and (3) number of program wait states. The bus width and number of access states for on-chip memory and registers are fixed, and are not affected by the bus controller. Bus Width: A bus width of 8 or 16 bits can be selected with ABWCR. An area for which an 8-bit bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected functions as a16-bit access space. If all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16bit access, 16-bit bus mode is set. Number of Access States: Two or three access states can be selected with ASTCR. An area for which two-state access is selected functions as a two-state access space, and an area for which three-state access is selected functions as a three-state access space. DRAM space is accessed in four states regardless of the ASTCR settings. When two-state access space is designated, wait insertion is disabled. Number of Program Wait States: When three-state access space is designated in ASTCR, the number of program wait states to be inserted automatically is selected with WCRH and WCRL. From 0 to 3 program wait states can be selected. When ASTCR is cleared to 0 for DRAM space, a program wait (Tc1-Tc2 wait) is not inserted. Also, no program wait is inserted in burst ROM space burst cycles. Table 6.3 shows the bus specifications for each basic bus interface area. Rev. 2.0, 06/04, page 139 of 980 Table 6.3 Bus Specifications for Each Area (Basic Bus Interface) Bus Specifications (Basic Bus Interface) Bus Width 16 Access States 2 3 Program Wait States 0 0 1 2 3 8 2 3 0 0 1 2 3 ABWCR ASTCR WCRH/WCRL ABWn 0 ASTn 0 1 Wn1 -- 0 1 1 0 1 -- 0 1 Note: n = 7 to 0 Wn0 -- 0 1 0 1 -- 0 1 0 1 6.3.3 Memory Interfaces The H8/3029 memory interfaces comprise a basic bus interface that allows direct connection of ROM, SRAM, and so on; a DRAM interface that allows direct connection of DRAM; and a burst ROM interface that allows direct connection of burst ROM. The interface can be selected independently for each area. An area for which the basic bus interface is designated functions as normal space, an area for which the DRAM interface is designated functions as DRAM space, and area 0 for which the burst ROM interface is designated functions as burst ROM space. Rev. 2.0, 06/04, page 140 of 980 6.3.4 Chip Select Signals For each of areas 0 to 7, the H8/3029 can output a chip select signal (CS0 to CS7) that goes low when the corresponding area is selected in expanded mode. Figure 6.4 shows the output timing of a CSn signal. Output of CS0 to CS3: Output of CS0 to CS3 is enabled or disabled in the data direction register (DDR) of the corresponding port. In the expanded modes with on-chip ROM disabled, a reset leaves pin CS0 in the output state and pins CS1 to CS3 in the input state. To output chip select signals CS1 to CS3, the corresponding DDR bits must be set to 1. In the expanded modes with on-chip ROM enabled, a reset leaves pins CS0 to CS3 in the input state. To output chip select signals CS0 to CS3, the corresponding DDR bits must be set to 1. For details, see section 8, I/O Ports. Output of CS4 to CS7: Output of CS4 to CS7 is enabled or disabled in the chip select control register (CSCR). A reset leaves pins CS4 to CS7 in the input state. To output chip select signals CS4 to CS7, the corresponding CSCR bits must be set to 1. For details, see section 8, I/O Ports. Address External address in area n +5n CSn Figure 6.4 CS Signal Output Timing (n = 0 to 7) When the on-chip ROM, on-chip RAM, and on-chip registers are accessed, CS0 to CS7 remain high. The CSn signals are decoded from the address signals. They can be used as chip select signals for SRAM and other devices. Rev. 2.0, 06/04, page 141 of 980 6.3.5 Address Output Method The H8/3029 provides a choice of two address update methods: either the same method as in the previous H8/300H Series (address update mode 1), or a method in which address update is restricted to external space accesses or self-refresh cycles (address update mode 2). Figure 6.5 shows examples of address output in these two update modes. On-chip memory cycle External read cycle On-chip memory cycle External read cycle On-chip memory cycle Address update mode 1 Address update mode 2 RD Figure 6.5 Sample Address Output in Each Address Update Mode (Basic Bus Interface, 3-State Space) Address Update Mode 1: Address update mode 1 is compatible with the previous H8/300H Series. Addresses are always updated between bus cycles. Address Update Mode 2: In address update mode 2, address updating is performed only in external space accesses or self-refresh cycles. In this mode, the address can be retained between an external space read cycle and an instruction fetch cycle (on-chip memory) by placing the program in on-chip memory. Address update mode 2 is therefore useful when connecting a device that requires address hold time with respect to the rise of the RD strobe. Switching between address update modes 1 and 2 is performed by means of the ADRCTL bit in ADRCR. The initial value of ADRCR is the address update mode 1 setting, providing compatibility with the previous H8/300H Series. Rev. 2.0, 06/04, page 142 of 980 Cautions: When using address update modes, the following points should be noted. * When address update mode 2 is selected, the address in an internal space (on-chip memory or internal I/O) access cycle is not output externally. * In order to secure address holding with respect to the rise of RD, when address update mode 2 is used an external space read access must be completed within a single access cycle. For example, in a word access to 8-bit access space, the bus cycle is split into two as shown in figure 6.6, and so there is not a single access cycle. In this case, address holding is not guaranteed at the rise of RD between the first (even address) and second (odd address) access cycles (area inside the ellipse in the figure). External read cycle (8-bit space word access) On-chip memory cycle On-chip memory cycle Address update mode 2 RD Even address Odd address Figure 6.6 Example of Consecutive External Space Accesses in Address Update Mode 2 * When address update mode 2 is selected, in a DRAM space CAS-before-RAS (CBR) refresh cycle the previous address is retained (the area 2 start address is not output). Rev. 2.0, 06/04, page 143 of 980 6.4 6.4.1 Basic Bus Interface Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 6.3). 6.4.2 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and when accessing external space, controls whether the upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus specifications for the area being accessed (8-bit access area or 16-bit access area) and the data size. 8-Bit Access Areas: Figure 6.7 illustrates data alignment control for 8-bit access space. With 8bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of data that can be accessed at one time is one byte: a word access is performed as two byte accesses, and a longword access, as four byte accesses. Upper data bus Lower data bus D15 D 8 D7 D0 Byte size Word size 1st bus cycle 2nd bus cycle 1st bus cycle Longword size 2nd bus cycle 3rd bus cycle 4th bus cycle Figure 6.7 Access Sizes and Data Alignment Control (8-Bit Access Area) 16-Bit Access Areas: Figure 6.8 illustrates data alignment control for 16-bit access areas. With 16-bit access areas, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword access is executed as two word accesses. Rev. 2.0, 06/04, page 144 of 980 In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. The upper data bus is used for an even address, and the lower data bus for an odd address. Upper data bus Lower data bus D15 D8 D7 D0 Byte size Byte size * Even address * Odd address Word size Longword size 1st bus cycle 2nd bus cycle Figure 6.8 Access Sizes and Data Alignment Control (16-Bit Access Area) 6.4.3 Valid Strobes Table 6.4 shows the data buses used, and the valid strobes, for the access spaces. In a read, the RD signal is valid for both the upper and the lower half of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half. Rev. 2.0, 06/04, page 145 of 980 Table 6.4 Area 8-bit access area 16-bit access area Data Buses Used and Valid Strobes Access Size Read/Write Byte Read Write Byte Read Write Address -- -- Even Odd Even Odd Word Read Write -- -- HWR LWR RD HWR, LWR Valid Strobe RD HWR RD Valid Invalid Valid Undetermined data Valid Valid Upper Data Bus Lower Data Bus (D7 to D0) (D15 to D8) Valid Invalid Undetermined data Invalid Valid Undetermined data Valid Valid Valid Notes: 1. Undetermined data means that unpredictable data is output. 2. Invalid means that the bus is in the input state and the input is ignored. 6.4.4 Memory Areas The initial state of each area is basic bus interface, three-state access space. The initial bus width is selected according to the operating mode. The bus specifications described here cover basic items only, and the following sections should be referred to for further details: Sections 6.4, Basic Bus Interface, 6.5, DRAM Interface, and 6.8, Burst ROM Interface. Area 0: Area 0 includes on-chip ROM, and in ROM-disabled expansion mode, all of area 0 is external space. In ROM-enabled expansion mode, the space excluding on-chip ROM is external space. When area 0 external space is accessed, the CS0 signal can be output. Either basic bus interface or burst ROM interface can be selected for area 0. The size of area 0 is 128 kbytes in modes 1 and 2, and 2 Mbytes in modes 3, 4, and 5. Areas 1 and 6: In external expansion mode, areas 1 and 6 are entirely external space. When area 1 and 6 external space is accessed, the CS1 and CS6 pin signals respectively can be output. Only the basic bus interface can be used for areas 1 and 6. The size of areas 1 and 6 is 128 kbytes in modes 1 and 2, and 2 Mbytes in modes 3, 4, and 5. Rev. 2.0, 06/04, page 146 of 980 Areas 2 to 5: In external expansion mode, areas 2 to 5 are entirely external space. When area 2 to 5 external space is accessed, signals CS2 to CS5 can be output. Basic bus interface or DRAM interface can be selected for areas 2 to 5. With the DRAM interface, signals CS2 to CS5 are used as RAS signals. The size of areas 2 to 5 is 128 kbytes in modes 1 and 2, and 2 Mbytes in modes 3, 4, and 5. Area 7: Area 7 includes the on-chip RAM and registers. In external expansion mode, the space excluding the on-chip RAM and registers is external space. The on-chip RAM is enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes external space . When area 7 external space is accessed, the CS7 signal can be output. Only the basic bus interface can be used for the area 7 memory interface. The size of area 7 is 128 kbytes in modes 1 and 2, and 2 Mbytes in modes 3, 4, and 5. Rev. 2.0, 06/04, page 147 of 980 6.4.5 Basic Bus Control Signal Timing 8-Bit, Three-State-Access Areas Figure 6.9 shows the timing of bus control signals for an 8-bit, three-state-access area. The upper data bus (D15 to D8) is used in accesses to these areas. The LWR pin is always high. Wait states can be inserted. Bus cycle T1 Address bus External address in area n T2 T3 CSn AS RD Read access D15 to D8 D7 to D0 Valid Invalid HWR LWR Write access D15 to D8 D7 to D0 Valid Undetermined data High Note: n = 7 to 0 Figure 6.9 Bus Control Signal Timing for 8-Bit, Three-State-Access Area Rev. 2.0, 06/04, page 148 of 980 8-Bit, Two-State-Access Areas Figure 6.10 shows the timing of bus control signals for an 8-bit, two-state-access area. The upper data bus (D15 to D8) is used in accesses to these areas. The LWR pin is always high. Wait states cannot be inserted. Bus cycle T1 Address bus External address in area n T2 CSn AS RD Read access D15 to D8 D7 to D0 Valid Invalid HWR LWR Write access D15 to D8 D7 to D0 Valid Undetermined data High Note: n = 7 to 0 Figure 6.10 Bus Control Signal Timing for 8-Bit, Two-State-Access Area Rev. 2.0, 06/04, page 149 of 980 16-Bit, Three-State-Access Areas Figures 6.11 to 6.13 show the timing of bus control signals for a 16-bit, three-state-access area. In these areas, the upper data bus (D15 to D8) is used in accesses to even addresses and the lower data bus (D7 to D0) in accesses to odd addresses. Wait states can be inserted. Bus cycle T1 Address bus CSn AS RD Read access D15 to D8 D7 to D0 HWR LWR Write access D15 to D8 D7 to D0 Valid Undetermined data High Valid Invalid Even external address in area n T2 T3 Note: n = 7 to 0 Figure 6.11 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (1) (Byte Access to Even Address) Rev. 2.0, 06/04, page 150 of 980 Bus cycle T1 Address bus CSn AS RD Read access D15 to D8 D7 to D0 HWR LWR Write access D15 to D8 D7 to D0 Undetermined data Valid High Invalid Valid Odd external address in area n T2 T3 Note: n = 7 to 0 Figure 6.12 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (2) (Byte Access to Odd Address) Rev. 2.0, 06/04, page 151 of 980 Bus cycle T1 Address bus CSn AS RD Read access D15 to D8 D7 to D0 HWR LWR Write access D15 to D8 D7 to D0 Valid Valid Valid Valid External address in area n T2 T3 Note: n = 7 to 0 Figure 6.13 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (3) (Word Access) Rev. 2.0, 06/04, page 152 of 980 16-Bit, Two-State-Access Areas: Figures 6.14 to 6.16 show the timing of bus control signals for a 16-bit, two-state-access area. In these areas, the upper data bus (D15 to D8) is used in accesses to even addresses and the lower data bus (D7 to D0) in accesses to odd addresses. Wait states cannot be inserted. Bus cycle T1 Address bus CSn AS RD Read access D15 to D8 D7 to D0 HWR LWR Write access D15 to D8 D7 to D0 Valid Undetermined data High Valid Invalid Even external address in area n T2 Note: n = 7 to 0 Figure 6.14 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (1) (Byte Access to Even Address) Rev. 2.0, 06/04, page 153 of 980 Bus cycle T1 Address bus CSn AS RD Read access D15 to D8 D7 to D0 HWR LWR Write access D15 to D8 D7 to D0 Undetermined data Valid High Invalid Valid Odd external address in area n T2 Note: n = 7 to 0 Figure 6.15 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (2) (Byte Access to Odd Address) Rev. 2.0, 06/04, page 154 of 980 Bus cycle T1 Address bus CSn AS RD Read access D15 to D8 D7 to D0 HWR LWR Write access D15 to D8 D7 to D0 Valid Valid Valid Valid External address in area n T2 Note: n = 7 to 0 Figure 6.16 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (3) (Word Access) 6.4.6 Wait Control When accessing external space, the H8/3029 can extend the bus cycle by inserting one or more wait states (Tw). There are two ways of inserting wait states: (1) program wait insertion and (2) pin wait insertion using the WAIT pin. Program Wait Insertion: From 0 to 3 wait states can be inserted automatically between the T2 state and T3 state on an individual area basis in three-state access space, according to the settings of WCRH and WCRL. Pin Wait Insertion: Setting the WAITE bit in BCR to 1 enables wait insertion by means of the WAIT pin. When external space is accessed in this state, a program wait is first inserted. If the WAIT pin is low at the falling edge of in the last T2 or TW state, another TW state is inserted. If the WAIT pin is held low, TW states are inserted until it goes high. Rev. 2.0, 06/04, page 155 of 980 This is useful when inserting four or more TW states, or when changing the number of TW states for different external devices. The WAITE bit setting applies to all areas. Pin waits cannot be inserted in DRAM space. Figure 6.17 shows an example of the timing for insertion of one program wait state in 3-state space. Inserted by program wait Inserted by WAIT pin T2 Tw Tw Tw T3 T1 WAIT Address bus AS RD Read access Data bus Read data HWR, LWR Write access Data bus Note: Write data indicates the timing of WAIT pin sampling. Figure 6.17 Example of Wait State Insertion Timing Rev. 2.0, 06/04, page 156 of 980 6.5 6.5.1 DRAM Interface Overview The H8/3029 is provided with a DRAM interface with functions for DRAM control signal (RAS, UCAS, LCAS, WE) output, address multiplexing, and refreshing, that direct connection of DRAM. In the expanded modes, external address space areas 2 to 5 can be designated as DRAM space accessed via the DRAM interface. A data bus width of 8 or 16 bits can be selected for DRAM space by means of a setting in ABWCR. When a 16-bit data bus width is selected, CAS is used for byte access control. In the case of x 16-bit organization DRAM, therefore, the 2-CAS type can be connected. A fast page mode is supported in addition to the normal read and write access modes. 6.5.2 DRAM Space and RAS Output Pin Settings Designation of areas 2 to 5 as DRAM space, and selection of the RAS output pin for each area designated as DRAM space, is performed by setting bits in DRCRA. Table 6.5 shows the correspondence between the settings of bits DRAS2 to DRAS0 and the selected DRAM space and RAS output pin. When an arbitrary value has been set in DRAS2 to DRAS0, a write of a different value other than 000 must not be performed. Rev. 2.0, 06/04, page 157 of 980 Table 6.5 Settings of Bits DRAS2 to DRAS0 and Corresponding DRAM Space (RAS RAS Output Pin) Area 4 Normal space Normal space Normal space Normal space DRAM space (CS4) DRAM space (CS4) DRAM space (CS4)* DRAM space (CS2)* Area 3 Normal space Normal space DRAM space (CS3) DRAM space (CS2)* DRAM space (CS3) DRAM space (CS3) DRAM space (CS2)* DRAM space (CS2)* Area 2 Normal space DRAM space (CS2) DRAM space (CS2) DRAM space (CS2)* DRAM space (CS2) DRAM space (CS2) DRAM space (CS2)* DRAM space (CS2)* DRAS2 DRAS1 DRAS0 Area 5 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Note: * Normal space Normal space Normal space Normal space Normal space DRAM space (CS5) DRAM space (CS4)* DRAM space (CS2)* A single CSn pin serves as a common RAS output pin for a number of areas. Unused CSn pins can be used as input/output ports. 6.5.3 Address Multiplexing When DRAM space is accessed, the row address and column address are multiplexed. The address multiplexing method is selected with bits MXC1 and MXC0 in DRCRB according to the number of bits in the DRAM column address. Table 6.6 shows the correspondence between the settings of MXC1 and MXC0 and the address multiplexing method. Rev. 2.0, 06/04, page 158 of 980 Table 6.6 Settings of Bits MXC1 and MXC0 and Address Multiplexing Method Column Address A23 to A13 A23 to A13 A23 to A13 A23 to A13 -- A23 to A13 A12 A11 A10 A9 DRCRB Address Pins A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 MXC1 MXC0 Bits Row address 0 0 1 1 0 1 Column address -- -- 8 bits 9 bits 10 bits Illegal setting -- A20* A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A12 A20* A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A12 A11 A20* A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 -- -- -- -- -- A8 -- A7 -- A6 -- A5 -- A4 -- A3 -- A2 -- A1 -- A0 A12 A11 A10 A9 Note: * Row address bit A20 is not multiplexed in 1-Mbyte mode. 6.5.4 Data Bus If the bit in ABWCR corresponding to an area designated as DRAM space is set to 1, that area is designated as 8-bit DRAM space; if the bit is cleared to 0, the area is designated as 16-bit DRAM space. In 16-bit DRAM space, x 16-bit organization DRAM can be connected directly. In 8-bit DRAM space the upper half of the data bus, D15 to D8, is enabled, while in 16-bit DRAM space both the upper and lower halves of the data bus, D15 to D0, are enabled. Access sizes and data alignment are the same as for the basic bus interface: see section 6.4.2, Data Size and Data Alignment. 6.5.5 Pins Used for DRAM Interface Table 6.7 shows the pins used for DRAM interfacing and their functions. Rev. 2.0, 06/04, page 159 of 980 Table 6.7 Pin PB4 PB5 HWR LWR CS2 CS3 CS4 CS5 RD P80 DRAM Interface Pins With DRAM Designated Name UCAS LCAS UCAS LCAS RAS2 RAS3 RAS4 RAS5 WE RFSH Upper column address strobe Lower column address strobe Upper column address strobe Lower column address strobe Row address strobe 2 Row address strobe 3 Row address strobe 4 Row address strobe 5 Write enable Refresh Address Data I/O Output Output Output Output Output Output Output Output Output Output Output I/O Function Upper column address strobe for DRAM space access (when CSEL = 0 in DRCRB) Lower column address strobe for DRAM space access (when CSEL = 0 in DRCRB) Upper column address strobe for DRAM space access (when CSEL = 1 in DRCRB) Lower column address strobe for DRAM space access (when CSEL = 1 in DRCRB) Row address strobe for DRAM space access Row address strobe for DRAM space access Row address strobe for DRAM space access Row address strobe for DRAM space access Write enable for DRAM space write access* Goes low in refresh cycle Row address/column address multiplexed output Data input/output pins A12 to A0 A12 to A0 D15 to D0 D15 to D0 Note: * Fixed high in a read access. 6.5.6 Basic Timing Figure 6.18 shows the basic access timing for DRAM space. The basic DRAM access timing is four states: one precharge cycle (Tp) state, one row address output cycle (Tr) state, and two column address output cycle (Tc1, Tc2) states. Unlike the basic bus interface, the corresponding bits in ASTCR control only enabling or disabling of wait insertion between Tc1 and Tc2, and do not affect the number of access states. When the corresponding bit in ASTCR is cleared to 0, wait states cannot be inserted between Tc1 and Tc2 in the DRAM access cycle. If a DRAM read/write cycle is followed by an access cycle for an external area other than DRAM space when HWR and LWR are selected as the UCAS and LCAS output pins, an idle cycle (Ti) is inserted unconditionally immediately after the DRAM access cycle. See section 6.9, Idle Cycle, for details. Rev. 2.0, 06/04, page 160 of 980 Tp Tr Tc1 Tc2 A23 to A0 Row Column AS High level CSn (RAS) (UCAS PB4 /PB5 / LCAS) RD(WE) Read access High level D15 to D0 PB4 /PB5 (UCAS / LCAS) Write access RD(WE) D15 to D0 Note: n = 2 to 5 Figure 6.18 Basic Access Timing (CSEL = 0 in DRCRB) 6.5.7 Precharge State Control In the H8/3029, provision is made for the DRAM RAS precharge time by always inserting one RAS precharge state (Tp) when DRAM space is accessed. This can be changed to two Tp states by setting the TPC bit to 1 in DRCRB. The optimum number of Tp cycles should be set according to the DRAM connected and the operating frequency of the H8/3029 chip. Figure 6.19 shows the timing when two Tp states are inserted. When the TCP bit is set to 1, two Tp states are also used for CAS-before-RAS refresh cycles. Rev. 2.0, 06/04, page 161 of 980 Tp1 Tp2 Tr Tc1 Tc2 A23 to A0 Row Column AS CSn (RAS) PB4 /PB5 (UCAS /LCAS) Read access High level RD(WE) D15 to D0 PB4 /PB5 (UCAS /LCAS) High level Write access RD(WE) D15 to D0 Note: n = 2 to 5 Figure 6.19 Timing with Two Precharge States (CSEL = 0 in DRCRB) 6.5.8 Wait Control In a DRAM access cycle, wait states can be inserted (1) between the Tr state and Tc1 state, and (2) between the Tc1 state and Tc2 state. Insertion of Trw Wait State between Tr and Tc1: One Trw state can be inserted between Tr and Tc1 by setting the RCW bit to 1 in DRCRB. Insertion of Tw Wait State(s) between Tc1 and Tc2: When the bit in ASTCR corresponding to an area designated as DRAM space is set to 1, from 0 to 3 wait states can be inserted between the Tc1 state and Tc2 state by means of settings in WCRH and WCRL. Figure 6.20 shows an example of the timing for wait state insertion. Rev. 2.0, 06/04, page 162 of 980 The settings of the RCW bit in DRCRB and of ASTCR, WCRH, and WCRL do not affect refresh cycles. Wait states cannot be inserted in a DRAM space access cycle by means of the WAIT pin. Tp Row Column Tr Trw Tc1 Tw Tw Tc2 A23 to A0 AS CSn(RAS) High level Read access PB4/PB5 (UCAS /LCAS) RD(WE) D15 to D0 High level Read data PB4/PB5 (UCAS /LCAS) Write access RD(WE) D15 to D0 Note: n = 2 to 5 Write data Figure 6.20 Example of Wait State Insertion Timing (CSEL = 0) 6.5.9 Byte Access Control and CAS Output Pin When an access is made to DRAM space designated as a 16-bit-access area in ABWCR, column address strobes (UCAS and LCAS) corresponding to the upper and lower halves of the external data bus are output. In the case of x 16-bit organization DRAM, the 2-CAS type can be connected. Either PB4 and PB5, or HWR and LWR, can be used as the UCAS and LCAS output pins, the selection being made with the CSEL bit in DRCRB. Table 6.8 shows the CSEL bit settings and corresponding output pin selections. Rev. 2.0, 06/04, page 163 of 980 When an access is made to DRAM space designated as an 8-bit-access area in ABWCR, only UCAS is output. When the entire DRAM space is designated as 8-bit-access space and CSEL = 0, PB5 can be used as an input/output port. Note that RAS down mode cannot be used when a device other than DRAM is connected to external space and HWR and LWR are used as write strobes. In this case, also, an idle cycle (Ti) is always inserted when an external access to other than DRAM space occurs after a DRAM space access. For details, see section 6.9, Idle Cycle. Table 6.8 CSEL 0 1 CSEL Settings and UCAS and LCAS Output Pins UCAS PB4 HWR LCAS PB5 LWR Figure 6.21 shows the control timing. Tp Tr Tc1 Tc2 A23 to A0 Row Column CSn (RAS) PB4(UCAS) Byte control PB5(LCAS) RD(WE) Note: n = 2 to 5 Figure 6.21 Control Timing (Upper-Byte Write Access When CSEL = 0) Rev. 2.0, 06/04, page 164 of 980 6.5.10 Burst Operation With DRAM, in addition to full access (normal access) in which data is accessed by outputting a row address for each access, a fast page mode is also provided which can be used when making a number of consecutive accesses to the same row address. This mode enables fast (burst) access of data by simply changing the column address after the row address has been output. Burst access can be selected by setting the BE bit to 1 in DRCRA. Burst Access (Fast Page Mode) Operation Timing: Figure 6.22 shows the operation timing for burst access. When there are consecutive access cycles for DRAM space, the column address and CAS signal output cycles (two states) continue as long as the row address is the same for consecutive access cycles. In burst access, too, the bus cycle can be extended by inserting wait states between Tc1 and Tc2. The wait state insertion method and timing are the same as for full access: see section 6.5.8, Wait Control, for details. The row address used for the comparison is determined by the bus width of the relevant area set in bits MXC1 and MXC0 in DRCRB, and in ABWCR. Table 6.9 shows the compared row addresses corresponding to the various settings of bits MXC1 and MXC0, and ABWCR. Tp A23 to A0 Row Column 1 High level Column 2 Tr Tc1 Tc2 Tc1 Tc2 AS CSn(RAS) PB4/PB5 (UCAS /LCAS) Read access RD(WE) D15 to D0 PB4/PB5 (UCAS/LCAS) Write access RD(WE) D15 to D0 Note: n = 2 to 5 Figure 6.22 Operation Timing in Fast Page Mode Rev. 2.0, 06/04, page 165 of 980 Table 6.9 Correspondence between Settings of MXC1 and MXC0 Bits and ABWCR, and Row Address Compared in Burst Access DRCRB ABWCR ABWn 0 1 1 1 0 1 0 1 0 1 -- 0 1 1 1 0 1 0 1 0 1 -- Bus Width 16 bits 8 bits 16 bits 8 bits 16 bits 8 bits -- 16 bits 8 bits 16 bits 8 bits 16 bits 8 bits -- Compared Row Address A19 to A9 A19 to A8 A19 to A10 A19 to A9 A19 to A11 A19 to A10 Illegal setting A23 to A9 A23 to A8 A23 to A10 A23 to A9 A23 to A11 A23 to A10 Illegal setting Operating Mode Modes 1 and 2 (1-Mbyte) MXC1 0 MXC0 0 Modes 3, 4, and 5 (16-Mbyte) 0 0 Note: n = 2 to 5 RAS Down Mode and RAS Up Mode: With DRAM provided with fast page mode, as long as accesses are to the same row address, burst operation can be continued without interruption even if accesses are not consecutive by holding the RAS signal low. * RAS Down Mode To select RAS down mode, set the BE and RDM bits to 1 in DRCRA. If access to DRAM space is interrupted and another space is accessed, the RAS signal is held low during the access to the other space, and burst access is performed if the row address of the next DRAM space access is the same as the row address of the previous DRAM space access. Figure 6.23 shows an example of the timing in RAS down mode. Rev. 2.0, 06/04, page 166 of 980 DRAM access Tp Tr Tc1 Tc2 External space access T1 T2 DRAM access Tc1 Tc2 A23 to A0 AS CSn (RAS) PB4/PB5 (UCAS/LCAS) D15 to D0 Note: n = 2 to 5 Figure 6.23 Example of Operation Timing in RAS Down Mode (CSEL = 0) When RAS down mode is selected, the conditions for an asserted RASn signal to return to the high level are as shown below. The timing in these cases is shown in figure 6.24. When DRAM space with a different row address is accessed Immediately before a CAS-before-RAS refresh cycle When the BE bit or RDM bit is cleared to 0 in DRCRA Immediately before release of the external bus Rev. 2.0, 06/04, page 167 of 980 DRAM access cycle 4)5n (a) Access to DRAM space with a different row address CBR refresh cycle 4)5n (b) CAS-before-RAS refresh cycle DRCRA write cycle 4)5n (c) BE bit or RDM bit cleared to 0 in DRCRA External bus released 4)5n (d) External bus released Note: n = 2 to 5 High-impedance RASn Figure 6.24 RAS Negation Timing when RAS Down Mode is Selected Rev. 2.0, 06/04, page 168 of 980 When RAS down mode is selected, the CAS-before-RAS refresh function provided with this DRAM interface must always be used as the DRAM refreshing method. When a refresh operation is performed, the RAS signal goes high immediately beforehand. The refresh interval setting must be made so that the maximum DRAM RAS pulse width specification is observed. When the self-refresh function is used, the RDM bit must be cleared to 0, and RAS up mode selected, before executing a SLEEP instruction in order to enter software standby mode. Select RAS down mode again after exiting software standby mode. Note that RAS down mode cannot be used when HWR and LWR are selected for UCAS and LCAS, a device other than DRAM is connected to external space, and HWR and LWR are used as write strobes. * RAS Up Mode To select RAS up mode, clear the RDM bit to 0 in DRCRA. Each time access to DRAM space is interrupted and another space is accessed, the RAS signal returns to the high level. Burst operation is only performed if DRAM space is continuous. Figure 6.25 shows an example of the timing in RAS up mode. External space access T1 T2 DRAM access Tp Tr Tc1 Tc2 DRAM access Tc1 Tc2 A23 to A0 AS CSn(RAS) PB4/PB5 (UCAS/LCAS) D15 to D0 Note: n = 2 to 5 Figure 6.25 Example of Operation Timing in RAS Up Mode Rev. 2.0, 06/04, page 169 of 980 6.5.11 Refresh Control The H8/3029 is provided with a CAS-before-RAS (CBR) function and self-refresh function as DRAM refresh control functions. CAS-Before-RAS (CBR) Refreshing: To select CBR refreshing, set the RCYCE bit to 1 in DRCRB. With CBR refreshing, RTCNT counts up using the input clock selected by bits CKS2 to CKS0 in RTMCSR, and a refresh request is generated when the count matches the value set in RTCOR (compare match). At the same time, RTCNT is reset and starts counting up again from H'00. Refreshing is thus repeated at fixed intervals determined by RTCOR and bits CKS2 to CKS0. A refresh cycle is executed after this refresh request has been accepted and the DRAM interface has acquired the bus. Set a value in bits CKS2 to CKS0 in RTCOR that will meet the refresh interval specification for the DRAM used. When RAS down mode is used, set the refresh interval so that the maximum RAS pulse width specification is met. RTCNT starts counting up when bits CKS2 to CKS0 are set. RTCNT and RTCOR settings should therefore be completed before setting bits CKS2 to CKS0. Also note that a repeat refresh request generated during a bus request, or a refresh request during refresh cycle execution, will be ignored. RTCNT operation is shown in figure 6.26, compare match timing in figure 6.27, and CBR refresh timing in figures 6.28 and 6.29. RTCNT RTCOR H'00 Refresh request Figure 6.26 RTCNT Operation Rev. 2.0, 06/04, page 170 of 980 RTCNT N H'00 RTCOR N Refresh request signal and CMF bit setting signal Figure 6.27 Compare Match Timing TRp TR1 TR2 Address bus* Area 2 start address CSn(RAS) PB4/PB5 (UCAS/LCAS) RD(WE) RFSH AS High High level Note: * In address update mode 1, the area 2 start address is output. In address update mode 2, the address in the preceding bus cycle is retained. Figure 6.28 CBR Refresh Timing (CSEL = 0, TPC = 0, RLW = 0) The basic CBS refresh cycle timing comprises three states: one RAS precharge cycle (TRP) state, and two RAS output cycle (TR1, TR2) states. Either one or two states can be selected for the RAS precharge cycle. When the TPC bit is set to 1 in DRCRB, RAS signal output is delayed by one cycle. This does not affect the timing of UCAS and LCAS output. Rev. 2.0, 06/04, page 171 of 980 Use the RLW bit in DRCRB to adjust the RAS signal width. A single refresh wait state (TRW) can be inserted between the TR1 state and TR2 state by setting the RLW bit to 1. The RLW bit setting is valid only for CBR refresh cycles, and does not affect DRAM read/write cycles. The number of states in the CBR refresh cycle is not affected by the settings in ASTCR, WCRH, or WCRL, or by the state of the WAIT pin. Figure 6.29 shows the timing when the TPC bit and RLW bit are both set to 1. TRp1 TRP2 TR1 TRW TR2 Address bus* Area 2 start address CSn(RAS) PB4/PB5 (UCAS/LCAS) RD(WE) RFSH AS High High level Note: * In address update mode 1, the area 2 start address is output. In address update mode 2, the address in the preceding bus cycle is retained. Figure 6.29 CBR Refresh Timing (CSEL = 0, TPC = 1, RLW = 1) DRAM must be refreshed immediately after powering on in order to stabilize its internal state. When using the H8/3029 CAS-before-RAS refresh function, therefore, a DRAM stabilization period should be provided by means of interrupts by another timer module, or by counting the number of times bit 7 (CMF) of RTMCSR is set, for instance, immediately after bits DRAS2 to DRAS0 have been set in DRCRA. Self-Refreshing: A self-refresh mode (battery backup mode) is provided for DRAM as a kind of standby mode. In this mode, refresh timing and refresh addresses are generated within the DRAM. The H8/3029 has a function that places the DRAM in self-refresh mode when the chip enters software standby mode. Rev. 2.0, 06/04, page 172 of 980 To use the self-refresh function, set the SRFMD bit to 1 in DRCRA. When a SLEEP instruction is subsequently executed in order to enter software standby mode, the CAS and RAS signals are output and the DRAM enters self-refresh mode, as shown in figure 6.30. When the chip exits software standby mode, CAS and RAS outputs go high. The following conditions must be observed when the self-refresh function is used: * When burst access is selected, RAS up mode must be selected before executing a SLEEP instruction in order to enter software standby mode. Therefore, if RAS down mode has been selected, the RDM bit in DRCRA must be cleared to 0 and RAS up mode selected before executing the SLEEP instruction. Select RAS down mode again after exiting software standby mode. * The instruction immediately following a SLEEP instruction must not be located in an area designated as DRAM space. The self-refresh function will not work properly unless the above conditions are observed. Software standby mode Address bus CSn(RAS) High-impedance Oscillation stabilization time PB4(UCAS) PB5(LCAS) RD(WE) RFSH Figure 6.30 Self-Refresh Timing (CSEL = 0) RFSH): Refresh Signal (RFSH A refresh signal (RFSH) that transmits a refresh cycle off-chip can be RFSH output by setting the RFSHE bit to 1 in DRCRA. RFSH output timing is shown in figures 6.28, 6.29, and 6.30. Rev. 2.0, 06/04, page 173 of 980 6.5.12 Examples of Use Examples of DRAM connection and program setup procedures are shown below. When the DRAM interface is used, check the DRAM device characteristics and choose the most appropriate method of use for that device. Connection Examples * Figure 6.31 shows typical interconnections when using two 2-CAS type 16-Mbit DRAMs using a x 16-bit organization, and the corresponding address map. The DRAMs used in this example are of the 10-bit row address x 10-bit column address type. Up to four DRAMs can be connected by designating areas 2 to 5 as DRAM space. Rev. 2.0, 06/04, page 174 of 980 H8/3029 CS2 (RAS2) CS3 (RAS3) PB4(UCAS) PB5(LCAS) RD (WE) A10-A1 D15-D0 2-CAS 16-Mbit DRAM 10-bit row address x 10-bit column address x16-bit organization RAS UCAS LCAS WE A9-A0 D15-D0 OE No.1 RAS UCAS LCAS WE No.2 A9-A0 D15-D0 OE (a) Interconnections (example) PB4 (UCAS) 15 87 PB5 (LCAS) 0 H'400000 Area 2 H'5FFFFE H'600000 Area 3 H'7FFFFE H'800000 Area 4 H'9FFFFE H'A00000 Area 5 H'BFFFFE (b) Address map Normal Normal DRAM (No.2) DRAM (No.1) CS2(RAS2) CS3(RAS3) CS4 CS5 Figure 6.31 Interconnections and Address Map for 2-CAS 16-Mbit DRAMs with x 16-Bit Organization Rev. 2.0, 06/04, page 175 of 980 * Figure 6.32 shows typical interconnections when using two 16-Mbit DRAMs using a x 8-bit organization, and the corresponding address map. The DRAMs used in this example are of the 11-bit row address x 10-bit column address type. The CS2 pin is used as the common RAS output pin for areas 2 and 3. When the DRAM address space spans a number of contiguous areas, as in this example, the appropriate setting of bits DRAS2 to DRAS0 enables a single CS pin to be used as the common RAS output pin for a number of areas, and makes it possible to directly connect large-capacity DRAM with address space that spans a maximum of four areas. Any unused CS pins (in this example, the CS3 pin) can be used as input/output ports. 2-CAS 16-Mbit DRAM 11-bit row address x 10-bit column address x8-bit organization RAS CAS WE A10-A0 D7-D0 No.1 H8/3029 CS2 (RAS2) PB4 (UCAS) PB5 (LCAS) RD (WE) A21, A10-A1 D15-D8 D7-D0 OE RAS CAS WE No.2 A10-A0 D7-D0 OE (a) Interconnections (example) PB5 PB4 (LCAS) (UCAS) 15 87 0 H'400000 Area 2 H'5FFFFE H'600000 Area 3 H'7FFFFE H'800000 Area 4 H'9FFFFE H'A00000 Area 5 H'BFFFFE 16-Mbyte mode (b) Address map Normal Normal CS4 CS5 DRAM (No.1) DRAM (No.2) CS2(RAS2) Figure 6.32 Interconnections and Address Map for 16-Mbit DRAMs with x 8-Bit Organization Rev. 2.0, 06/04, page 176 of 980 * Figure 6.33 shows typical interconnections when using two 4-Mbit DRAMs, and the corresponding address map. The DRAMs used in this example are of the 9-bit row address x 9-bit column address type. In this example, upper address decoding allows multiple DRAMs to be connected to a single area. The RFSH pin is used in this case, since both DRAMs must be refreshed simultaneously. However, note that RAS down mode cannot be used in this interconnection example. 2-CAS 4-Mbit DRAM 9-bit row address x 9-bit column address x16-bit organization RAS UCAS LCAS WE H8/3029 CS2 (RAS2) PB4 (UCAS) PB5 (LCAS) RD (WE) RFSH A19 A9-A1 D15-D0 No.1 A8-A0 D15-D0 OE RAS UCAS LCAS WE No.2 A8-A0 D15-D0 OE (a) Interconnections (example) PB4 (UCAS) 15 H'400000 DRAM (No.1) H'47FFFE H'480000 DRAM (No.2) Area 2 H'4FFFFE H'500000 Not used H'5FFFFE 16-Mbyte mode (b) Address map CS2 (RAS2) PB5 (LCAS) 87 0 Figure 6.33 Interconnections and Address Map for 2-CAS 4-Mbit DRAMs with x 16-Bit Organization Rev. 2.0, 06/04, page 177 of 980 Example of Program Setup Procedure: Figure 6.34 shows an example of the program setup procedure. Set ABWCR Set RTCOR Set bits CKS2 to CKS0 in RTMCSR Set DRCRB Set DRCRA Wait for DRAM stabilization time DRAM can be accessed Figure 6.34 Example of Setup Procedure when Using DRAM Interface 6.5.13 Usage Notes Note the following points when using the DRAM refresh function. * Refresh cycles will not be executed when the external bus released state, software standby mode, or a bus cycle is extended by means of wait state insertion. Refreshing must therefore be performed by other means in these cases. * If a refresh request is generated internally while the external bus is released, the first request is retained and a single refresh cycle will be executed after the bus-released state is cleared. Figure 6.35 shows the bus cycle in this case. * When a bus cycle is extended by means of wait state insertion, the first request is retained in the same way as when the external bus has been released. * In the event of contention with a bus request from an external bus master when a transition is made to software standby mode, the BACK and strobe states may be indeterminate after the transition to software standby mode (see figure 6.36). Rev. 2.0, 06/04, page 178 of 980 When software standby mode is used, the BRLE bit should be cleared to 0 in BRCR before executing the SLEEP instruction. Similar contention in a transition to self-refresh mode may prevent dependable strobe waveform output. This can also be avoided by clearing the BRLE bit to 0 in BRCR. * Immediately after self-refreshing is cleared, external bus release is possible during a given period until the start of a CPU cycle. Attention must be paid to the RAS state to ensure that the specification for the RAS precharge time immediately after self-refreshing is met. External bus released Refresh cycle CPU cycle Refresh cycle RFSH Refresh request BACK Figure 6.35 Bus-Released State and Refresh Cycles Software standby mode BREQ BACK Address bus Strobe Figure 6.36 Bus-Released State and Software Standby Mode Rev. 2.0, 06/04, page 179 of 980 Oscillation stabilization CPU internal cycle time on exit from software (period in which external standby mode bus can be released) CPU cycle Address @SP 4)5 +)5 Figure 6.37 Self-Refresh Clearing Rev. 2.0, 06/04, page 180 of 980 6.6 6.6.1 Interval Timer Operation When DRAM is not connected to the H8/3029 chip, the refresh timer can be used as an interval timer by clearing bits DRAS2 to DRAS0 in DRCRA to 0. After setting RTCOR, selection a clock source with bits CKS2 to CKS0 in RTMCSR, and set the CMIE bit to 1. Timing of Setting of Compare Match Flag and Clearing by Compare Match: The CMF flag in RTMCSR is set to 1 by a compare match output when the RTCOR and RTCNT values match. The compare match signal is generated in the last state in which the values match (when RTCNT is updated from the matching value to a new value). Accordingly, when RTCNT and RTCOR match, the compare match signal is not generated until the next counter clock pulse. Figure 6.38 shows the timing. RTCNT N H'00 RTCOR N Compare match signal CMF flag Figure 6.38 Timing of CMF Flag Setting Operation in Power-Down State: The interval timer operates in sleep mode. It does not operate in hardware standby mode. In software standby mode, RTCNT and RTMCSR bits 7 and 6 are initialized, but RTMCSR bits 5 to 3 and RTCOR retain their settings prior to the transition to software standby mode. Contention between RTCNT Write and Counter Clear: If a counter clear signal occurs in the T3 state of an RTCNT write cycle, clearing of the counter takes priority and the write is not performed. See figure 6.39. Rev. 2.0, 06/04, page 181 of 980 T1 T2 T3 Address bus RTCNT address Internal write signal Counter clear signal RTCNT N H'00 Figure 6.39 Contention between RTCNT Write and Clear Contention between RTCNT Write and Increment: If an increment pulse occurs in the T3 state of an RTCNT write cycle, writing takes priority and RTCNT is not incremented. See figure 6.40. T1 T2 T3 Address bus RTCNT address Internal write signal RTCNT input clock RTCNT N M Counter write data Figure 6.40 Contention between RTCNT Write and Increment Rev. 2.0, 06/04, page 182 of 980 Contention between RTCOR Write and Compare Match: If a compare match occurs in the T3 state of an RTCOR write cycle, writing takes priority and the compare match signal is inhibited. See figure 6.41. T1 T2 T3 Address bus RTCOR address Internal write signal RTCNT N N+1 RTCOR N M RTCOR write data Compare match signal Inhibited Figure 6.41 Contention between RTCOR Write and Compare Match RTCNT Operation at Internal Clock Source Switchover: Switching internal clock sources may cause RTCNT to increment, depending on the switchover timing. Table 6.10 shows the relation between the time of the switchover (by writing to bits CKS2 to CKS0) and the operation of RTCNT. The RTCNT input clock is generated from the internal clock source by detecting the falling edge of the internal clock. If a switchover is made from a high clock source to a low clock source, as in case No. 3 in table 6.10, the switchover will be regarded as a falling edge, an RTCNT clock pulse will be generated, and RTCNT will be incremented. Rev. 2.0, 06/04, page 183 of 980 Table 6.10 Internal Clock Switchover and RTCNT Operation No. CKS2 to CKS0 Write Timing Low Low switchover*1 RTCNT Operation 1 Old clock source New clock source RTCNT clock RTCNT N N+1 CKS bits rewritten 2 Low High switchover*2 Old clock source New clock source RTCNT clock RTCNT N N+1 N+2 CKS bits rewritten Rev. 2.0, 06/04, page 184 of 980 No. CKS2 to CKS0 Write Timing High Low switchover*3 RTCNT Operation 3 Old clock source New clock source *4 RTCNT clock RTCNT N N+1 N+2 CKS bits rewritten 4 High High switchover*4 Old clock source New clock source RTCNT clock RTCNT N N+1 N+2 CKS bits rewritten Notes: *1 *2 *3 *4 Including switchovers from a low clock source to the halted state, and from the halted state to a low clock source. Including switchover from the halted state to a high clock source. Including switchover from a high clock source to the halted state. The switchover is regarded as a falling edge, causing RTCNT to increment. Rev. 2.0, 06/04, page 185 of 980 6.7 Interrupt Sources Compare match interrupts (CMI) can be generated when the refresh timer is used as an interval timer. Compare match interrupt requests are masked/unmasked with the CMIE bit in RTMCSR. 6.8 6.8.1 Burst ROM Interface Overview With the H8/3029, external space area 0 can be designated as burst ROM space, and burst ROM space interfacing can be performed. The burst ROM space interface enables 16-bit organization ROM with burst access capability to be accessed at high speed. Area 0 is designated as burst ROM space by means of the BROME bit in BCR. Continuous burst access of a maximum or four or eight words can be performed on external space area 0. Two or three states can be selected for burst access. 6.8.2 Basic Timing The number of states in the initial cycle (full access) and a burst cycle of the burst ROM interface is determined by the setting of the AST0 bit in ASTCR. When the AST0 bit is set to 1, wait states can also be inserted in the initial cycle. Wait states cannot be inserted in a burst cycle. Burst access of up to four words is performed when the BRSTS0 bit is cleared to 0 in BCR, and burst access of up to eight words when the BRSTS0 bit is set to 1. The number of burst access states is two when the BRSTS1 bit is cleared to 0, and three when the BRSTS1 bit is set to 1. The basic access timing for burst ROM space is shown in figure 6.42. Rev. 2.0, 06/04, page 186 of 980 Full access T1 T2 T3 T1 Burst access T2 T1 T2 Address bus Only lower address changes +50 )5 4, Data bus Read data Read data Read data Figure 6.42 Example of Burst ROM Access Timing 6.8.3 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) of the burst ROM interface. Wait states cannot be inserted in a burst cycle. Rev. 2.0, 06/04, page 187 of 980 6.9 6.9.1 Idle Cycle Operation When the H8/3029 chip accesses external space, it can insert a 1-state idle cycle (TI) between bus cycles in the following cases: (1) when read accesses between different areas occur consecutively, (2) when a write cycle occurs immediately after a read cycle, and (3) immediately after a DRAM space access. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM, which has a long output floating time, and high-speed memory, I/O interfaces, and so on. The ICIS1 and ICIS0 bits in BCR both have an initial value of 1, so that an idle cycle is inserted in the initial state. If there are no data collisions, the ICIS bits can be cleared. Consecutive Reads between Different Areas: If consecutive reads between different areas occur while the ICIS1 bit is set to 1 in BCR, an idle cycle is inserted at the start of the second read cycle. Figure 6.43 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM, each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted, and a data collision is prevented. Bus cycle A Bus cycle B Address bus T1 T2 T3 T1 T2 Address bus Bus cycle A Bus cycle B T1 T2 T3 Ti T1 T2 4, Data bus Long buffer-off time (a) Idle cycle not inserted Data collision 4, Data bus (b) Idle cycle inserted Figure 6.43 Example of Idle Cycle Operation (1) (ICIS1 = 1) Write after Read: If an external write occurs after an external read while the ICIS0 bit is set to 1 in BCR, an idle cycle is inserted at the start of the write cycle. Figure 6.44 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. Rev. 2.0, 06/04, page 188 of 980 In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented. Bus cycle A Bus cycle B Address bus T1 T2 T3 T1 T2 Address bus Bus cycle A Bus cycle B T1 T2 T3 Ti T1 T2 4, 094 Data bus Long buffer-off time (a) Idle cycle not inserted Data collision 4, 094 Data bus (b) Idle cycle inserted Figure 6.44 Example of Idle Cycle Operation (2) (ICIS0 = 1) External Address Space Access Immediately after DRAM Space Access: If a DRAM space access is followed by a non-DRAM external access when HWR and LWR have been selected as the UCAS and LCAS output pins by means of the CSEL bit in DRCRB, a Ti cycle is inserted regardless of the settings of bits ICIS0 and ICIS1 in BCR. Figure 6.45 shows an example of the operation. This is done to prevent simultaneous changing of the HWR and LWR signals used as UCAS and LCAS in DRAM space and CSn for the space in the next cycle, and so avoid an erroneous write to the external device in the next cycle. A Ti cycle is not inserted when PB4 and PB5 have been selected as the UCAS and LCAS output pins. In the case of consecutive DRAM space access precharge cycles (Tp), the ICIS0 bit settings are invalid. In the case of consecutive reads between different areas, for example, if the second access is a DRAM access, only a Tp cycle is inserted, and a Ti cycle is not. The timing in this case is shown in figure 6.46. Rev. 2.0, 06/04, page 189 of 980 Bus cycle A (DRAM access cycle) Bus cycle B Address bus Tp Tr Tc1 Tc2 T1 T2 Address bus Bus cycle A (DRAM access cycle) Bus cycle B Tp Tr Tc1 Tc2 Ti T1 T2 HWR/LWR (UCAS/LCAS) HWR/LWR (UCAS/LCAS) CSn Simultaneous change of HWR/LWR and CSn (a) Idle cycle not inserted CSn (b) Idle cycle inserted HWR/LWR UCAS/LCAS LCAS) Figure 6.45 Example of Idle Cycle Operation (3) (HWR LWR Used as UCAS LCAS HWR External read T1 Address bus T2 T3 DRAM space read Tp Tr Tc1 Tc2 RD UCAS/LCAS Address bus Figure 6.46 Example of Idle Cycle Operation (4) (Consecutive Precharge Cycles) Usage Notes: When non-insertion of idle cycles is set, the rise (negation) of RD and the fall (assertion) of CSn may occur simultaneously. An example of the operation is shown in figure 6.47. If consecutive reads between different external areas occur while the ICIS1 bit is cleared to 0 in BCR, or if a write cycle to a different external area occurs after an external read while the ICIS0 bit is cleared to 0, the RD negation in the first read cycle and the CSn assertion in the following bus cycle will occur simultaneously. Therefore, depending on the output delay time of each signal, it is possible that the low-level output of RD in the preceding read cycle and the low-level output of CSn in the following bus cycle will overlap. A setting whereby idle cycle insertion is not performed can be made only when RD and CSn do not change simultaneously, or when it does not matter if they do. Rev. 2.0, 06/04, page 190 of 980 Bus cycle A Address bus T1 T2 T3 Bus cycle B T1 T2 Address bus Bus cycle A T1 T2 T3 Bus cycle B Ti T1 T2 RD CSn Simultaneous change of RD and CSn Possibility of mutual overlap (a) Idle cycle not inserted RD CSn (b) Idle cycle inserted Figure 6.47 Example of Idle Cycle Operation (5) 6.9.2 Pin States in Idle Cycle Table 6.11 shows the pin states in an idle cycle. Table 6.11 Pin States in Idle Cycle Pins A23 to A0 D15 to D0 CSn UCAS, LCAS AS RD HWR LWR Note: * Pin State Next cycle address value High impedance High* High High High High High Remains low in DRAM space RAS down mode. Rev. 2.0, 06/04, page 191 of 980 6.10 Bus Arbiter The bus controller has a built-in bus arbiter that arbitrates between different bus masters. There are four bus masters: the CPU, DMA controller (DMAC), DRAM interface, and an external bus master. When a bus master has the bus right it can carry out read, write, or refresh access. Each bus master uses a bus request signal to request the bus right. At fixed times the bus arbiter determines priority and uses a bus acknowledge signal to grant the bus to a bus master, which can the operate using the bus. The bus arbiter checks whether the bus request signal from a bus master is active or inactive, and returns an acknowledge signal to the bus master. When two or more bus masters request the bus, the highest-priority bus master receives an acknowledge signal. The bus master that receives an acknowledge signal can continue to use the bus until the acknowledge signal is deactivated. The bus master priority order is: (High) External bus master > DRAM interface > DMAC > CPU (Low) The bus arbiter samples the bus request signals and determines priority at all times, but it does not always grant the bus immediately, even when it receives a bus request from a bus master with higher priority than the current bus master. Each bus master has certain times at which it can release the bus to a higher-priority bus master. 6.10.1 Operation CPU: The CPU is the lowest-priority bus master. If the DMAC, DRAM interface, or an external bus master requests the bus while the CPU has the bus right, the bus arbiter transfers the bus right to the bus master that requested it. The bus right is transferred at the following times: * The bus right is transferred at the boundary of a bus cycle. If word data is accessed by two consecutive byte accesses, however, the bus right is not transferred between the two byte accesses. * If another bus master requests the bus while the CPU is performing internal operations, such as executing a multiply or divide instruction, the bus right is transferred immediately. The CPU continues its internal operations. * If another bus master requests the bus while the CPU is in sleep mode, the bus right is transferred immediately. DMAC: When the DMAC receives an activation request, it requests the bus right from the bus arbiter. If the DMAC is bus master and the DRAM interface or an external bus master requests the bus, the bus arbiter transfers the bus right from the DMAC to the bus master that requested the bus. The bus right is transferred at the following times. Rev. 2.0, 06/04, page 192 of 980 The bus right is transferred when the DMAC finishes transferring one byte or one word. A DMAC transfer cycle consists of a read cycle and a write cycle. The bus right is not transferred between the read cycle and the write cycle. There is a priority order among the DMAC channels. For details see section 7.4.9, MultipleChannel Operation. DRAM Interface: The DRAM interface requests the bus right from the bus arbiter when a refresh cycle request is issued, and releases the bus at the end of the refresh cycle. For details see section 6.5, DRAM Interface. External Bus Master: When the BRLE bit is set to 1 in BRCR, the bus can be released to an external bus master. The external bus master has highest priority, and requests the bus right from the bus arbiter driving the BREQ signal low. Once the external bus master acquires the bus, it keeps the bus until the BREQ signal goes high. While the bus is released to an external bus master, the H8/3029 chip holds the address bus, data bus, bus control signals (AS, RD, HWR, and LWR), and chip select signals (CSn: n = 7 to 0) in the high-impedance state, and holds the BACK pin in the low output state. The bus arbiter samples the BREQ pin at the rise of the system clock (). If BREQ is low, the bus is released to the external bus master at the appropriate opportunity. The BREQ signal should be held low until the BACK signal goes low. When the BREQ pin is high in two consecutive samples, the BACK pin is driven high to end the bus-release cycle. Figure 6.48 shows the timing when the bus right is requested by an external bus master during a read cycle in a two-state access area. There is a minimum interval of three states from when the BREQ signal goes low until the bus is released. Rev. 2.0, 06/04, page 193 of 980 CPU cycles T0 T1 T2 External bus released CPU cycles Address bus Data bus Address High-impedance High-impedance AS RD HWR, LWR BREQ BACK Minimum 3 cycles (1) (2) (3) High High-impedance High-impedance High-impedance (4) (5) (6) Figure 6.48 Example of External Bus Master Operation In the event of contention with a bus request from an external bus master when a transition is made to software standby mode, the BACK and strobe states may be indeterminate after the transition to software standby mode (see figure 6.36). When software standby mode is used, the BRLE bit should be cleared to 0 in BRCR before executing the SLEEP instruction. Rev. 2.0, 06/04, page 194 of 980 6.11 6.11.1 Register and Pin Input Timing Register Write Timing ABWCR, ASTCR, WCRH, and WCRL Write Timing: Data written to ABWCR, ASTCR, WCRH, and WCRL takes effect starting from the next bus cycle. Figure 6.49 shows the timing when an instruction fetched from area 0 changes area 0 from three-state access to two-state access. T1 Address bus 3-state access to area 0 T2 T3 T1 T2 T3 T1 T2 ASTCR address 2-state access to area 0 Figure 6.49 ASTCR Write Timing DDR and CSCR Write Timing: Data written to DDR or CSCR for the port corresponding to the CSn pin to switch between CSn output and generic input takes effect starting from the T3 state of the DDR write cycle. Figure 6.50 shows the timing when the CS1 pin is changed from generic input to CS1 output. T1 Address bus T2 T3 P8DDR address +51 High-impedance Figure 6.50 DDR Write Timing Rev. 2.0, 06/04, page 195 of 980 BRCR Write Timing: Data written to BRCR to switch between A23, A22, A21, or A20 output and generic input or output takes effect starting from the T3 state of the BRCR write cycle. Figure 6.51 shows the timing when a pin is changed from generic input to A23, A22, A21, or A20 output. T1 Address bus PA7 to PA4 (A23 to A20) BRCR address T2 T3 High-impedance Figure 6.51 BRCR Write Timing 6.11.2 BREQ Pin Input Timing After driving the BREQ pin low, hold it low until BACK goes low. If BREQ returns to the high level before BACK goes lows, the bus arbiter may operate incorrectly. To terminate the external-bus-released state, hold the BREQ signal high for at least three states. If BREQ is high for too short an interval, the bus arbiter may operate incorrectly. Rev. 2.0, 06/04, page 196 of 980 Section 7 DMA Controller 7.1 Overview The H8/3029 has an on-chip DMA controller (DMAC) that can transfer data on up to four channels. When the DMA controller is not used, it can be independently halted to conserve power. For details see section 20.6, Module Standby Function. 7.1.1 Features DMAC features are listed below. * Selection of short address mode or full address mode Short address mode 8-bit source address and 24-bit destination address, or vice versa Maximum four channels available Selection of I/O mode, idle mode, or repeat mode Full address mode 24-bit source and destination addresses Maximum two channels available Selection of normal mode or block transfer mode * Directly addressable 16-Mbyte address space * Selection of byte or word transfer * Activation by internal interrupts, external requests, or auto-request (depending on transfer mode) 16-bit timer compare match/input capture interrupts (x3) Serial communication interface (SCI channel 0) transmit-data-empty/receive-data-full interrupts External requests Auto-request A/D converter conversion-end interrupt Rev. 2.0, 06/04, page 197 of 980 7.1.2 Block Diagram Figure 7.1 shows a DMAC block diagram. Internal address bus Internal interrupts IMIA0 IMIA1 IMIA2 ADI TXI0 RXI0 Address buffer Arithmetic-logic unit MAR0A Channel 0A Control logic Channel 0 Channel 0B DTCR0A DTCR0B DTCR1A DTCR1B Channel 1 Channel 1B Channel 1A IOAR0A MAR0B IOAR0B ETCR0B MAR1A IOAR1A ETCR1A MAR1B IOAR1B ETCR1B Interrupt DEND0A DEND0B signals DEND1A DEND1B Data buffer Internal data bus Legend DTCR: Data transfer control register MAR: Memory address register IOAR: I/O address register ETCR: Execute transfer count register Figure 7.1 Block Diagram of DMAC Rev. 2.0, 06/04, page 198 of 980 Module data bus DREQ0 DREQ1 TEND0 TEND1 ETCR0A 7.1.3 Functional Overview Table 7.1 gives an overview of the DMAC functions. Table 7.1 DMAC Functional Overview Address Reg. Length Transfer Mode Short address mode I/O mode * Transfers one byte or one word per request * Increments or decrements the memory address by 1 or 2 * Executes 1 to 65,536 transfers Idle mode * Transfers one byte or one word per request * Holds the memory address fixed * Executes 1 to 65,536 transfers Repeat mode * Transfers one byte or one word per request * Increments or decrements the memory address by 1 or 2 * Executes a specified number (1 to 255) of transfers, then returns to the initial state and continues Full address mode Activation * Source Destination 8 * * * * Compare match/input 24 capture A interrupts from 16-bit timer channels 0 to 2 Transmit-data-empty interrupt from SCI channel 0 Conversion-end interrupt from A/D converter Receive-data-full interrupt from SCI channel 0 External request 8 24 24 8 * Normal mode * * Auto-request Retains the transfer request internally Executes a specified number(1 to 65,536) of transfers continuously Selection of burst mode or cyclesteal mode * External request Transfers one byte or one word per request Executes 1 to 65,536 transfers * Block transfer * * * * Transfers one block of a specified size per request * Executes 1 to 65,536 transfers Allows either the source or destination * to be a fixed block area Block size can be 1 to 255 bytes or words Auto-request External request 24 24 Compare match/ input 24 capture A interrupts from 16-bit timer channels 0 to 2 External request Conversion-end interrupt from A/D converter 24 Rev. 2.0, 06/04, page 199 of 980 7.1.4 Input/Output Pins Table 7.2 lists the DMAC pins. Table 7.2 Channel 0 1 DMAC Pins Name DMA request 0 Transfer end 0 DMA request 1 Transfer end 1 Abbreviation DREQ0 TEND0 DREQ1 TEND1 Input/ Output Input Output Input Output Function External request for DMAC channel 0 Transfer end on DMAC channel 0 External request for DMAC channel 1 Transfer end on DMAC channel 1 Note: External requests cannot be made to channel A in short address mode. 7.1.5 Register Configuration Table 7.3 lists the DMAC registers. Rev. 2.0, 06/04, page 200 of 980 Table 7.3 DMAC Registers Abbreviation R/W MAR0AR MAR0AE MAR0AH MAR0AL IOAR0A R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined H'00 Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined H'00 Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined H'00 Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined H'00 Channel Address* Name 0 H'FFF20 H'FFF21 H'FFF22 H'FFF23 H'FFF26 H'FFF24 H'FFF25 H'FFF27 H'FFF28 H'FFF29 H'FFF2A H'FFF2B H'FFF2E H'FFF2C H'FFF2D H'FFF2F 1 H'FFF30 H'FFF31 H'FFF32 H'FFF33 H'FFF36 H'FFF34 H'FFF35 H'FFF37 H'FFF38 H'FFF39 H'FFF3A H'FFF3B H'FFF3E H'FFF3C H'FFF3D H'FFF3F Note: * Memory address register 0AR Memory address register 0AE Memory address register 0AH Memory address register 0AL I/O address register 0A Execute transfer count register 0AH ETCR0AH Execute transfer count register 0AL ETCR0AL Data transfer control register 0A Memory address register 0BR Memory address register 0BE Memory address register 0BH Memory address register 0BL I/O address register 0B DTCR0A MAR0BR MAR0BE MAR0BH MAR0BL IOAR0B Execute transfer count register 0BH ETCR0BH Execute transfer count register 0BL ETCR0BL Data transfer control register 0B Memory address register 1AR Memory address register 1AE Memory address register 1AH Memory address register 1AL I/O address register 1A DTCR0B MAR1AR MAR1AE MAR1AH MAR1AL IOAR1A Execute transfer count register 1AH ETCR1AH Execute transfer count register 1AL ETCR1AL Data transfer control register 1A Memory address register 1BR Memory address register 1BE Memory address register 1BH Memory address register 1BL I/O address register 1B DTCR1A MAR1BR MAR1BE MAR1BH MAR1BL IOAR1B Execute transfer count register 1BH ETCR1BH Execute transfer count register 1BL ETCR1BL Data transfer control register 1B DTCR1B The lower 20 bits of the address are indicated. Rev. 2.0, 06/04, page 201 of 980 7.2 Register Descriptions (1) (Short Address Mode) In short address mode, transfers can be carried out independently on channels A and B. Short address mode is selected by bits DTS2A and DTS1A in data transfer control register A (DTCRA) as indicated in table 7.4. Table 7.4 Selection of Short and Full Address Modes Bit 1 DTS1A 1 Description DMAC channel 0 operates as one channel in full address mode DMAC channels 0A and 0B operate as two independent channels in short address mode DMAC channel 1 operates as one channel in full address mode DMAC channels 1A and 1B operate as two independent channels in short address mode Bit 2 Channel DTS2A 0 1 Other than above 1 1 1 Other than above 7.2.1 Memory Address Registers (MAR) A memory address register (MAR) is a 32-bit readable/writable register that specifies a source or destination address. The transfer direction is determined automatically from the activation source. An MAR consists of four 8-bit registers designated MARR, MARE, MARH, and MARL. All bits of MARR are reserved; they cannot be modified and are always read as 1. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value Read/Write Undetermined -- -- -- -- -- -- -- -- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MARR MARE MARH MARL Source or destination address An MAR functions as a source or destination address register depending on how the DMAC is activated: as a destination address register if activation is by a receive-data-full interrupt from serial communication interface (SCI) channel 0 or by an A/D converter conversion-end interrupt, and as a source address register otherwise. The MAR value is incremented or decremented each time one byte or word is transferred, automatically updating the source or destination memory address. For details, see section 7.3.4, Data Transfer Control Registers (DTCR). The MARs are not initialized by a reset or in standby mode. Rev. 2.0, 06/04, page 202 of 980 7.2.2 I/O Address Registers (IOAR) An I/O address register (IOAR) is an 8-bit readable/writable register that specifies a source or destination address. The IOAR value is the lower 8 bits of the address. The upper 16 address bits are all 1 (H'FFFF). Bit Initial value Read/Write R/W R/W R/W 7 6 5 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W Source or destination address An IOAR functions as a source or destination address register depending on how the DMAC is activated: as a destination address register if activation is by a receive-data-full interrupt from serial communication interface (SCI) channel 0 or by an A/D converter conversion-end interrupt, and as a source address register otherwise. The IOAR value is held fixed. It is not incremented or decremented when a transfer is executed. The IOARs are not initialized by a reset or in standby mode. 7.2.3 Execute Transfer Count Registers (ETCR) An execute transfer count register (ETCR) is a 16-bit readable/writable register that specifies the number of transfers to be executed. These registers function in one way in I/O mode and idle mode, and another way in repeat mode. * I/O mode and idle mode Bit Initial value Read/Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Transfer counter In I/O mode and idle mode, ETCR functions as a 16-bit counter. The count is decremented by 1 each time one transfer is executed. The transfer ends when the count reaches H'0000. Rev. 2.0, 06/04, page 203 of 980 * Repeat mode Bit Initial value Read/Write R/W R/W R/W 7 6 5 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W ETCRH Transfer counter Bit Initial value Read/Write R/W R/W R/W 7 6 5 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W ETCRL Initial count In repeat mode, ETCRH functions as an 8-bit transfer counter and ETCRL holds the initial transfer count. ETCRH is decremented by 1 each time one transfer is executed. When ETCRH reaches H'00, the value in ETCRL is reloaded into ETCRH and the same operation is repeated. The ETCRs are not initialized by a reset or in standby mode. Rev. 2.0, 06/04, page 204 of 980 7.2.4 Data Transfer Control Registers (DTCR) A data transfer control register (DTCR) is an 8-bit readable/writable register that controls the operation of one DMAC channel. Bit Initial value Read/Write 7 DTE 0 R/W 6 DTSZ 0 R/W 5 DTID 0 R/W 4 RPE 0 R/W 3 DTIE 0 R/W 2 DTS2 0 R/W 1 DTS1 0 R/W 0 DTS0 0 R/W Data transfer enable Enables or disables data transfer Data transfer size Selects byte or word size Data transfer increment/decrement Selects whether to increment or decrement the memory address register Repeat enable Selects repeat mode Data transfer select These bits select the data transfer activation source Data transfer interrupt enable Enables or disables the CPU interrupt at the end of the transfer The DTCRs are initialized to H'00 by a reset and in standby mode. Bit 7--Data Transfer Enable (DTE): Enables or disables data transfer on a channel. When the DTE bit is set to 1, the channel waits for a transfer to be requested, and executes the transfer when activated as specified by bits DTS2 to DTS0. When DTE is 0, the channel is disabled and does not accept transfer requests. DTE is set to 1 by reading the register when DTE is 0, then writing 1. Bit 7 DTE 0 1 Description Data transfer is disabled. In I/O mode or idle mode, DTE is cleared to 0 when the specified number of transfers have been completed Data transfer is enabled (Initial value) If DTIE is set to 1, a CPU interrupt is requested when DTIE is cleared to 0. Rev. 2.0, 06/04, page 205 of 980 Bit 6--Data Transfer Size (DTSZ): Selects the data size of each transfer. Bit 6 DTSZ 0 1 Description Byte-size transfer Word-size transfer (Initial value) Bit 5--Data Transfer Increment/Decrement (DTID): Selects whether to increment or decrement the memory address register (MAR) after a data transfer in I/O mode or repeat mode. Bit 5 DTID 0 Description MAR is incremented after each data transfer * * 1 * * If DTSZ = 0, MAR is incremented by 1 after each transfer If DTSZ = 1, MAR is incremented by 2 after each transfer If DTSZ = 0, MAR is decremented by 1 after each transfer If DTSZ = 1, MAR is decremented by 2 after each transfer (Initial value) MAR is decremented after each data transfer MAR is not incremented or decremented in idle mode. Bit 4--Repeat Enable (RPE): Selects whether to transfer data in I/O mode, idle mode, or repeat mode. Bit 4 RPE 0 1 Bit 3 DTIE 0 1 0 1 Repeat mode Idle mode Description I/O mode (Initial value) Operations in these modes are described in sections 7.4.2, I/O Mode, 7.4.3, Idle Mode, and 7.4.4, Repeat Mode. Rev. 2.0, 06/04, page 206 of 980 Bit 3--Data Transfer Interrupt Enable (DTIE): Enables or disables the CPU interrupt (DEND) requested when the DTE bit is cleared to 0. Bit 3 DTIE 0 1 Description The DEND interrupt requested by DTE is disabled The DEND interrupt requested by DTE is enabled (Initial value) Bits 2 to 0--Data Transfer Select (DTS2, DTS1, DTS0): These bits select the data transfer activation source. Some of the selectable sources differ between channels A and B. Bit 2 DTS2 0 Bit 1 DTS1 0 Bit 0 DTS0 0 1 1 1 0 1 0 1 0 1 0 1 Description Compare match/input capture A interrupt from 16-bit timer channel 0 (Initial value) Compare match/input capture A interrupt from 16-bit timer channel 1 Compare match/input capture A interrupt from 16-bit timer channel 2 Conversion-end interrupt from A/D converter Transmit-data-empty interrupt from SCI channel 0 Receive-data-full interrupt from SCI channel 0 Falling edge of DREQ input (channel B) Transfer in full address mode (channel A) Low level of DREQ input (channel B) Transfer in full address mode (channel A) Note: See section 7.3.4, Data Transfer Control Registers (DTCR). The same internal interrupt can be selected as an activation source for two or more channels at once. In that case the channels are activated in a priority order, highest-priority channel first. For the priority order, see section 7.4.9, Multiple-Channel Operation. When a channel is enabled (DTE = 1), its selected DMAC activation source cannot generate a CPU interrupt. Rev. 2.0, 06/04, page 207 of 980 7.3 Register Descriptions (2) (Full Address Mode) In full address mode the A and B channels operate together. Full address mode is selected as indicated in table 7.4. 7.3.1 Memory Address Registers (MAR) A memory address register (MAR) is a 32-bit readable/writable register. MARA functions as the source address register of the transfer, and MARB as the destination address register. An MAR consists of four 8-bit registers designated MARR, MARE, MARH, and MARL. All bits of MARR are reserved; they cannot be modified and are always read as 1. (Write is invalid.) Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value Read/Write Undetermined -- -- -- -- -- -- -- -- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MARR MARE MARH MARL Source or destination address The MAR value is incremented or decremented each time one byte or word is transferred, automatically updating the source or destination memory address. For details, see section 7.3.4, Data Transfer Control Registers (DTCR). The MARs are not initialized by a reset or in standby mode. 7.3.2 I/O Address Registers (IOAR) The I/O address registers (IOARs) are not used in full address mode. Rev. 2.0, 06/04, page 208 of 980 7.3.3 Execute Transfer Count Registers (ETCR) An execute transfer count register (ETCR) is a 16-bit readable/writable register that specifies the number of transfers to be executed. The functions of these registers differ between normal mode and block transfer mode. * Normal mode ETCRA Bit Initial value Read/Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Transfer counter ETCRB: Is not used in normal mode. In normal mode ETCRA functions as a 16-bit transfer counter. The count is decremented by 1 each time one transfer is executed. The transfer ends when the count reaches H'0000. ETCRB is not used. Rev. 2.0, 06/04, page 209 of 980 * Block transfer mode ETCRA Bit Initial value Read/Write R/W R/W R/W 7 6 5 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W ETCRAH Block size counter Bit Initial value Read/Write R/W R/W R/W 7 6 5 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W ETCRAL Initial block size ETCRB Bit Initial value Read/Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Block transfer counter In block transfer mode, ETCRAH functions as an 8-bit block size counter. ETCRAL holds the initial block size. ETCRAH is decremented by 1 each time one byte or word is transferred. When the count reaches H'00, ETCRAH is reloaded from ETCRAL. Blocks consisting of an arbitrary number of bytes or words can be transferred repeatedly by setting the same initial block size value in ETCRAH and ETCRAL. In block transfer mode ETCRB functions as a 16-bit block transfer counter. ETCRB is decremented by 1 each time one block is transferred. The transfer ends when the count reaches H'0000. The ETCRs are not initialized by a reset or in standby mode. Rev. 2.0, 06/04, page 210 of 980 7.3.4 Data Transfer Control Registers (DTCR) The data transfer control registers (DTCRs) are 8-bit readable/writable registers that control the operation of the DMAC channels. A channel operates in full address mode when bits DTS2A and DTS1A are both set to 1 in DTCRA. DTCRA and DTCRB have different functions in full address mode. DTCRA Bit Initial value Read/Write 7 DTE 0 R/W 6 DTSZ 0 R/W 5 SAID 0 R/W 4 SAIDE 0 R/W 3 DTIE 0 R/W 2 DTS2A 0 R/W 1 DTS1A 0 R/W 0 DTS0A 0 R/W Data transfer enable Enables or disables data transfer Data transfer size Selects byte or word size Data transfer interrupt enable Enables or disables the CPU interrupt at the end of the transfer Data transfer select 0A Selects block transfer mode Source address increment/decrement Source address increment/ decrement enable These bits select whether the source address register (MARA) is incremented, decremented, or held fixed during the data transfer Data transfer select 2A and 1A These bits must both be set to 1 DTCRA is initialized to H'00 by a reset and in standby mode. Rev. 2.0, 06/04, page 211 of 980 Bit 7--Data Transfer Enable (DTE): Together with the DTME bit in DTCRB, this bit enables or disables data transfer on the channel. When the DTME and DTE bits are both set to 1, the channel is enabled. If auto-request is specified, data transfer begins immediately. Otherwise, the channel waits for transfers to be requested. When the specified number of transfers have been completed, the DTE bit is automatically cleared to 0. When DTE is 0, the channel is disabled and does not accept transfer requests. DTE is set to 1 by reading the register when DTE is 0, then writing 1. Bit 7 DTE 0 1 Description Data transfer is disabled (DTE is cleared to 0 when the specified number (Initial value) of transfers have been completed) Data transfer is enabled If DTIE is set to 1, a CPU interrupt is requested when DTE is cleared to 0. Bit 6--Data Transfer Size (DTSZ): Selects the data size of each transfer. Bit 6 DTSZ 0 1 Description Byte-size transfer Word-size transfer (Initial value) Bit 5--Source Address Increment/Decrement (SAID) and, Bit 4--Source Address Increment/Decrement Enable (SAIDE): These bits select whether the source address register (MARA) is incremented, decremented, or held fixed during the data transfer. Bit 5 SAID 0 Bit 4 SAIDE 0 1 Description MARA is held fixed MARA is incremented after each data transfer * * 1 0 1 If DTSZ = 0, MARA is incremented by 1 after each transfer If DTSZ = 1, MARA is incremented by 2 after each transfer (Initial value) MARA is held fixed MARA is decremented after each data transfer * * If DTSZ = 0, MARA is decremented by 1 after each transfer If DTSZ = 1, MARA is decremented by 2 after each transfer Rev. 2.0, 06/04, page 212 of 980 Bit 3--Data Transfer Interrupt Enable (DTIE): Enables or disables the CPU interrupt (DEND) requested when the DTE bit is cleared to 0. Bit 3 DTIE 0 1 Description The DEND interrupt requested by DTE is disabled The DEND interrupt requested by DTE is enabled (Initial value) Bits 2 and 1--Data Transfer Select 2A and 1A (DTS2A, DTS1A): A channel operates in full address mode when DTS2A and DTS1A are both set to 1. Bit 0--Data Transfer Select 0A (DTS0A): Selects normal mode or block transfer mode. Bit 0 DTS0A 0 1 Description Normal mode Block transfer mode (Initial value) Operations in these modes are described in sections 7.4.5, Normal Mode, and 7.4.6, Block Transfer Mode. Rev. 2.0, 06/04, page 213 of 980 DTCRB Bit Initial value Read/Write 7 DTME 0 R/W 6 -- 0 R/W 5 DAID 0 R/W 4 DAIDE 0 R/W 3 TMS 0 R/W 2 DTS2B 0 R/W 1 DTS1B 0 R/W 0 DTS0B 0 R/W Data transfer master enable Enables or disables data transfer, together with the DTE bit, and is cleared to 0 by an interrupt Reserved bit Transfer mode select Selects whether the block area is the source or destination in block transfer mode Data transfer select 2B to 0B These bits select the data transfer activation source Destination address increment/decrement Destination address increment/decrement enable These bits select whether the destination address register (MARB) is incremented, decremented, or held fixed during the data transfer DTCRB is initialized to H'00 by a reset and in standby mode. Bit 7--Data Transfer Master Enable (DTME): Together with the DTE bit in DTCRA, this bit enables or disables data transfer. When the DTME and DTE bits are both set to 1, the channel is enabled. When an NMI interrupt occurs DTME is cleared to 0, suspending the transfer so that the CPU can use the bus. The suspended transfer resumes when DTME is set to 1 again. For further information on operation in block transfer mode, see section 7.6.6, NMI Interrupts and Block Transfer Mode. DTME is set to 1 by reading the register while DTME = 0, then writing 1. Bit 7 DTME 0 1 Description Data transfer is disabled (DTME is cleared to 0 when an NMI interrupt occurs) Data transfer is enabled (Initial value) Rev. 2.0, 06/04, page 214 of 980 Bit 6--Reserved: Although reserved, this bit can be written and read. Bit 5--Destination Address Increment/Decrement (DAID) and, Bit 4--Destination Address Increment/Decrement Enable (DAIDE): These bits select whether the destination address register (MARB) is incremented, decremented, or held fixed during the data transfer. Bit 5 DAID 0 Bit 4 DAIDE 0 1 Description MARB is held fixed MARB is incremented after each data transfer * * 1 0 1 If DTSZ = 0, MARB is incremented by 1 after each data transfer If DTSZ = 1, MARB is incremented by 2 after each data transfer (Initial value) MARB is held fixed MARB is decremented after each data transfer * * If DTSZ = 0, MARB is decremented by 1 after each data transfer If DTSZ = 1, MARB is decremented by 2 after each data transfer Bit 3--Transfer Mode Select (TMS): Selects whether the source or destination is the block area in block transfer mode. Bit 3 TMS 0 1 Description Destination is the block area in block transfer mode Source is the block area in block transfer mode (Initial value) Rev. 2.0, 06/04, page 215 of 980 Bits 2 to 0--Data Transfer Select 2B to 0B (DTS2B, DTS1B, DTS0B): These bits select the data transfer activation source. The selectable activation sources differ between normal mode and block transfer mode. Normal mode Bit 2 DTS2B 0 Bit 1 DTS1B 0 1 1 0 1 Bit 0 DTS0B 0 1 0 1 0 1 0 1 Description Auto-request (burst mode) Cannot be used Auto-request (cycle-steal mode) Cannot be used Cannot be used Cannot be used Falling edge of DREQ Low level input at DREQ (Initial value) Block transfer mode Bit 2 Bit 1 Bit 0 DTS2B DTS1B DTS0B Description 0 0 0 1 1 1 0 1 0 1 0 1 0 1 Compare match/input capture A interrupt from 16-bit timer channel 0 (Initial value) Compare match/input capture A interrupt from 16-bit timer channel 1 Compare match/input capture A interrupt from 16-bit timer channel 2 Conversion-end interrupt from A/D converter Cannot be used Cannot be used Falling edge of DREQ Cannot be used The same internal interrupt can be selected to activate two or more channels. The channels are activated in a priority order, highest priority first. For the priority order, see section 7.4.9, Multiple-Channel Operation. Rev. 2.0, 06/04, page 216 of 980 7.4 7.4.1 Operation Overview Table 7.5 summarizes the DMAC modes. Table 7.5 DMAC Modes Activation I/O mode Idle mode Repeat mode Notes Up to four channels can operate independently Only the B channels support external requests Transfer Mode Short address mode Compare match/input * capture A interrupt from 16-bit timer channels 0 to 2 Transmit-data-empty and receive-data-full interrupts from SCI channel 0 Conversion-end interrupt from A/D converter External request * Full address mode Normal mode Auto-request * A and B channels are paired; up to two channels are available Burst mode transfer or cycle-steal mode transfer can be selected for autorequests External request Block transfer mode Compare match/input * capture A interrupt from 16-bit timer channels 0 to 2 Conversion-end interrupt from A/D converter External request A summary of operations in these modes follows. I/O Mode: One byte or word is transferred per request. A designated number of these transfers are executed. A CPU interrupt can be requested at completion of the designated number of transfers. One 24-bit address and one 8-bit address are specified. The transfer direction is determined automatically from the activation source. Idle Mode: One byte or word is transferred per request. A designated number of these transfers are executed. A CPU interrupt can be requested at completion of the designated number of transfers. One 24-bit address and one 8-bit address are specified. The addresses are held fixed. The transfer direction is determined automatically from the activation source. Rev. 2.0, 06/04, page 217 of 980 Repeat Mode: One byte or word is transferred per request. A designated number of these transfers are executed. When the designated number of transfers are completed, the initial address and counter value are restored and operation continues. No CPU interrupt is requested. One 24-bit address and one 8-bit address are specified. The transfer direction is determined automatically from the activation source. Normal Mode * Auto-request The DMAC is activated by register setup alone, and continues executing transfers until the designated number of transfers have been completed. A CPU interrupt can be requested at completion of the transfers. Both addresses are 24-bit addresses. Cycle-steal mode The bus is released to another bus master after each byte or word is transferred. Burst mode Unless requested by a higher-priority bus master, the bus is not released until the designated number of transfers have been completed. * External request One byte or word is transferred per request. A designated number of these transfers are executed. A CPU interrupt can be requested at completion of the designated number of transfers. Both addresses are 24-bit addresses. Block Transfer Mode: One block of a specified size is transferred per request. A designated number of block transfers are executed. At the end of each block transfer, one address is restored to its initial value. When the designated number of blocks have been transferred, a CPU interrupt can be requested. Both addresses are 24-bit addresses. Rev. 2.0, 06/04, page 218 of 980 7.4.2 I/O Mode I/O mode can be selected independently for each channel. One byte or word is transferred at each transfer request in I/O mode. A designated number of these transfers are executed. One address is specified in the memory address register (MAR), the other in the I/O address register (IOAR). The direction of transfer is determined automatically from the activation source. The transfer is from the address specified in IOAR to the address specified in MAR if activated by an SCI channel 0 receive-data-full interrupt, and from the address specified in MAR to the address specified in IOAR otherwise. Table 7.6 indicates the register functions in I/O mode. Table 7.6 Register Functions in I/O Mode Function Activated by SCI 0 ReceiveData-Full Other Interrupt Activation 0 MAR Register 23 Initial Setting Destination or source start address Source or destination address Number of transfers Operation Incremented or decremented once per transfer Held fixed Destination address register Source address register Transfer counter Source address register Destination address register 23 All 1s 7 IOAR 0 15 ETCR 0 Decremented once per transfer until H'0000 is reached and transfer ends Legend MAR: Memory address register IOAR: I/O address register ETCR: Execute transfer count register MAR and IOAR specify the source and destination addresses. MAR specifies a 24-bit source or destination address, which is incremented or decremented as each byte or word is transferred. IOAR specifies the lower 8 bits of a fixed address. The upper 16 bits are all 1s. IOAR is not incremented or decremented. Figure 7.2 illustrates how I/O mode operates. Rev. 2.0, 06/04, page 219 of 980 Address T Transfer IOAR 1 byte or word is transferred per request Address B Legend L = initial setting of MAR N = initial setting of ETCR Address T = L Address B = L + (-1) DTID * (2 DTSZ * N - 1) Figure 7.2 Operation in I/O Mode The transfer count is specified as a 16-bit value in ETCR. The ETCR value is decremented by 1 at each transfer. When the ETCR value reaches H'0000, the DTE bit is cleared and the transfer ends. If the DTIE bit is set to 1, a CPU interrupt is requested at this time. The maximum transfer count is 65,536, obtained by setting ETCR to H'0000. Transfers can be requested (activated) by compare match/input capture A interrupts from 16-bit timer channels 0 to 2, transmit-data-empty and receive-data-full interrupts from SCI channel 0, conversion-end interrupts from the A/D converter, and external request signals. For the detailed settings see section 7.2.4, Data Transfer Control Registers (DTCR). Rev. 2.0, 06/04, page 220 of 980 Figure 7.3 shows a sample setup procedure for I/O mode. I/O mode setup Set source and destination addresses 1 Set transfer count 2 Read DTCR 3 1. Set the source and destination addresses in MAR and IOAR. The transfer direction is determined automatically from the activation source. 2. Set the transfer count in ETCR. 3. Read DTCR while the DTE bit is cleared to 0. 4. Set the DTCR bits as follows. * Select the DMAC activation source with bits DTS2 to DTS0. * Set or clear the DTIE bit to enable or disable the CPU interrupt at the end of the transfer. * Clear the RPE bit to 0 to select I/O mode. * Select MAR increment or decrement with the DTID bit. * Select byte size or word size with the DTSZ bit. * Set the DTE bit to 1 to enable the transfer. Set DTCR 4 I/O mode Figure 7.3 I/O Mode Setup Procedure (Example) 7.4.3 Idle Mode Idle mode can be selected independently for each channel. One byte or word is transferred at each transfer request in idle mode. A designated number of these transfers are executed. One address is specified in the memory address register (MAR), the other in the I/O address register (IOAR). The direction of transfer is determined automatically from the activation source. The transfer is from the address specified in IOAR to the address specified in MAR if activated by an SCI channel 0 receive-data-full interrupt, and from the address specified in MAR to the address specified in IOAR otherwise. Table 7.7 indicates the register functions in idle mode. Rev. 2.0, 06/04, page 221 of 980 Table 7.7 Register Functions in Idle Mode Function Activated by SCI 0 ReceiveData-Full Other Interrupt Activation 0 MAR Register 23 Initial Setting Operation Destination address register Source address register Transfer counter Source address register Destination address register Destination or Held fixed source address Source or destination address Number of transfers Held fixed 23 All 1s 7 IOAR 0 15 ETCR 0 Decremented once per transfer until H'0000 is reached and transfer ends Legend MAR: Memory address register IOAR: I/O address register ETCR: Execute transfer count register MAR and IOAR specify the source and destination addresses. MAR specifies a 24-bit source or destination address. IOAR specifies the lower 8 bits of a fixed address. The upper 16 bits are all 1s. MAR and IOAR are not incremented or decremented. Figure 7.4 illustrates how idle mode operates. MAR Transfer IOAR 1 byte or word is transferred per request Figure 7.4 Operation in Idle Mode Rev. 2.0, 06/04, page 222 of 980 The transfer count is specified as a 16-bit value in ETCR. The ETCR value is decremented by 1 at each transfer. When the ETCR value reaches H'0000, the DTE bit is cleared, the transfer ends, and a CPU interrupt is requested. The maximum transfer count is 65,536, obtained by setting ETCR to H'0000. Transfers can be requested (activated) by compare match/input capture A interrupts from 16-bit timer channels 0 to 2, transmit-data-empty and receive-data-full interrupts from SCI channel 0, conversion-end interrupts from the A/D converter, and external request signals. For the detailed settings see section 7.3.4, Data Transfer Control Registers (DTCR). Figure 7.5 shows a sample setup procedure for idle mode. Idle mode setup Set source and destination addresses 1 Set transfer count 2 1. Set the source and destination addresses in MAR and IOAR. The transfer direction is determined automatically from the activation source. 2. Set the transfer count in ETCR. 3. Read DTCR while the DTE bit is cleared to 0. 4. Set the DTCR bits as follows. * Select the DMAC activation source with bits DTS2 to DTS0. * Set the DTIE and RPE bits to 1 to select idle mode. * Select byte size or word size with the DTSZ bit. * Set the DTE bit to 1 to enable the transfer. Read DTCR 3 Set DTCR 4 Idle mode Figure 7.5 Idle Mode Setup Procedure (Example) Rev. 2.0, 06/04, page 223 of 980 7.4.4 Repeat Mode Repeat mode is useful for cyclically transferring a bit pattern from a table to the programmable timing pattern controller (TPC) in synchronization, for example, with 16-bit timer compare match. Repeat mode can be selected for each channel independently. One byte or word is transferred per request in repeat mode, as in I/O mode. A designated number of these transfers are executed. One address is specified in the memory address register (MAR), the other in the I/O address register (IOAR). At the end of the designated number of transfers, MAR and ETCRH are restored to their original values and operation continues. The direction of transfer is determined automatically from the activation source. The transfer is from the address specified in IOAR to the address specified in MAR if activated by an SCI channel 0 receive-datafull interrupt, and from the address specified in MAR to the address specified in IOAR otherwise. Table 7.8 indicates the register functions in repeat mode. Table 7.8 Register Functions in Repeat Mode Function Activated by SCI 0 ReceiveData-Full Other Interrupt Activation Initial Setting Destination address register Source address register Destination or source start address Register Operation Incremented or decremented at each transfer until ETCRH reaches H'0000, then restored to initial value Held fixed 23 MAR 0 23 All 1s 7 IOAR 0 Source address register Transfer counter Destination Source or address destination register address Number of transfers 7 0 ETCRH Decremented once per transfer until H'0000 is reached, then reloaded from ETCRL Held fixed 7 0 Initial transfer count ETCRL Legend MAR: Memory address register IOAR: I/O address register ETCR: Execute transfer count register Number of transfers Rev. 2.0, 06/04, page 224 of 980 In repeat mode ETCRH is used as the transfer counter while ETCRL holds the initial transfer count. ETCRH is decremented by 1 at each transfer until it reaches H'00, then is reloaded from ETCRL. MAR is also restored to its initial value, which is calculated from the DTSZ and DTID bits in DTCR. Specifically, MAR is restored as follows: MAR MAR - (-1) DTID *2 DTSZ * ETCRL ETCRH and ETCRL should be initially set to the same value. In repeat mode transfers continue until the CPU clears the DTE bit to 0. After DTE is cleared to 0, if the CPU sets DTE to 1 again, transfers resume from the state at which DTE was cleared. No CPU interrupt is requested. As in I/O mode, MAR and IOAR specify the source and destination addresses. MAR specifies a 24-bit source or destination address. IOAR specifies the lower 8 bits of a fixed address. The upper 16 bits are all 1s. IOAR is not incremented or decremented. Figure 7.6 illustrates how repeat mode operates. Address T Transfer IOAR 1 byte or word is transferred per request Address B Legend L = initial setting of MAR N = initial setting of ETCRH and ETCRL Address T = L Address B = L + (-1) DTID * (2 DTSZ * N - 1) Figure 7.6 Operation in Repeat Mode Rev. 2.0, 06/04, page 225 of 980 The transfer count is specified as an 8-bit value in ETCRH and ETCRL. The maximum transfer count is 255, obtained by setting both ETCRH and ETCRL to H'FF. Transfers can be requested (activated) by compare match/input capture A interrupts from 16-bit timer channels 0 to 2, transmit-data-empty and receive-data-full interrupts from SCI channel 0, conversion-end interrupts from the A/D converter, and external request signals. For the detailed settings see section 7.2.4, Data Transfer Control Registers (DTCR). Figure 7.7 shows a sample setup procedure for repeat mode. Repeat mode Set source and destination addresses 1 Set transfer count 2 1. Set the source and destination addresses in MAR and IOAR. The transfer direction is determined automatically from the activation source. 2. Set the transfer count in both ETCRH and ETCRL. 3. Read DTCR while the DTE bit is cleared to 0. 4. Set the DTCR bits as follows. * Select the DMAC activation source with bits DTS2 to DTS0. * Clear the DTIE bit to 0 and set the RPE bit to 1 to select repeat mode. * Select MAR increment or decrement with the DTID bit. * Select byte size or word size with the DTSZ bit. * Set the DTE bit to 1 to enable the transfer. Read DTCR 3 Set DTCR 4 Repeat mode Figure 7.7 Repeat Mode Setup Procedure (Example) Rev. 2.0, 06/04, page 226 of 980 7.4.5 Normal Mode In normal mode the A and B channels are combined. One byte or word is transferred per request. A designated number of these transfers are executed. Addresses are specified in MARA and MARB. Table 7.9 indicates the register functions in I/O mode. Table 7.9 Register 23 MARA 23 MARB Register Functions in Normal Mode Function 0 Source address register 0 Destination address register Initial Setting Source start address Destination start address Number of transfers Operation Incremented or decremented once per transfer, or held fixed Incremented or decremented once per transfer, or held fixed Decremented once per transfer 15 ETCRA 0 Transfer counter Legend MARA: Memory address register A MARB: Memory address register B ETCRA: Execute transfer count register A The source and destination addresses are both 24-bit addresses. MARA specifies the source address. MARB specifies the destination address. MARA and MARB can be independently incremented, decremented, or held fixed as data is transferred. The transfer count is specified as a 16-bit value in ETCRA. The ETCRA value is decremented by 1 at each transfer. When the ETCRA value reaches H'0000, the DTE bit is cleared and the transfer ends. If the DTIE bit is set to 1, a CPU interrupt is requested at this time. The maximum transfer count is 65,536, obtained by setting ETCRA to H'0000. Rev. 2.0, 06/04, page 227 of 980 Figure 7.8 illustrates how normal mode operates. Address T A Transfer Address T B Address BA Address B B Legend L A = initial setting of MARA L B = initial setting of MARB N = initial setting of ETCRA TA = LA BA = L A + SAIDE * (-1) SAID * (2 DTSZ * N - 1) TB = LB BB = L B + DAIDE * (-1) DAID * (2 DTSZ * N - 1) Figure 7.8 Operation in Normal Mode Transfers can be requested (activated) by an external request or auto-request. An auto-requested transfer is activated by the register settings alone. The designated number of transfers are executed automatically. Either cycle-steal or burst mode can be selected. In cycle-steal mode the DMAC releases the bus temporarily after each transfer. In burst mode the DMAC keeps the bus until the transfers are completed, unless there is a bus request from a higher-priority bus master. For the detailed settings see section 7.3.4, Data Transfer Control Registers (DTCR). Rev. 2.0, 06/04, page 228 of 980 Figure 7.9 shows a sample setup procedure for normal mode. Normal mode Set initial source address 1 1. 2. 3. 4. Set initial destination address 2 5. Set transfer count 3 Set DTCRB (1) 4 Set DTCRA (1) 5 Read DTCRB 6 6. 7. 8. 9. Set the initial source address in MARA. Set the initial destination address in MARB. Set the transfer count in ETCRA. Set the DTCRB bits as follows. * Clear the DTME bit to 0. * Set the DAID and DAIDE bits to select whether MARB is incremented, decremented, or held fixed. * Select the DMAC activation source with bits DTS2B to DTS0B. Set the DTCRA bits as follows. * Clear the DTE bit to 0. * Select byte or word size with the DTSZ bit. * Set the SAID and SAIDE bits to select whether MARA is incremented, decremented, or held fixed. * Set or clear the DTIE bit to enable or disable the CPU interrupt at the end of the transfer. * Clear the DTS0A bit to 0 and set the DTS2A and DTS1A bits to 1 to select normal mode. Read DTCRB with DTME cleared to 0. Set the DTME bit to 1 in DTCRB. Read DTCRA with DTE cleared to 0. Set the DTE bit to 1 in DTCRA to enable the transfer. Set DTCRB (2) 7 Read DTCRA 8 Set DTCRA (2) 9 Normal mode Note: Carry out settings 1 to 9 with the DEND interrupt masked in the CPU. If an NMI interrupt occurs during the setup procedure, it may clear the DTME bit to 0, in which case the transfer will not start. Figure 7.9 Normal Mode Setup Procedure (Example) Rev. 2.0, 06/04, page 229 of 980 7.4.6 Block Transfer Mode In block transfer mode the A and B channels are combined. One block of a specified size is transferred per request. A designated number of block transfers are executed. Addresses are specified in MARA and MARB. The block area address can be either held fixed or cycled. Table 7.10 indicates the register functions in block transfer mode. Table 7.10 Register Functions in Block Transfer Mode Register 23 MARA 23 MARB 7 0 0 0 Function Source address register Destination address register Block size counter Initial Setting Source start address Destination start address Block size Operation Incremented or decremented once per transfer, or held fixed Incremented or decremented once per transfer, or held fixed Decremented once per transfer until H'00 is reached, then reloaded from ETCRL Held fixed ETCRAH 7 0 Initial block size Block size ETCRAL 15 ETCRB 0 Block transfer counter Number of block transfers Decremented once per block transfer until H'0000 is reached and the transfer ends Legend MARA: Memory address register A MARB: Memory address register B ETCRA: Execute transfer count register A ETCRB: Execute transfer count register B The source and destination addresses are both 24-bit addresses. MARA specifies the source address. MARB specifies the destination address. MARA and MARB can be independently incremented, decremented, or held fixed as data is transferred. One of these registers operates as a block area register: even if it is incremented or decremented, it is restored to its initial value at the end of each block transfer. The TMS bit in DTCRB selects whether the block area is the source or destination. Rev. 2.0, 06/04, page 230 of 980 If M (1 to 255) is the size of the block transferred at each request and N (1 to 65,536) is the number of blocks to be transferred, then ETCRAH and ETCRAL should initially be set to M and ETCRB should initially be set to N. Figure 7.10 illustrates how block transfer mode operates. In this figure, bit TMS is cleared to 0, meaning the block area is the destination. TA Transfer Block 1 Block area BA Address T B Address B B Block 2 M bytes or words are transferred per request Block N Legend L A = initial setting of MARA L B = initial setting of MARB M = initial setting of ETCRAH and ETCRAL N = initial setting of ETCRB T A = LA B A = L A + SAIDE * (-1) SAID * (2 DTSZ * M - 1) T B = LB B B = L B + DAIDE * (-1) DAID * (2 DTSZ * M - 1) Figure 7.10 Operation in Block Transfer Mode Rev. 2.0, 06/04, page 231 of 980 When activated by a transfer request, the DMAC executes a burst transfer. During the transfer MARA and MARB are updated according to the DTCR settings, and ETCRAH is decremented. When ETCRAH reaches H'00, it is reloaded from ETCRAL to restore the initial value. The memory address register of the block area is also restored to its initial value, and ETCRB is decremented. If ETCRB is not H'0000, the DMAC then waits for the next transfer request. ETCRAH and ETCRAL should be initially set to the same value. The above operation is repeated until ETCRB reaches H'0000, at which point the DTE bit is cleared to 0 and the transfer ends. If the DTIE bit is set to 1, a CPU interrupt is requested at this time. Figure 7.11 shows examples of a block transfer with byte data size when the block area is the destination. In (a) the block area address is cycled. In (b) the block area address is held fixed. Transfers can be requested (activated) by compare match/input capture A interrupts from ITU channels 0 to 2, by an A/D converter conversion-end interrupt, and by external request signals. For the detailed settings see section 7.3.4, Data Transfer Control Registers (DTCR). Rev. 2.0, 06/04, page 232 of 980 Start (DTE = DTME = 1) Start (DTE = DTME = 1) Transfer requested? Yes Get bus No Transfer requested? Yes Get bus No Read from MARA address MARA = MARA + 1 Write to MARB address MARB = MARB + 1 ETCRAH = ETCRAH -1 No ETCRAH = H'00 Yes Release bus ETCRAH = ETCRAL MARB = MARB - ETCRAL ETCRB = ETCRB -1 No Read from MARA address MARA = MARA + 1 Write to MARB address ETCRAH = ETCRAH -1 No ETCRAH = H'00 Yes Release bus ETCRAH = ETCRAL ETCRB = ETCRB -1 No ETCRB = H'0000 Yes Clear DTE to 0 and end transfer ETCRB = H'0000 Yes Clear DTE to 0 and end transfer a. DTSZ = TMS = 0 SAID = DAID = 0 SAIDE = DAIDE = 1 b. DTSZ = TMS = 0 SAID = 0 SAIDE = 1 DAIDE = 0 Figure 7.11 Block Transfer Mode Flowcharts (Examples) Rev. 2.0, 06/04, page 233 of 980 Figure 7.12 shows a sample setup procedure for block transfer mode. Block transfer mode Set source address 1 Set destination address 2 Set block transfer count 3 Set block size 4 Set DTCRB (1) 5 Set DTCRA (1) 6 Read DTCRB 7 Set the source address in MARA. Set the destination address in MARB. Set the block transfer count in ETCRB. Set the block size (number of bytes or words) in both ETCRAH and ETCRAL. 5. Set the DTCRB bits as follows. * Clear the DTME bit to 0. * Set the DAID and DAIDE bits to select whether MARB is incremented, decremented, or held fixed. * Set or clear the TMS bit to make the block area the source or destination. * Select the DMAC activation source with bits DTS2B to DTS0B. 6. Set the DTCRA bits as follows. * Clear the DTE to 0. * Select byte size or word size with the DTSZ bit. * Set the SAID and SAIDE bits to select whether MARA is incremented, decremented, or held fixed. * Set or clear the DTIE bit to enable or disable the CPU interrupt at the end of the transfer. * Set bits DTS2A to DTS0A all to 1 to select block transfer mode. 7. Read DTCRB with DTME cleared to 0. 8. Set the DTME bit to 1 in DTCRB. 9. Read DTCRA with DTE cleared to 0. 10. Set the DTE bit to 1 in DTCRA to enable the transfer. 1. 2. 3. 4. Set DTCRB (2) 8 Read DTCRA 9 Set DTCRA (2) 10 Block transfer mode Note: Carry out settings 1 to 10 with the DEND interrupt masked in the CPU. If an NMI interrupt occurs during the setup procedure, it may clear the DTME bit to 0, in which case the transfer will not start. Figure 7.12 Block Transfer Mode Setup Procedure (Example) Rev. 2.0, 06/04, page 234 of 980 7.4.7 DMAC Activation The DMAC can be activated by an internal interrupt, external request, or auto-request. The available activation sources differ depending on the transfer mode and channel as indicated in table 7.11. Table 7.11 DMAC Activation Sources Short Address Mode Channels Activation Source Internal interrupts IMIA0 IMIA1 IMIA2 ADI TXI0 RXI0 External requests Falling edge of DREQ Low input at DREQ Auto-request x x x x x x 0A and 1A Channels 0B and 1B x x x x x x x x Full Address Mode Normal Block Activation by Internal Interrupts: When an interrupt request is selected as a DMAC activation source and the DTE bit is set to 1, that interrupt request is not sent to the CPU. It is not possible for an interrupt request to activate the DMAC and simultaneously generate a CPU interrupt. When the DMAC is activated by an interrupt request, the interrupt request flag is cleared automatically. If the same interrupt is selected to activate two or more channels, the interrupt request flag is cleared when the highest-priority channel is activated, but the transfer request is held pending on the other channels in the DMAC, which are activated in their priority order. Rev. 2.0, 06/04, page 235 of 980 Activation by External Request: If an external request (DREQ pin) is selected as an activation source, the DREQ pin becomes an input pin and the corresponding TEND pin becomes an output pin, regardless of the port data direction register (DDR) settings. The DREQ input can be levelsensitive or edge-sensitive. In short address mode and normal mode, an external request operates as follows. If edge sensing is selected, one byte or word is transferred each time a high-to-low transition of the DREQ input is detected. If the next edge is input before the transfer is completed, the next transfer may not be executed. If level sensing is selected, the transfer continues while DREQ is low, until the transfer is completed. The bus is released temporarily after each byte or word has been transferred, however. If the DREQ input goes high during a transfer, the transfer is suspended after the current byte or word has been transferred. When DREQ goes low, the request is held internally until one byte or word has been transferred. The TEND signal goes low during the last write cycle. In block transfer mode, an external request operates as follows. Only edge-sensitive transfer requests are possible in block transfer mode. Each time a high-to-low transition of the DREQ input is detected, a block of the specified size is transferred. The TEND signal goes low during the last write cycle in each block. Activation by Auto-Request: The transfer starts as soon as enabled by register setup, and continues until completed. Cycle-steal mode or burst mode can be selected. In cycle-steal mode the DMAC releases the bus temporarily after transferring each byte or word. Normally, DMAC cycles alternate with CPU cycles. In burst mode the DMAC keeps the bus until the transfer is completed, unless there is a higherpriority bus request. If there is a higher-priority bus request, the bus is released after the current byte or word has been transferred. Rev. 2.0, 06/04, page 236 of 980 7.4.8 DMAC Bus Cycle Figure 7.13 shows an example of the timing of the basic DMAC bus cycle. This example shows a word-size transfer from a 16-bit two-state access area to an 8-bit three-state access area. When the DMAC gets the bus from the CPU, after one dead cycle (Td), it reads from the source address and writes to the destination address. During these read and write operations the bus is not released even if there is another bus request. DMAC cycles comply with bus controller settings in the same way as CPU cycles. CPU cycle T1 Source address Address bus Destination address T2 T1 T2 Td T1 DMAC cycle (1 word transfer) T2 T1 T2 T3 T1 T2 T3 T1 CPU cycle T2 T1 T2 RD HWR LWR Figure 7.13 DMA Transfer Bus Timing (Example) Rev. 2.0, 06/04, page 237 of 980 Figure 7.14 shows the timing when the DMAC is activated by low input at a DREQ pin. This example shows a word-size transfer from a 16-bit two-state access area to another 16-bit two-state access area. The DMAC continues the transfer while the DREQ pin is held low. DMAC cycle (last transfer cycle) Td T1 T2 T1 T2 CPU cycle T1 T2 T3 Td DMAC cycle T1 T2 T1 T2 CPU cycle T1 T2 CPU cycle T1 T2 DREQ Address bus Source Destination address address Source Destination address address RD HWR , LWR TEND Figure 7.14 Bus Timing of DMA Transfer Requested by Low DREQ Input Rev. 2.0, 06/04, page 238 of 980 Figure 7.15 shows an auto-requested burst-mode transfer. This example shows a transfer of three words from a 16-bit two-state access area to another 16-bit two-state access area. CPU cycle T1 Source address Address bus Destination address T2 Td T1 T2 T1 T2 DMAC cycle T1 T2 T1 T2 T1 T2 T1 T2 CPU cycle T1 T2 RD HWR , LWR Figure 7.15 Burst DMA Bus Timing When the DMAC is activated from a DREQ pin there is a minimum interval of four states from when the transfer is requested until the DMAC starts operating. The DREQ pin is not sampled during the time between the transfer request and the start of the transfer. In short address mode and normal mode, the pin is next sampled at the end of the read cycle. In block transfer mode, the pin is next sampled at the end of one block transfer. Rev. 2.0, 06/04, page 239 of 980 Figure 7.16 shows the timing when the DMAC is activated by the falling edge of DREQ in normal mode. CPU cycle T2 T1 T2 CPU cycle T2 T1 T2 T1 T2 Td DMAC cycle T1 T2 T1 DMAC cycle Td T1 T2 DREQ Address bus RD HWR , LWR Minimum 4 states Next sampling point Figure 7.16 Timing of DMAC Activation by Falling Edge of DREQ in Normal Mode Rev. 2.0, 06/04, page 240 of 980 Figure 7.17 shows the timing when the DMAC is activated by level-sensitive low DREQ input in normal mode. CPU cycle T2 T1 T2 T1 T2 Td DMAC cycle T1 T2 T1 T2 T1 CPU cycle T2 T1 T2 T1 DREQ Address bus RD HWR , LWR Minimum 4 states Next sampling point Figure 7.17 Timing of DMAC Activation by Low DREQ Level in Normal Mode Rev. 2.0, 06/04, page 241 of 980 Figure 7.18 shows the timing when the DMAC is activated by the falling edge of DREQ in block transfer mode. End of 1 block transfer DMAC cycle T1 T2 T1 T2 T1 T2 T1 T2 T1 CPU cycle T2 T1 T2 DMAC cycle Td T1 T2 DREQ Address bus RD HWR , LWR TEND Next sampling Minimum 4 states Figure 7.18 Timing of DMAC Activation by Falling Edge of DREQ in Block Transfer Mode Rev. 2.0, 06/04, page 242 of 980 7.4.9 Multiple-Channel Operation The DMAC channel priority order is: channel 0 > channel 1 and channel A > channel B. Table 7.12 shows the complete priority order. Table 7.12 Channel Priority Order Short Address Mode Channel 0A Channel 0B Channel 1A Channel 1B Channel 1 Low Full Address Mode Channel 0 Priority High If transfers are requested on two or more channels simultaneously, or if a transfer on one channel is requested during a transfer on another channel, the DMAC operates as follows. * When a transfer is requested, the DMAC requests the bus right. When it gets the bus right, it starts a transfer on the highest-priority channel at that time. * Once a transfer starts on one channel, requests to other channels are held pending until that channel releases the bus. * After each transfer in short address mode, and each externally-requested or cycle-steal transfer in normal mode, the DMAC releases the bus and returns to step 1. After releasing the bus, if there is a transfer request for another channel, the DMAC requests the bus again. * After completion of a burst-mode transfer, or after transfer of one block in block transfer mode, the DMAC releases the bus and returns to step 1. If there is a transfer request for a higher-priority channel or a bus request from a higher-priority bus master, however, the DMAC releases the bus after completing the transfer of the current byte or word. After releasing the bus, if there is a transfer request for another channel, the DMAC requests the bus again. Figure 7.19 shows the timing when channel 0A is set up for I/O mode and channel 1 for burst mode, and a transfer request for channel 0A is received while channel 1 is active. Rev. 2.0, 06/04, page 243 of 980 DMAC cycle (channel 1) T1 Address bus T2 T1 CPU cycle T2 Td DMAC cycle (channel 0A) T1 T2 T1 T2 T1 CPU cycle T2 Td DMAC cycle (channel 1) T1 T2 T1 T2 RD HWR , LWR Figure 7.19 Timing of Multiple-Channel Operations 7.4.10 External Bus Requests, DRAM Interface, and DMAC During a DMAC transfer, if the bus right is requested by an external bus request signal (BREQ) or by the DRAM interface (refresh cycle), the DMAC releases the bus after completing the transfer of the current byte or word. If there is a transfer request at this point, the DMAC requests the bus right again. Figure 7.20 shows an example of the timing of insertion of a refresh cycle during a burst transfer on channel 0. Refresh cycle T2 T1 T2 Td DMAC cycle (channel 0) T1 Address bus T2 T1 T2 T1 T2 T1 DMAC cycle (channel 0) T1 T2 T1 T2 T1 T2 RD HWR , LWR Figure 7.20 Bus Timing of DRAM Interface, and DMAC Rev. 2.0, 06/04, page 244 of 980 7.4.11 NMI Interrupts and DMAC NMI interrupts do not affect DMAC operations in short address mode. If an NMI interrupt occurs during a transfer in full address mode, the DMAC suspends operations. In full address mode, a channel is enabled when its DTE and DTME bits are both set to 1. NMI input clears the DTME bit to 0. After transferring the current byte or word, the DMAC releases the bus to the CPU. In normal mode, the suspended transfer resumes when the CPU sets the DTME bit to 1 again. Check that the DTE bit is set to 1 and the DTME bit is cleared to 0 before setting the DTME bit to 1. Figure 7.21 shows the procedure for resuming a DMAC transfer in normal mode on channel 0 after the transfer was halted by NMI input. Resuming DMAC transfer in normal mode 1. Check that DTE = 1 and DTME = 0. 2. Read DTCRB while DTME = 0, then write 1 in the DTME bit. 1 DTE = 1 DTME = 0 Yes Set DTME to 1 No 2 DMA transfer continues End Figure 7.21 Procedure for Resuming a DMAC Transfer Halted by NMI (Example) For information about NMI interrupts in block transfer mode, see section 7.6.6, NMI Interrupts and Block Transfer Mode. Rev. 2.0, 06/04, page 245 of 980 7.4.12 Aborting a DMAC Transfer When the DTE bit in an active channel is cleared to 0, the DMAC halts after transferring the current byte or word. The DMAC starts again when the DTE bit is set to 1. In full address mode, the DTME bit can be used for the same purpose. Figure 7.22 shows the procedure for aborting a DMAC transfer by software. DMAC transfer abort 1. Clear the DTE bit to 0 in DTCR. To avoid generating an interrupt when aborting a DMAC transfer, clear the DTIE bit to 0 simultaneously. 1 Set DTCR DMAC transfer aborted Figure 7.22 Procedure for Aborting a DMAC Transfer Rev. 2.0, 06/04, page 246 of 980 7.4.13 Exiting Full Address Mode Figure 7.23 shows the procedure for exiting full address mode and initializing the pair of channels. To set the channels up in another mode after exiting full address mode, follow the setup procedure for the relevant mode. Exiting full address mode Halt the channel 1 1. Clear the DTE bit to 0 in DTCRA, or wait for the transfer to end and the DTE bit to be cleared to 0. 2. Clear all DTCRB bits to 0. 3. Clear all DTCRA bits to 0. Initialize DTCRB 2 Initialize DTCRA 3 Initialized and halted Figure 7.23 Procedure for Exiting Full Address Mode (Example) Rev. 2.0, 06/04, page 247 of 980 7.4.14 DMAC States in Reset State, Standby Modes, and Sleep Mode When the chip is reset or enters software standby mode, the DMAC is initialized and halts. DMAC operations continue in sleep mode. Figure 7.24 shows the timing of a cycle-steal transfer in sleep mode. Sleep mode CPU cycle T2 Td DMAC cycle T1 T2 T1 T2 Td DMAC cycle T1 T2 T1 T2 Td Address bus RD HWR , LWR Figure 7.24 Timing of Cycle-Steal Transfer in Sleep Mode Rev. 2.0, 06/04, page 248 of 980 7.5 Interrupts The DMAC generates only DMA-end interrupts. Table 7.13 lists the interrupts and their priority. Table 7.13 DMAC Interrupts Description Interrupt DEND0A DEND0B DEND1A DEND1B Short Address Mode End of transfer on channel 0A End of transfer on channel 0B End of transfer on channel 1A End of transfer on channel 1B Full Address Mode End of transfer on channel 0 -- End of transfer on channel 1 -- Low Interrupt Priority High Each interrupt is enabled or disabled by the DTIE bit in the corresponding data transfer control register (DTCR). Separate interrupt signals are sent to the interrupt controller. The interrupt priority order among channels is channel 0 > channel 1 and channel A > channel B. Figure 7.25 shows the DMA-end interrupt logic. An interrupt is requested whenever DTE = 0 and DTIE = 1. DTE DMA-end interrupt DTIE Figure 7.25 DMA-End Interrupt Logic The DMA-end interrupt for the B channels (DENDB) is unavailable in full address mode. The DTME bit does not affect interrupt operations. Rev. 2.0, 06/04, page 249 of 980 7.6 7.6.1 Usage Notes Note on Word Data Transfer Word data cannot be accessed starting at an odd address. When word-size transfer is selected, set even values in the memory and I/O address registers (MAR and IOAR). 7.6.2 DMAC Self-Access The DMAC itself cannot be accessed during a DMAC cycle. DMAC registers cannot be specified as source or destination addresses. 7.6.3 Longword Access to Memory Address Registers A memory address register can be accessed as longword data at the MARR address. Example MOV.L #LBL, ER0 MOV.L ER0, @MARR Four byte accesses are performed. Note that the CPU may release the bus between the second byte (MARE) and third byte (MARH). Memory address registers should be written and read only when the DMAC is halted. 7.6.4 Note on Full Address Mode Setup Full address mode is controlled by two registers: DTCRA and DTCRB. Care must be taken to prevent the B channel from operating in short address mode during the register setup. The enable bits (DTE and DTME) should not be set to 1 until the end of the setup procedure. Rev. 2.0, 06/04, page 250 of 980 7.6.5 Note on Activating DMAC by Internal Interrupts When using an internal interrupt to activate the DMAC, make sure that the interrupt selected as the activating source does not occur during the interval after it has been selected but before the DMAC has been enabled. The on-chip supporting module that will generate the interrupt should not be activated until the DMAC has been enabled. If the DMAC must be enabled while the onchip supporting module is active, follow the procedure in figure 7.26. Enabling of DMAC Yes Interrupt handling by CPU Selected interrupt requested? No 1 1. While the DTE bit is cleared to 0, interrupt requests are sent to the CPU. 2. Clear the interrupt enable bit to 0 in the interrupt-generating on-chip supporting module. 3. Enable the DMAC. 4. Enable the DMAC-activating interrupt. Clear selected interrupt's enable bit to 0 2 Enable DMAC 3 Set selected interrupt's enable bit to 1 4 DMAC operates Figure 7.26 Procedure for Enabling DMAC while On-Chip Supporting Module is Operating (Example) If the DTE bit is set to 1 but the DTME bit is cleared to 0, the DMAC is halted and the selected activating source cannot generate a CPU interrupt. If the DMAC is halted by an NMI interrupt, for example, the selected activating source cannot generate CPU interrupts. To terminate DMAC operations in this state, clear the DTE bit to 0 to allow CPU interrupts to be requested. To continue DMAC operations, carry out steps 2 and 4 in figure 7.26 before and after setting the DTME bit to 1. Rev. 2.0, 06/04, page 251 of 980 When 16-bit timer interrupt activates the DMAC, make sure the next interrupt does not occur before the DMA transfer ends. If one 16-bit timer interrupt activates two or more channels, make sure the next interrupt does not occur before the DMA transfers end on all the activated channels. If the next interrupt occurs before a transfer ends, the channel or channels for which that interrupt was selected may fail to accept further activation requests. 7.6.6 NMI Interrupts and Block Transfer Mode If an NMI interrupt occurs in block transfer mode, the DMAC operates as follows. * When the NMI interrupt occurs, the DMAC finishes transferring the current byte or word, then clears the DTME bit to 0 and halts. The halt may occur in the middle of a block. It is possible to find whether a transfer was halted in the middle of a block by checking the block size counter. If the block size counter does not have its initial value, the transfer was halted in the middle of a block. * If the transfer is halted in the middle of a block, the activating interrupt flag is cleared to 0. The activation request is not held pending. * While the DTE bit is set to 1 and the DTME bit is cleared to 0, the DMAC is halted and does not accept activating interrupt requests. If an activating interrupt occurs in this state, the DMAC does not operate and does not hold the transfer request pending internally. Neither is a CPU interrupt requested. For this reason, before setting the DTME bit to 1, first clear the enable bit of the activating interrupt to 0. Then, after setting the DTME bit to 1, set the interrupt enable bit to 1 again. See section 7.6.5, Note on Activating DMAC by Internal Interrupts. * When the DTME bit is set to 1, the DMAC waits for the next transfer request. If it was halted in the middle of a block transfer, the rest of the block is transferred when the next transfer request occurs. Otherwise, the next block is transferred when the next transfer request occurs. 7.6.7 Memory and I/O Address Register Values Table 7.14 indicates the address ranges that can be specified in the memory and I/O address registers (MAR and IOAR). Rev. 2.0, 06/04, page 252 of 980 Table 7.14 Address Ranges Specifiable in MAR and IOAR 1-Mbyte Mode MAR IOAR H'00000 to H'FFFFF (0 to 1048575) H'FFF00 to H'FFFFF (1048320 to 1048575) 16-Mbyte Mode H'000000 to H'FFFFFF (0 to 16777215) H'FFFF00 to H'FFFFFF (16776960 to 16777215) MAR bits 23 to 20 are ignored in 1-Mbyte mode. 7.6.8 Bus Cycle when Transfer is Aborted When a transfer is aborted by clearing the DTE bit or suspended by an NMI that clears the DTME bit, if this halts a channel for which the DMAC has a transfer request pending internally, a dead cycle may occur. This dead cycle does not update the halted channel's address register or counter value. Figure 7.27 shows an example in which an auto-requested transfer in cycle-steal mode on channel 0 is aborted by clearing the DTE bit in channel 0. DMAC cycle Td Td CPU cycle T1 T2 Td DMAC cycle T1 T2 T1 T2 T1 CPU cycle T2 T3 CPU cycle T1 T2 Address bus RD HWR, LWR DTE bit is cleared Figure 7.27 Bus Timing at Abort of DMA Transfer in Cycle-Steal Mode 7.6.9 Transfer Requests by A/D Converter When the A/D converter is set to scan mode and conversion is performed on more than one channel, the A/D converter generates a transfer request when all conversions are completed. The converted data is stored in the appropriate ADDR registers. Block transfer mode and full address mode should therefore be used to transfer all the conversion results at one time. Rev. 2.0, 06/04, page 253 of 980 Rev. 2.0, 06/04, page 254 of 980 Section 8 I/O Ports 8.1 Overview This LSI has ten input/output ports (ports 1 to 6, 8, 9, A, and B) and one input port (port 7). Table 8.1 summarizes the port functions. The pins in each port are multiplexed as shown in table 8.1. Each port has a data direction register (DDR) for selecting input or output, and a data register (DR) for storing output data. In addition to these registers, ports 2, 4, and 5 have an input pull-up control register (PCR) for switching input pull-up transistors on and off. Ports 1 to 6 and port 8 can drive one TTL load and a 90-pF capacitive load. Ports 9, A, and B can drive one TTL load and a 30-pF capacitive load. Ports 1 to 6 and 8 to B can drive a darlington pair. Ports 1, 2, and 5 can drive LEDs (with 10-mA current sink). Pins P82 to P80, PA7 to PA0 have Schmitt-trigger input circuits. For block diagrams of the ports see appendix C, I/O Port Block Diagrams. Rev. 2.0, 06/04, page 255 of 980 Table 8.1 Port Description Port Functions Expanded Modes Pins P17 to P10/ A7 to A0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Address output (A7 to A0) and generic input DDR = 0: generic input DDR = 1: address output Address output (A15 to A8) and generic input DDR = 0: generic input DDR = 1: address output Single-Chip Modes Mode 7 Generic input/output Port 1 * 8-bit I/O port Can drive LEDs Address output pins (A7 to A0) Port 2 * 8-bit I/O port Built-in input pull-up transistors Can drive LEDs Port 3 * 8-bit I/O port P27 to P20/ A15 to A8 Address output pins (A15 to A8) Generic input/output P37 to P30/ D15 to D8 Data input/output (D15 to D8) Generic input/output Port 4 * 8-bit I/O port P47 to P40/ * Built-in input pull- D7 to D0 up transistors P53 to P50/ * Built-in input pull- A19 to A16 up transistors * Can drive LEDs Data input/output (D7 to D0) and 8-bit generic input/output 8-bit bus mode: generic input/output 16-bit bus mode: data input/output Address output (A19 to A16) Generic input/output Port 5 * 4-bit I/O port Generic input/output Address output (A19 to A16) and 4-bit generic input DDR = 0: generic input DDR = 1: address output Port 6 * 7-bit I/O port and P67/ 1-bit input port P66/LWR P65/HWR P64/RD P63/AS P62/BACK P61/BREQ P60/WAIT Port 7 * 8-bit input port P77/AN7/DA1 P76/AN6/DA0 P75 to P70/ AN5 to AN0 Port 8 * 5-bit I/O port * P82 to P80 have Schmitt inputs P84/CS0 Clock output () and generic input Bus control signal output (LWR, HWR, RD, AS) Generic input/output Bus control signal input/output (BACK, BREQ, WAIT) and 3-bit generic input/output Analog input (AN7, AN6) to A/D converter, analog output (DA1, DA0) from D/A converter, and generic input Analog input (AN5 to AN0) to A/D converter, and generic input DDR = 0: generic input DDR = 1 (reset value): CS0 output DDR = 0 (reset value): generic input DDR = 1: CS0 output Generic input/output P83/IRQ3/ CS1/ADTRG IRQ3 input, CS1 output, external trigger input (ADTRG) to A/D converter, and generic input DDR = 0 (after reset): generic input DDR = 1: CS1 output IRQ3 input, external trigger input (ADTRG) to A/D converter, and generic input/output IRQ2 and IRQ1 input and generic input/output P82/IRQ2/CS2 IRQ2 and IRQ1 input, CS2 and CS3 output, and generic input* P81/IRQ1/CS3 DDR = 0 (reset value): generic input DDR = 1: CS2 and CS3 output P80/IRQ0 /RFSH IRQ0 input, RFSH output, and generic input/output IRQ0 input and generic input/output Note: * P81 can be used as an output port by making a setting in DRCRA. Rev. 2.0, 06/04, page 256 of 980 Expanded Modes Port Description Pins P95/IRQ5 /SCK1 P94/IRQ4 /SCK0 P93/RxD1 P92/RxD0 P91/TxD1 P90/TxD0 PA7/TP7/ TIOCB2/A20 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Single-Chip Modes Mode 7 Port 9 * 6-bit I/O port Input and output (SCK1, SCK0, RxD1, RxD0, TxD1, TxD0) for serial communication interfaces 1 and 0 (SCI1/0), IRQ5 and IRQ4 input, and 6-bit generic input/output Port A * 8-bit I/O port * Schmitt inputs Output (TP7) from programmable timing pattern controller (TPC), input or output (TIOCB2) for 16-bit timer and generic input/output Address output (A20) Address output (A20), TPC output (TP7), input or output (TIOCB2) for 16-bit timer, and generic input/output TPC output (TP7), 16-bit timer input or output (TIOCB2), and generic input/output PA6/TP6/ TIOCA2/A21 PA5/TP5/ TIOCB1/A22 PA4/TP4/ TIOCA1/A23 PA3/TP3/ TIOCB0/ TCLKD PA2/TP2/ TIOCA0/ TCLKC PA1/TP1/ TCLKB /TEND1 PA0/TP0/ TCLKA /TEND0 Port B * 8-bit I/O port PB7/TP15/ RXD2 PB6/TP14/ TXD2 PB5/TP13/ SCK2/LCAS PB4/TP12/ UCAS PB3/TP11/ TMIO3/ DREQ1/CS4 PB2/TP10/ TMO2/CS5 PB1/TP9/ TMIO1/ DREQ0/CS6 PB0/TP8/ TMO0/CS7 TPC output (TP6 to TP4), TPC output (TP6 to TP4),16-bit timer input and 16-bit timer input and output (TIOCA2, TIOCB1, TIOCA1), address output (TIOCA2, TIOCB1, output (A23 to A21), and generic input/output TIOCA1) , and generic input/output TPC output (TP6 to TP4), 16-bit timer input and output (TIOCA2, TIOCB1, TIOCA1) and generic input/output TPC output (TP3 to TP0), 16-bit timer input and output (TIOCB0, TIOCA0, TCLKD, TCLKC, TCLKB, TCLKA), 8-bit timer input (TCLKD, TCLKC, TCLKB, TCLKA), output (TEND1, TEND0) from DMA controller (DMAC), and generic input/output TPC output (TP15 to TP12), SCI2 input and output (SCK2 , RxD2, TxD2), DRAM TPC output (TP15 to interface output (LCAS, UCAS), and generic input/output TP12), SCI2 input and output (SCK2, RxD2, TxD2), and generic input/output TPC output (TP11 to TP8), 8-bit timer input and output (TMIO3, TMO2, TMIO1, TPC output (TP11 to TP8), TMO0), DMAC input (DREQ1, DREQ0), CS7 to CS4 output, and generic 8-bit timer input and input/output output (TMIO3, TMO2, TMIO1, TMO0), DMAC input (DREQ1, DREQ0), and generic input/output Rev. 2.0, 06/04, page 257 of 980 8.2 8.2.1 Port 1 Overview Port 1 is an 8-bit input/output port also used for address output, with the pin configuration shown in figure 8.1. The pin functions differ between the expanded modes with on-chip ROM disabled, expanded modes with on-chip ROM enabled, and single-chip mode. In modes 1 to 4 (expanded modes with on-chip ROM disabled), they are address bus output pins (A7 to A0). In mode 5 (expanded mode with on-chip ROM enabled), settings in the port 1 data direction register (P1DDR) can designate pins for address bus output (A7 to A0) or generic input. In mode 7 (single-chip mode), port 1 is a generic input/output port. When DRAM is connected to areas 2 to 5, A7 to A0 output row and column addresses in read and write cycles. For details see section 6.5, DRAM Interface. Pins in port 1 can drive one TTL load and a 90-pF capacitive load. They can also drive an LED or a darlington transistor pair. Port 1 pins P17 /A 7 P16 /A 6 P15 /A 5 Port 1 P14 /A 4 P13 /A 3 P12 /A 2 P11 /A 1 P10 /A 0 Modes 1 to 4 A 7 (output) A 6 (output) A 5 (output) A 4 (output) A 3 (output) A 2 (output) A 1 (output) A 0 (output) Mode 5 P17 (input)/A 7 (output) P16 (input)/A 6 (output) P15 (input)/A 5 (output) P14 (input)/A 4 (output) P13 (input)/A 3 (output) P12 (input)/A 2 (output) P11 (input)/A 1 (output) P10 (input)/A 0 (output) Mode 7 P17 (input/output) P16 (input/output) P15 (input/output) P14 (input/output) P13 (input/output) P12 (input/output) P11 (input/output) P10 (input/output) Figure 8.1 Port 1 Pin Configuration Rev. 2.0, 06/04, page 258 of 980 8.2.2 Register Descriptions Table 8.2 summarizes the registers of port 1. Table 8.2 Port 1 Registers Initial Value Address* H'EE000 H'FFFD0 Note: * Name Abbreviation R/W W R/W Modes 1 to 4 H'FF H'00 Modes 5 and 7 H'00 H'00 Port 1 data direction register P1DDR Port 1 data register P1DR Lower 20 bits of the address in advanced mode. Port 1 Data Direction Register (P1DDR): P1DDR is an 8-bit write-only register that can select input or output for each pin in port 1. Bit Modes Initial value 1 to 4 Read/Write Modes Initial value 5 and 7 Read/Write 7 1 -- 0 W 6 1 -- 0 W 5 1 -- 0 W 4 1 -- 0 W 3 1 -- 0 W 2 1 -- 0 W 1 1 -- 0 W 0 1 -- 0 W P1 7 DDR P1 6 DDR P1 5 DDR P1 4 DDR P1 3 DDR P1 2 DDR P1 1 DDR P1 0 DDR Port 1 data direction 7 to 0 These bits select input or output for port 1 pins Modes 1 to 4 (Expanded Modes with On-Chip ROM Disabled): P1DDR values are fixed at 1. Port 1 functions as an address bus. Mode 5 (Expanded Mode with On-Chip ROM Enabled): After a reset, port 1 functions as an input port. A pin in port 1 becomes an address output pin if the corresponding P1DDR bit is set to 1, and a generic input pin if this bit is cleared to 0. Mode 7 (Single-Chip Mode): Port 1 functions as an input/output port. A pin in port 1 becomes an output port if the corresponding P1DDR bit is set to 1, and an input port if this bit is cleared to 0. Rev. 2.0, 06/04, page 259 of 980 In modes 1 to 4, P1DDR bits are always read as 1, and cannot be modified. In modes 5 and 7, P1DDR is a write-only register. Its value cannot be read. All bits return 1 when read. P1DDR is initialized to H'FF in modes 1 to 4, and to H'00 in modes 5 and 7, by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Therefore, if a transition is made to software standby mode while port 1 is functioning as an input/output port and a P1DDR bit is set to 1, the corresponding pin maintains its output state. Port 1 Data Register (P1DR): P1DR is an 8-bit readable/writable register that stores port 1 output data. When port 1 functions as an output port, the value of this register is output. When this register is read, the pin logic level is read for bits for which the P1DDR setting is 0, and the P1DR value is read for bits for which the P1DDR setting is 1. Bit Initial value Read/Write 7 P1 7 0 R/W 6 P1 6 0 R/W 5 P1 5 0 R/W 4 P1 4 0 R/W 3 P1 3 0 R/W 2 P1 2 0 R/W 1 P1 1 0 R/W 0 P1 0 0 R/W Port 1 data 7 to 0 These bits store data for port 1 pins P1DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Rev. 2.0, 06/04, page 260 of 980 8.3 8.3.1 Port 2 Overview Port 2 is an 8-bit input/output port also used for address output, with the pin configuration shown in figure 8.2. The pin functions differ according to the operating mode. In modes 1 to 4 (expanded modes with on-chip ROM disabled), port 2 consists of address bus output pins (A15 to A8). In mode 5 (expanded mode with on-chip ROM enabled), settings in the port 2 data direction register (P2DDR) can designate pins for address bus output (A15 to A8) or generic input. In mode 7 (single-chip mode), port 2 is a generic input/output port. When DRAM is connected to areas 2 to 5, A12 to A8 output row and column addresses in read and write cycles. For details see section 6.5, DRAM Interface. Port 2 has software-programmable built-in pull-up transistors. Pins in port 2 can drive one TTL load and a 90-pF capacitive load. They can also drive an LED or a darlington transistor pair. Port 2 pins P27 /A 15 P26 /A 14 P25 /A 13 Port 2 P24 /A 12 P23 /A 11 P22 /A 10 P21 /A 9 P20 /A 8 Modes 1 to 4 A15 (output) A14 (output) A13 (output) A12 (output) A11 (output) A10 (output) A9 (output) A8 (output) Mode 5 P27 (input)/A15 (output) P26 (input)/A14 (output) P25 (input)/A13 (output) P24 (input)/A12 (output) P23 (input)/A11 (output) P22 (input)/A10 (output) P21 (input)/A9 (output) P20 (input)/A8 (output) Mode 7 P27 (input/output) P26 (input/output) P25 (input/output) P24 (input/output) P23 (input/output) P22 (input/output) P21 (input/output) P20 (input/output) Figure 8.2 Port 2 Pin Configuration Rev. 2.0, 06/04, page 261 of 980 8.3.2 Register Descriptions Table 8.3 summarizes the registers of port 2. Table 8.3 Port 2 Registers Initial Value Address* H'EE001 H'FFFD1 H'EE03C Name Port 2 data direction register Port 2 data register Port 2 input pull-up MOS control register Abbreviation R/W Modes 1 to 4 Modes 5 and 7 P2DDR P2DR P2PCR W H'FF H'00 H'00 H'00 R/W H'00 R/W H'00 Note: * Lower 20 bits of the address in advanced mode. Port 2 Data Direction Register (P2DDR): P2DDR is an 8-bit write-only register that can select input or output for each pin in port 2. Bit Modes Initial value 1 to 4 Read/Write Modes Initial value 5 and 7 Read/Write 7 1 -- 0 W 6 1 -- 0 W 5 1 -- 0 W 4 1 -- 0 W 3 1 -- 0 W 2 1 -- 0 W 1 1 -- 0 W 0 1 -- 0 W P2 7 DDR P2 6 DDR P2 5 DDR P2 4 DDR P2 3 DDR P2 2 DDR P2 1 DDR P2 0 DDR Port 2 data direction 7 to 0 These bits select input or output for port 2 pins Modes 1 to 4 (Expanded Modes with On-Chip ROM Disabled): P2DDR values are fixed at 1. Port 2 functions as an address bus. Mode 5 (Expanded Mode with On-Chip ROM Enabled): Following a reset, port 2 is an input port. A pin in port 2 becomes an address output pin if the corresponding P2DDR bit is set to 1, and a generic input port if this bit is cleared to 0. Mode 7 (Single-Chip Mode): Port 2 functions as an input/output port. A pin in port 2 becomes an output port if the corresponding P2DDR bit is set to 1, and an input port if this bit is cleared to 0. Rev. 2.0, 06/04, page 262 of 980 In modes 1 to 4, P2DDR bits are always read as 1, and cannot be modified. In modes 5 and 7, P2DDR is a write-only register. Its value cannot be read. All bits return 1 when read. P2DDR is initialized to H'FF in modes 1 to 4, and to H'00 in modes 5 and 7, by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Therefore, if a transition is made to software standby mode while port 2 is functioning as an input/output port and a P2DDR bit is set to 1, the corresponding pin maintains its output state. Port 2 Data Register (P2DR): P2DR is an 8-bit readable/writable register that stores output data for port 2. When port 2 functions as an output port, the value of this register is output. When a bit in P2DDR is set to 1, if port 2 is read the value of the corresponding P2DR bit is returned. When a bit in P2DDR is cleared to 0, if port 2 is read the corresponding pin logic level is read. Bit Initial value Read/Write 7 P2 0 R/W 7 6 P2 6 0 R/W 5 P2 5 0 R/W 4 P2 4 0 R/W 3 P2 3 0 R/W 2 P2 2 0 R/W 1 P2 1 0 R/W 0 P2 0 0 R/W Port 2 data 7 to 0 These bits store data for port 2 pins P2DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Port 2 Input Pull-Up MOS Control Register (P2PCR): P2PCR is an 8-bit readable/writable register that controls the MOS input pull-up transistors in port 2. Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W P2 7 PCR P2 6 PCR P2 5 PCR P2 4 PCR P2 3 PCR P2 2 PCR P2 1 PCR P2 0 PCR Port 2 input pull-up MOS control 7 to 0 These bits control input pull-up transistors built into port 2 In modes 5 and 7, when a P2DDR bit is cleared to 0 (selecting generic input), if the corresponding bit in P2PCR is set to 1, the input pull-up transistor is turned on. P2PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Rev. 2.0, 06/04, page 263 of 980 Table 8.4 Mode 1 2 3 4 5 7 Input Pull-Up Transistor States (Port 2) Hardware Standby Mode Off Software Standby Mode Off Other Modes Off Reset Off Off Off On/off On/off Legend Off: The input pull-up transistor is always off. On/off: The input pull-up transistor is on if P2PCR = 1 and P2DDR = 0. Otherwise, it is off. Rev. 2.0, 06/04, page 264 of 980 8.4 8.4.1 Port 3 Overview Port 3 is an 8-bit input/output port also used for data bus, with the pin configuration shown in figure 8.3. Port 3 is a data bus in modes 1 to 5 (expanded modes) and a generic input/output port in mode 7 (single-chip mode). Pins in port 3 can drive one TTL load and a 90-pF capacitive load. They can also drive a darlington transistor pair. Port 3 pins P37 /D15 P36 /D14 P35 /D13 Port 3 P34 /D12 P33 /D11 P32 /D10 P31 /D9 P30 /D8 Modes 1 to 5 D15 (input/output) D14 (input/output) D13 (input/output) D12 (input/output) D11 (input/output) D10 (input/output) D9 (input/output) D8 (input/output) Mode 7 P37 (input/output) P36 (input/output) P35 (input/output) P34 (input/output) P33 (input/output) P32 (input/output) P31 (input/output) P30 (input/output) Figure 8.3 Port 3 Pin Configuration 8.4.2 Register Descriptions Table 8.5 summarizes the registers of port 3. Table 8.5 Address* H'EE002 H'FFFD2 Port 3 Registers Name Port 3 data direction register Port 3 data register Abbreviation P3DDR P3DR R/W W R/W Initial Value H'00 H'00 Note: * Lower 20 bits of the address in advanced mode. Rev. 2.0, 06/04, page 265 of 980 Port 3 Data Direction Register (P3DDR): P3DDR is an 8-bit write-only register that can select input or output for each pin in port 3. Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W P3 7 DDR P3 6 DDR P3 5 DDR P3 4 DDR P3 3 DDR P3 2 DDR P3 1 DDR P3 0 DDR Port 3 data direction 7 to 0 These bits select input or output for port 3 pins Modes 1 to 5 (Expanded Modes): Port 3 functions as a data bus, regardless of the P3DDR settings. Mode 7 (Single-Chip Mode): Port 3 functions as an input/output port. A pin in port 3 becomes an output port if the corresponding P3DDR bit is set to 1, and an input port if this bit is cleared to 0. P3DDR is a write-only register. Its value cannot be read. All bits return 1 when read. P3DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Therefore, if a transition is made to software standby mode while port 3 is functioning as an input/output port and a P3DDR bit is set to 1, the corresponding pin maintains its output state. Port 3 Data Register (P3DR): P3DR is an 8-bit readable/writable register that stores output data for port 3. When port 3 functions as an output port, the value of this register is output. When a bit in P3DDR is set to 1, if port 3 is read the value of the corresponding P3DR bit is returned. When a bit in P3DDR is cleared to 0, if port 3 is read the corresponding pin logic level is read. Bit Initial value Read/Write 7 P3 0 R/W 7 6 P3 0 R/W 6 5 P3 0 R/W 5 4 P3 0 R/W 4 3 P3 0 R/W 3 2 P3 0 R/W 2 1 P3 0 R/W 1 0 P3 0 R/W 0 Port 3 data 7 to 0 These bits store data for port 3 pins P3DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Rev. 2.0, 06/04, page 266 of 980 8.5 8.5.1 Port 4 Overview Port 4 is an 8-bit input/output port also used for data bus, with the pin configuration shown in figure 8.4. The pin functions differ depending on the operating mode. In modes 1 to 5 (expanded modes), when the bus width control register (ABWCR) designates areas 0 to 7 all as 8-bit-access areas, the chip operates in 8-bit bus mode and port 4 is a generic input/output port. When at least one of areas 0 to 7 is designated as a 16-bit-access area, the chip operates in 16-bit bus mode and port 4 becomes part of the data bus. In mode 7 (single-chip mode), port 4 is a generic input/output port. Port 4 has software-programmable built-in pull-up transistors. Pins in port 4 can drive one TTL load and a 90-pF capacitive load. They can also drive a darlington transistor pair. Port 4 pins P47 /D7 P46 /D6 P45 /D5 Port 4 P44 /D4 P43 /D3 P42 /D2 P41 /D1 P40 /D0 Modes 1 to 5 P47 (input/output)/D7 (input/output) P46 (input/output)/D6 (input/output) P45 (input/output)/D5 (input/output) P44 (input/output)/D4 (input/output) P43 (input/output)/D3 (input/output) P42 (input/output)/D2 (input/output) P41 (input/output)/D1 (input/output) P40 (input/output)/D0 (input/output) Mode 7 P47 (input/output) P46 (input/output) P45 (input/output) P44 (input/output) P43 (input/output) P42 (input/output) P41 (input/output) P40 (input/output) Figure 8.4 Port 4 Pin Configuration Rev. 2.0, 06/04, page 267 of 980 8.5.2 Register Descriptions Table 8.6 summarizes the registers of port 4. Table 8.6 Address* H'EE003 H'FFFD3 H'EE03E Note: * Port 4 Registers Name Port 4 data direction register Port 4 data register Port 4 input pull-up control register Abbreviation P4DDR P4DR P4PCR R/W W R/W R/W Initial Value H'00 H'00 H'00 Lower 20 bits of the address in advanced mode. Port 4 Data Direction Register (P4DDR): P4DDR is an 8-bit write-only register that can select input or output for each pin in port 4. Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W P4 7 DDR P4 6 DDR P4 5 DDR P4 4 DDR P4 3 DDR P4 2 DDR P4 1 DDR P4 0 DDR Port 4 data direction 7 to 0 These bits select input or output for port 4 pins Modes 1 to 5 (Expanded Modes): When all areas are designated as 8-bit-access areas by the bus controller's bus width control register (ABWCR), selecting 8-bit bus mode, port 4 functions as an input/output port. In this case, a pin in port 4 becomes an output port if the corresponding P4DDR bit is set to 1, and an input port if this bit is cleared to 0. When at least one area is designated as a 16-bit-access area, selecting 16-bit bus mode, port 4 functions as part of the data bus, regardless of the P4DDR settings. Mode 7 (Single-Chip Mode): Port 4 functions as an input/output port. A pin in port 4 becomes an output port if the corresponding P4DDR bit is set to 1, and an input port if this bit is cleared to 0. P4DDR is a write-only register. Its value cannot be read. All bits return 1 when read. P4DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Rev. 2.0, 06/04, page 268 of 980 ABWCR and P4DDR are not initialized in software standby mode. Therefore, if a transition is made to software standby mode while port 4 is functioning as an input/output port and a P4DDR bit is set to 1, the corresponding pin maintains its output state. Port 4 Data Register (P4DR): P4DR is an 8-bit readable/writable register that stores output data for port 4. When port 4 functions as an output port, the value of this register is output. When a bit in P4DDR is set to 1, if port 4 is read the value of the corresponding P4DR bit is returned. When a bit in P4DDR is cleared to 0, if port 4 is read the corresponding pin logic level is read. Bit Initial value Read/Write 7 P4 7 0 R/W 6 P4 6 0 R/W 5 P4 5 0 R/W 4 P4 4 0 R/W 3 P4 3 0 R/W 2 P4 2 0 R/W 1 P4 1 0 R/W 0 P4 0 0 R/W Port 4 data 7 to 0 These bits store data for port 4 pins P4DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Port 4 Input Pull-Up MOS Control Register (P4PCR): P4PCR is an 8-bit readable/writable register that controls the MOS input pull-up transistors in port 4. Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W P4 7 PCR P4 6 PCR P4 5 PCR P4 4 PCR P4 3 PCR P4 2 PCR P4 1 PCR P4 0 PCR Port 4 input pull-up control 7 to 0 These bits control input pull-up transistors built into port 4 In mode 7 (single-chip mode), and in 8-bit bus mode in modes 1 to 5 (expanded modes), when a P4DDR bit is cleared to 0 (selecting generic input), if the corresponding P4PCR bit is set to 1, the input pull-up transistor is turned on. P4PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Rev. 2.0, 06/04, page 269 of 980 Table 8.7 summarizes the states of the input pull-up transistors in each operating mode. Table 8.7 Mode 1 to 5 7 8-bit bus mode 16-bit bus mode Input Pull-Up Transistor States (Port 4) Reset Off Hardware Standby Mode Off Software Standby Mode On/off Off On/off Other Modes On/off Off On/off Legend Off: The input pull-up transistor is always off. On/off: The input pull-up transistor is on if P4PCR = 1 and P4DDR = 0. Otherwise, it is off. Rev. 2.0, 06/04, page 270 of 980 8.6 8.6.1 Port 5 Overview Port 5 is a 4-bit input/output port also used for address output, with the pin configuration shown in figure 8.5. The pin functions differ depending on the operating mode. In modes 1 to 4 (expanded modes with on-chip ROM disabled), port 5 consists of address output pins (A19 to A16). In mode 5 (expanded mode with on-chip ROM enabled), settings in the port 5 data direction register (P5DDR) designate pins for address bus output (A19 to A16) or generic input. In mode 7 (single-chip mode), port 5 is a generic input/output port. Port 5 has software-programmable built-in pull-up transistors. Pins in port 5 can drive one TTL load and a 90-pF capacitive load. They can also drive an LED or a darlington transistor pair. Port 5 pins P53 /A 19 Port 5 P52 /A 18 P51 /A 17 P50 /A 16 Modes 1 to 4 A19 (output) A18 (output) A17 (output) A16 (output) Mode 5 P5 3 (input)/A19 (output) P5 2 (input)/A18 (output) P5 1 (input)/A17 (output) P5 0 (input)/A16 (output) Mode 7 P5 3 (input/output) P5 2 (input/output) P5 1 (input/output) P5 0 (input/output) Figure 8.5 Port 5 Pin Configuration 8.6.2 Register Descriptions Table 8.8 summarizes the registers of port 5. Table 8.8 Port 5 Registers Initial Value Address* Name H'EE004 Port 5 data direction register Abbreviation P5DDR P5DR R/W Modes 1 to 4 Modes 5 and 7 W H'FF H'F0 H'F0 H'F0 R/W H'F0 R/W H'F0 H'FFFD4 Port 5 data register Note: * H'EE03F Port 5 input pull-up control register P5PCR Lower 20 bits of the address in advanced mode. Rev. 2.0, 06/04, page 271 of 980 Port 5 Data Direction Register (P5DDR): P5DDR is an 8-bit write-only register that can select input or output for each pin in port 5. Bits 7 to 4 are reserved. They are fixed at 1, and cannot be modified. Bit Modes Initial value 1 to 4 Read/Write Modes Initial value 5 and 7 Read/Write 7 -- 1 -- 1 -- 6 -- 1 -- 1 -- Reserved bits 5 -- 1 -- 1 -- 4 -- 1 -- 1 -- 3 1 -- 0 W 2 1 -- 0 W 1 1 -- 0 W 0 1 -- 0 W P5 3 DDR P5 2 DDR P5 1 DDR P5 0 DDR Port 5 data direction 3 to 0 These bits select input or output for port 5 pins Modes 1 to 4 (Expanded Modes with On-Chip ROM Disabled): P5DDR values are fixed at 1. Port 5 functions as an address bus. Mode 5 (Expanded Mode with On-Chip ROM Enabled): Following a reset, port 5 is an input port. A pin in port 5 becomes an address output pin if the corresponding P5DDR bit is set to 1, and an input port if this bit is cleared to 0. Mode 7 (Single-Chip Mode): Port 5 functions as an input/output port. A pin in port 5 becomes an output port if the corresponding P5DDR bit is set to 1, and an input port if this bit is cleared to 0. In modes 1 to 4, P5DDR bits are always read as 1, and cannot be modified. In modes 5 and 7, P5DDR is a write-only register. Its value cannot be read. All bits return 1 when read. P5DDR is initialized to H'FF in modes 1 to 4, and to H'F0 in modes 5 and 7, by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Therefore, if a transition is made to software standby mode while port 5 is functioning as an input/output port and a P5DDR bit is set to 1, the corresponding pin maintains its output state. Rev. 2.0, 06/04, page 272 of 980 Port 5 Data Register (P5DR): P5DR is an 8-bit readable/writable register that stores output data for port 5. When port 5 functions as an output port, the value of this register is output. When a bit in P5DDR is set to 1, if port 5 is read the value of the corresponding P5DR bit is returned. When a bit in P5DDR is cleared to 0, if port 5 is read the corresponding pin logic level is read. Bits 7 to 4 are reserved. They are fixed at 1, and cannot be modified. Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 P5 0 R/W 3 2 P5 0 R/W 2 1 P5 0 R/W 1 0 P5 0 R/W 0 Reserved bits Port 5 data 3 to 0 These bits store data for port 5 pins P5DR is initialized to H'F0 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Port 5 Input Pull-Up MOS Control Register (P5PCR): P5PCR is an 8-bit readable/writable register that controls the MOS input pull-up transistors in port 5. Bits 7 to 4 are reserved. They are fixed at 1, and cannot be modified. Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W P5 3 PCR P5 2 PCR P5 1 PCR P5 0 PCR Reserved bits Port 5 input pull-up control 3 to 0 These bits control input pull-up transistors built into port 5 In modes 5 and 7, when a P5DDR bit is cleared to 0 (selecting generic input), if the corresponding bit in P5PCR is set to 1, the input pull-up transistor is turned on. P5PCR is initialized to H'F0 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Table 8.9 summarizes the states of the input pull-ups in each mode. Rev. 2.0, 06/04, page 273 of 980 Table 8.9 Mode 1 2 3 4 5 7 Input Pull-Up Transistor States (Port 5) Hardware Standby Mode Off Software Standby Mode Off Other Modes Off Reset Off Off Off On/off On/off Legend Off: The input pull-up transistor is always off. On/off: The input pull-up transistor is on if P5PCR = 1 and P5DDR = 0. Otherwise, it is off. Rev. 2.0, 06/04, page 274 of 980 8.7 8.7.1 Port 6 Overview Port 6 is an 8-bit input/output port that is also used for input and output of bus control signals (LWR, HWR, RD, AS, BACK, BREQ, WAIT) and for clock () output. The pin configuration of port 6 is shown in figure 8.6. In modes 1 to 5 (expanded modes), the pin functions are P67 (generic input)/, LWR, HWR, RD, AS, P62/BACK, P61/BREQ, and P60/WAIT). See table 8.11 for the selection of the pin functions. In mode 7 (single-chip mode), P67 functions as a generic input port or o output, and P66 to P60 function as generic input/output ports. When DRAM is connected to areas 2 to 5, LWR, HWR, and RD also function as LCAS, UCAS, and WE, respectively. For details see section 6.5, DRAM Interface. Pins in port 6 can drive one TTL load and a 90-pF capacitive load. They can also drive a darlington transistor pair. Port 6 pins P6 7 / P6 6 / LWR P6 5 / HWR Port 6 P6 4 / RD P6 3 / AS P6 2 / BACK P6 1 / BREQ P6 0 / WAIT Modes 1 to 5 (expanded modes) P67 (input)/ (output) (output) (output) (output) (output) Mode 7 (single-chip mode) P6 7 (input) / (output) P6 6 (input/output) P6 5 (input/output) P6 4 (input/output) P6 3 (input/output) P6 2 (input/output) P6 1 (input/output) P6 0 (input/output) LWR HWR RD AS P62 (input/output)/ BACK (output) P61 (input/output)/ BREQ (input) P60 (input/output)/ WAIT (input) Figure 8.6 Port 6 Pin Configuration Rev. 2.0, 06/04, page 275 of 980 8.7.2 Register Descriptions Table 8.10 summarizes the registers of port 6. Table 8.10 Port 6 Registers Address* H'EE005 H'FFFD5 Note: * Name Port 6 data direction register Port 6 data register Abbreviation P6DDR P6DR R/W W R/W Initial Value H'80 H'80 Lower 20 bits of the address in advanced mode. Port 6 Data Direction Register (P6DDR): P6DDR is an 8-bit write-only register that can select input or output for each pin in port 6. Bit 7 is reserved. It is fixed at 1, and cannot be modified. Bit Initial value Read/Write 7 -- 1 -- Reserved bit 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W P6 6 DDR P6 5 DDR P6 4 DDR P6 3 DDR P6 2 DDR P6 1 DDR P6 0 DDR Port 6 data direction 6 to 0 These bits select input or output for port 6 pins Modes 1 to 5 (Expanded Modes): P67 functions as the clock output pin () or an input port. P67 is the clock output pin () if the PSTOP bit in MSTRCH is cleared to 0 (initial value), and an input port if this bit is set to 1. P66 to P63 function as bus control output pins (LWR, HWR, RD, and AS), regardless of the settings of bits P66DDR to P63DDR. P62 to P60 function as bus control input/output pins (BACK, BREQ, and WAIT) or input/output ports. For the method of selecting the pin functions, see table 8.11. When P62 to P60 function as input/output ports, the pin becomes an output port if the corresponding P6DDR bit is set to 1, and an input port if this bit is cleared to 0. Mode 7 (Single-Chip Mode): P67 functions as the clock output pin () or an input port. P66 to P60 function as generic input/output ports. P67 is the clock output pin () if the PSTOP bit in MSTCRH is cleared to 0, and an input port if this bit is set to 1 (initial value). A pin in port 6 becomes an output port if the corresponding bit of P66DDR to P60DDR is set to 1, and an input port if this pin is cleared to 0. Rev. 2.0, 06/04, page 276 of 980 P6DDR is a write-only register. Its value cannot be read. All bits return 1 when read. P6DDR is initialized to H'80 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Therefore, if a transition is made to software standby mode while port 6 is functioning as an input/output port and a P6DDR bit is set to 1, the corresponding pin maintains its output state. Port 6 Data Register (P6DR): P6DR is an 8-bit readable/writable register that stores output data for port 6. When port 6 functions as an output port, the value of this register is output. For bit 7, a value of 1 is returned if the bit is read while the PSTOP bit in MSTCRH is cleared to 0, and the P67 pin logic level is returned if the bit is read while the PSTOP bit is set to 1. Bit 7 cannot be modified. For bits 6 to 0, the pin logic level is returned if the bit is read while the corresponding bit in P6DDR is cleared to 0, and the P6DR value is returned if the bit is read while the corresponding bit in P6DDR is set to 1. Bit Initial value Read/Write 7 P67 1 R 6 P6 6 0 R/W 5 P6 5 0 R/W 4 P6 4 0 R/W 3 P6 3 0 R/W 2 P6 2 0 R/W 1 P6 1 0 R/W 0 P6 0 0 R/W Port 6 data 7 to 0 These bits store data for port 6 pins P6DR is initialized to H'80 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Rev. 2.0, 06/04, page 277 of 980 Table 8.11 Port 6 Pin Functions in Modes 1 to 5 Pin P67/ Pin Functions and Selection Method Bit PSTOP in MSTCRH selects the pin function. PSTOP Pin function LWR 0 output 1 P67 input Functions as LWR regardless of the setting of bit P66DDR. P66DDR Pin function 0 LWR output* 1 Note: * If any of bits DRAS2 to DRAS0 in DRCRA is 1 and bit CSEL in DRCRB is 1, LWR output functions as LCAS. HWR Functions as HWR regardless of the setting of bit P65DDR. P65DDR Pin function 0 HWR output* 1 Note: * If any of bits DRAS2 to DRAS0 in DRCRA is 1 and bit CSEL in DRCRB is 1, HWR output functions as UCAS. RD Functions as RD regardless of the setting of bit P64DDR. P64DDR Pin function 0 RD output* 1 Note: * If any of bits DRAS2 to DRAS0 in DRCRA is 1, RD output functions as WE. AS Functions as AS regardless of the setting of bit P63DDR. P63DDR Pin function P62/BACK 0 AS output 1 Bit BRLE in BRCR and bit P62DDR select the pin function as follows. BRLE P62DDR Pin function 0 P62 input 0 1 P62 output 1 -- BACK output P61/BREQ Bit BRLE in BRCR and bit P61DDR select the pin function as follows. BRLE P61DDR Pin function 0 P61 input 0 1 P61 output 1 -- BREQ input P60/WAIT Bit WAITE in BCR and bit P60DDR select the pin function as follows. WAITE P60DDR Pin function 0 P60 input 0 1 P60 output 1 0* WAIT input Note: * Do not set bit P60DDR to 1. Rev. 2.0, 06/04, page 278 of 980 8.8 8.8.1 Port 7 Overview Port 7 is an 8-bit input port that is also used for analog input to the A/D converter and analog output from the D/A converter. The pin functions are the same in all operating modes. Figure 8.7 shows the pin configuration of port 7. See section 15, A/D Converter, for details of the A/D converter analog input pins, and section 16, D/A Converter, for details of the D/A converter analog output pins. Port 7 pins P77 (input)/AN 7 (input)/DA 1 (output) P76 (input)/AN 6 (input)/DA 0 (output) P75 (input)/AN 5 (input) Port 7 P74 (input)/AN 4 (input) P73 (input)/AN 3 (input) P72 (input)/AN 2 (input) P71 (input)/AN 1 (input) P70 (input)/AN 0 (input) Figure 8.7 Port 7 Pin Configuration Rev. 2.0, 06/04, page 279 of 980 8.8.2 Register Description Table 8.12 summarizes the port 7 register. Port 7 is an input port, and port 7 has no data direction register. Table 8.12 Port 7 Data Register Address* H'FFFD6 Note: * Name Port 7 data register Abbreviation P7DR R/W R Initial Value Undetermined Lower 20 bits of the address in advanced mode. Port 7 Data Register (P7DR) Bit Initial value Read/Write 7 P77 --* R 6 P76 --* R 5 P75 --* R 4 P74 --* R 3 P73 --* R 2 P72 --* R 1 P71 --* R 0 P70 --* R Note: * Determined by pins P7 7 to P70 . When port 7 is read, the pin logic levels are always read. P7DR cannot be modified. Rev. 2.0, 06/04, page 280 of 980 8.9 8.9.1 Port 8 Overview Port 8 is a 5-bit input/output port that is also used for CS3 to CS0 output, RFSH output, IRQ3 to IRQ0 input, and A/D converter ADTRG input. Figure 8.8 shows the pin configuration of port 8. In modes 1 to 5 (expanded modes), port 8 can provide CS3 to CS0 output, RFSH output, IRQ3 to IRQ0 input, and ADTRG input. See table 8.14 for the selection of pin functions in expanded modes. In mode 7 (single-chip mode), port 8 can provide IRQ3 to IRQ0 input and ADTRG input. See table 8.15 for the selection of pin functions in single-chip mode. See section 15, A/D Converter, for a description of the A/D converter's ADTRG input pin. The IRQ3 to IRQ0 functions are selected by IER settings, regardless of whether the pin is used for input or output. Caution is therefore required. For details see section 5.3.1, External Interrupts. When DRAM is connected to areas 2 to 5, the CS3 and CS2 output pins function as RAS output pins for each area. For details see section 6.5, DRAM Interface. Pins in port 8 can drive one TTL load and a 90-pF capacitive load. They can also drive a darlington transistor pair. Pins P82 to P80 have Schmitt-trigger inputs. Rev. 2.0, 06/04, page 281 of 980 Port 8 pins Pin functions in modes 1 to 5 (expanded modes) P84 (input)/ CS 0 (output) P83 (input)/ CS 1 (output)/ IRQ 3 (input) / ADTRG (input) P82 (input)/ CS 2 (output)/ IRQ 2 (input) P81 (input/output)/ CS3 (output)/IRQ1(input) P80 (input/output)/ RFSH (output)/ IRQ 0 (input) P84 / CS 0 P83 / CS 1 / IRQ 3 / ADTRG Port 8 P82 / CS 2 / IRQ 2 P81 / CS 3 / IRQ 1 P80 / RFSH /IRQ 0 Pin functions in mode 7 (single-chip mode) P84 /(input/output) P83 /(input/output)/ IRQ 3 (input) / ADTRG (input) P82 /(input/output)/ IRQ 2 (input) P81 /(input/output)/ IRQ 1 (input) P80 /(input/output)/ IRQ 0 (input) Figure 8.8 Port 8 Pin Configuration Rev. 2.0, 06/04, page 282 of 980 8.9.2 Register Descriptions Table 8.13 summarizes the registers of port 8. Table 8.13 Port 8 Registers Initial Value Address* H'EE007 H'FFFD7 Note: * Name Port 8 data direction register Port 8 data register Abbreviation P8DDR P8DR R/W W R/W Modes 1 to 4 H'F0 H'E0 Modes 5 and 7 H'E0 H'E0 Lower 20 bits of the address in advanced mode. Port 8 Data Direction Register (P8DDR): P8DDR is an 8-bit write-only register that can select input or output for each pin in port 8. Bits 7 to 5 are reserved. They are fixed at 1, and cannot be modified. Bit Modes Initial value 1 to 4 Read/Write Modes Initial value 5 and 7 Read/Write 7 -- 1 -- 1 -- 6 -- 1 -- 1 -- 5 -- 1 -- 1 -- 4 1 W 0 W 3 0 W 0 W 2 0 W 0 W 1 0 W 0 W 0 0 W 0 W P8 4 DDR P8 3 DDR P8 2 DDR P8 1 DDR P8 0 DDR Reserved bits Port 8 data direction 4 to 0 These bits select input or output for port 8 pins Modes 1 to 5 (Expanded Modes): When bits in P8DDR bit are set to 1, P84 to P81 become CS0 to CS3 output pins. When bits in P8DDR are cleared to 0, the corresponding pins become input ports. However, P81 can also be used as an output port, depending on the setting of bits DRAS2 to DRAS0 in DRAM control register A (DRCRA). For details see section 6.5.2, DRAM Space and RAS Output Pin Settings. In modes 1 to 4 (expanded modes with on-chip ROM disabled), following a reset P84 functions as the CS0 output, while CS1 to CS3 are input ports. In mode 5 (expanded mode with on-chip ROM enabled), following a reset CS0 to CS3 are all input ports. When the refresh enable bit (RFSHE) in DRCRA is set to 1, P80 is used for RFSH output. When RFSHE is cleared to 0, P80 becomes an input/output port according to the P8DDR setting. For details see table 8.14. Rev. 2.0, 06/04, page 283 of 980 Mode 7 (Single-Chip Mode): Port 8 is a generic input/output port. A pin in port 8 becomes an output port if the corresponding P8DDR bit is set to 1, and an input port if this bit is cleared to 0. P8DDR is a write-only register. Its value cannot be read. All bits return 1 when read. P8DDR is initialized to H'F0 in modes 1 to 4, and to H'E0 in modes 5 and 7, by a reset and in hardware standby mode. In software standby mode P8DDR retains its previous setting. Therefore, if a transition is made to software standby mode while port 8 is functioning as an input/output port and a P8DDR bit is set to 1, the corresponding pin maintains its output state. Port 8 Data Register (P8DR): P8DR is an 8-bit readable/writable register that stores output data for port 8. When port 8 functions as an output port, the value of this register is output. When a bit in P8DDR is set to 1, if port 8 is read the value of the corresponding P8DR bit is returned. When a bit in P8DDR is cleared to 0, if port 8 is read the corresponding pin logic level is read. Bits 7 to 5 are reserved. They are fixed at 1, and cannot be modified. Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- Reserved bits 5 -- 1 -- 4 P8 0 R/W 4 3 P8 0 R/W 3 2 P8 0 R/W 2 1 P8 0 R/W 1 0 P8 0 R/W 0 Port 8 data 4 to 0 These bits store data for port 8 pins P8DR is initialized to H'E0 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Rev. 2.0, 06/04, page 284 of 980 Table 8.14 Port 8 Pin Functions in Modes 1 to 5 Pin P84/CS0 Pin Functions and Selection Method Bit P84DDR selects the pin function as follows. P84DDR Pin function P83/CS1/IRQ3/ADTRG 0 P84 input 1 CS0 output Bit P83DDR selects the pin function as follows. P83DDR Pin function 0 P83 input IRQ3 input ADTRG input 1 CS1 output P82/CS2/IRQ2 The DRAM interface settings by bits DRAS2 to DRAS0 in DRCRA, and bit P82DDR, select the pin function as follows. DRAM interface settings P82DDR Pin function (1) in table below 0 P82 input 1 CS2 output IRQ3 input Note: * CS2 is output as RAS2. DRAM interface setting DRAS2 DRAS1 DRAS0 0 0 1 0 (1) 0 1 1 0 0 1 0 (2) 1 1 1 |(2) in table below -- CS2 output* P81/CS3/IRQ1 The DRAM interface settings by bits DRAS2 to DRAS0 in DRCRA, and bit P81DDR, select the pin function as follows. DRAM interface settings P81DDR Pin function (1) in table below 0 1 (2) in table below 0 1 P81 output pin (3) in table below -- CS3 output pin* P81 input CS3 output P81 input pin pin pin IRQ1 input pin Note: * CS3 is output as RAS3. DRAM interface setting DRAS2 DRAS1 DRAS0 P80/RFSH/IRQ0 0 0 1 0 (1) 0 1 1 0 0 1 0 (3) (2) (3) 1 1 1 (2) Bit RFSHE in DRCRA and bit P80DDR select the pin function as follows. RFSHE P80DDR Pin function 0 P80 input 0 1 P80 output IRQ0 input Note: * If areas 2 to 5 are not designated as DRAM space, this bit should not be set to 1. 1* -- RFSH output Rev. 2.0, 06/04, page 285 of 980 Table 8.15 Port 8 Pin Functions in Mode 7 Pin P84 Pin Functions and Selection Method Bit P84DDR selects the pin function as follows. P84DDR Pin function P83/IRQ3/ADTRG 0 P84 input 1 P84 output Bit P83DDR selects the pin function as follows. P83DDR Pin function 0 P83 input IRQ3 input ADTRG input 1 P83 output P82/IRQ2 Bit P82DDR selects the pin function as follows. P82DDR Pin function 0 P82 input IRQ2 input 1 P82 output P81/IRQ1 Bit P81DDR selects the pin function as follows. P81DDR Pin function 0 P81 input IRQ1 input 1 P81 output P80/IRQ0 Bit P80DDR select the pin function as follows. P80DDR Pin function 0 P80 input IRQ0 input 1 P80 output Rev. 2.0, 06/04, page 286 of 980 8.10 8.10.1 Port 9 Overview Port 9 is a 6-bit input/output port that is also used for input and output (TxD0, TxD1, RxD0, RxD1, SCK0, SCK1) by serial communication interface channels 0 and 1 (SCI0 and SCI1), and for IRQ5 and IRQ4 input. See table 8.17 for the selection of pin functions. The IRQ5 and IRQ4 functions are selected by IER settings, regardless of whether the pin is used for input or output. Caution is therefore required. For details see section 5.3.1, External Interrupts. Port 9 has the same set of pin functions in all operating modes. Figure 8.9 shows the pin configuration of port 9. Pins in port 9 can drive one TTL load and a 30-pF capacitive load. They can also drive a darlington transistor pair. Port 9 pins P95 (input/output)/SCK 1 (input/output)/IRQ 5 (input) P94 (input/output)/SCK 0 (input/output)/IRQ 4 (input) Port 9 P93 (input/output)/RxD1 (input) P92 (input/output)/RxD0 (input) P91 (input/output)/TxD1 (output) P90 (input/output)/TxD0 (output) Figure 8.9 Port 9 Pin Configuration Rev. 2.0, 06/04, page 287 of 980 8.10.2 Register Descriptions Table 8.16 summarizes the registers of port 9. Table 8.16 Port 9 Registers Address* H'EE008 H'FFFD8 Note: * Name Port 9 data direction register Port 9 data register Abbreviation P9DDR P9DR R/W W R/W Initial Value H'C0 H'C0 Lower 20 bits of the address in advanced mode. Port 9 Data Direction Register (P9DDR): P9DDR is an 8-bit write-only register that can select input or output for each pin in port 9. Bits 7 and 6 are reserved. They are fixed at 1, and cannot be modified. Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W P9 5 DDR P9 4 DDR P9 3 DDR P9 2 DDR P9 1 DDR P9 0 DDR Reserved bits Port 9 data direction 5 to 0 These bits select input or output for port 9 pins When port 9 functions as an input/output port, a pin in port 9 becomes an output port if the corresponding P9DDR bit is set to 1, and an input port if this bit is cleared to 0. For the method of selecting the pin functions, see table 8.17. P9DDR is a write-only register. Its value cannot be read. All bits return 1 when read. P9DDR is initialized to H'C0 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Therefore, if a transition is made to software standby mode while port 9 is functioning as an input/output port and a P9DDR bit is set to 1, the corresponding pin maintains its output state. Rev. 2.0, 06/04, page 288 of 980 Port 9 Data Register (P9DR): P9DR is an 8-bit readable/writable register that stores output data for port 9. When port 9 functions as an output port, the value of this register is output. When a bit in P9DDR is set to 1, if port 9 is read the value of the corresponding P9DR bit is returned. When a bit in P9DDR is cleared to 0, if port 9 is read the corresponding pin logic level is read. Bits 7 and 6 are reserved. They are fixed at 1, and cannot be modified. Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 P9 5 0 R/W 4 P9 4 0 R/W 3 P9 3 0 R/W 2 P9 2 0 R/W 1 P9 1 0 R/W 0 P9 0 0 R/W Reserved bits Port 9 data 5 to 0 These bits store data for port 9 pins P9DR is initialized to H'C0 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Rev. 2.0, 06/04, page 289 of 980 Table 8.17 Port 9 Pin Functions Pin P95/SCK1/IRQ5 Pin Functions and Selection Method Bit C/A in SMR of SCI1, bits CKE0 and CKE1 in SCR, and bit P95DDR select the pin function as follows. CKE1 C/A CKE0 P95DDR Pin function 0 P95 input 0 1 P95 output 0 1 -- SCK1 output 0 1 -- -- SCK1 output 1 -- -- -- SCK1 input IRQ5 input P94/SCK0/IRQ4 Bit C/A in SMR of SCI0, bits CKE0 and CKE1 in SCR, and bit P94DDR select the pin function as follows. CKE1 C/A CKE0 P94DDR Pin function 0 P94 input 0 1 P94 output 0 1 -- SCK0 output 0 1 -- -- SCK0 output 1 -- -- -- SCK0 input IRQ4 input P93/RxD1 Bit RE in SCR of SCI1, bit SMIF in SCMR, and bit P93DDR select the pin function as follows. SMIF RE P93DDR Pin function P92/RxD0 0 P93 input 0 1 P93 output 0 1 -- RxD1 input 1 -- -- RxD1 input Bit RE in SCR of SCI0, bit SMIF in SCMR, and bit P92DDR select the pin function as follows. SMIF RE P92DDR Pin function 0 P92 input 0 1 P92 output 0 1 -- RxD0 input 1 -- -- RxD0 input Rev. 2.0, 06/04, page 290 of 980 Pin P91/TxD1 Pin Functions and Selection Method Bit TE in SCR of SCI1, bit SMIF in SCMR, and bit P91DDR select the pin function as follows. SMIF TE P91 DDR Pin function 0 P91 input 0 1 P91 output 0 1 -- TxD1 output 1 -- -- TxD1 output* Note: * Functions as the TxD1 output pin, but there are two states: one in which the pin is driven, and another in which the pin is at high-impedance. P90/TxD0 Bit TE in SCR of SCI0, bit SMIF in SCMR, and bit P90DDR select the pin function as follows. SMIF TE P90DDR Pin function 0 P90 input 0 1 P90 output 0 1 -- TxD0 output 1 -- -- TxD0 output* Note: * Functions as the TxD0 output pin, but there are two states: one in which the pin is driven, and another in which the pin is at high-impedance. Rev. 2.0, 06/04, page 291 of 980 8.11 8.11.1 Port A Overview Port A is an 8-bit input/output port that is also used for output (TP7 to TP0) from the programmable timing pattern controller (TPC), input and output, (TIOCB2, TIOCA2, TIOCB1, TIOCA1, TIOCB0, TIOCA0, TCLKD, TCLKC, TCLKB, TCLKA) by the 16-bit timer, input (TCLKD, TCLKC, TCLKB, TCLKA) to the 8-bit timer, output (TEND1, TEND0) from the DMA controller (DMAC), and address output (A23 to A20). A reset or hardware standby transition leaves port A as an input port, except that in modes 3 and 4, one pin is always used for A20 output. See table 8.19 to 8.21 for the selection of pin functions. Usage of pins for TPC, 16-bit timer, 8-bit timer, and DMAC input and output is described in the sections on those modules. For output of address bits A23 to A20 in modes 3, 4, and 5, see section 6.2.4, Bus Release Control Register (BRCR). Pins not assigned to any of these functions are available for generic input/output. Figure 8.10 shows the pin configuration of port A. Pins in port A can drive one TTL load and a 30-pF capacitive load. They can also drive a darlington transistor pair. Port A has Schmitt-trigger inputs. Rev. 2.0, 06/04, page 292 of 980 Port A pins PA 7 /TP7 /TIOCB2 /A20 PA 6 /TP6 /TIOCA2 /A21 PA 5 /TP5 /TIOCB1 /A22 PA 4 /TP4 /TIOCA1 /A23 Port A PA 3 /TP3 /TIOCB0 /TCLKD PA 2 /TP2 /TIOCA0 /TCLKC PA 1 /TP1 /TEND1 /TCLKB PA 0 /TP0 /TEND0 /TCLKA Pin functions in modes 1, 2, and 7 PA 7 (input/output)/TP 7 (output)/TIOCB 2 (input/output) PA 6 (input/output)/TP 6 (output)/TIOCA 2 (input/output) PA 5 (input/output)/TP 5 (output)/TIOCB 1 (input/output) PA 4 (input/output)/TP 4 (output)/TIOCA 1 (input/output) PA 3 (input/output)/TP 3 (output)/TIOCB 0 (input/output)/TCLKD (input) PA 2 (input/output)/TP 2 (output)/TIOCA 0 (input/output)/TCLKC (input) PA 1 (input/output)/TP 1 (output)/TEND 1 (output)/TCLKB (input) PA 0 (input/output)/TP 0 (output)/TEND 0 (output)/TCLKA (input) Pin functions in modes 3 and 4 A 20 (output) PA 6 (input/output)/TP 6 (output)/TIOCA 2 (input/output)/A 21(output) PA 5 (input/output)/TP 5 (output)/TIOCB 1 (input/output)/A 22(output) PA 4 (input/output)/TP 4 (output)/TIOCA 1 (input/output)/A 23(output) PA 3 (input/output)/TP 3 (output)/TIOCB 0 (input/output)/TCLKD (input) PA 2 (input/output)/TP 2 (output)/TIOCA 0 (input/output)/TCLKC (input) PA 1 (input/output)/TP 1 (output)/TEND 1 (output)/TCLKB (input) PA 0 (input/output)/TP 0 (output)/TEND 0 (output)/TCLKA (input) Pin functions in mode 5 PA 7 (input/output)/TP7 (output)/TIOCB2 (input/output)/A 20 (output) PA 6 (input/output)/TP6 (output)/TIOCA2 (input/output)/A 21 (output) PA 5 (input/output)/TP5 (output)/TIOCB1 (input/output)/A 22 (output) PA 4 (input/output)/TP4 (output)/TIOCA1 (input/output)/A 23 (output) PA 3 (input/output)/TP3 (output)/TIOCB0 (input/output)/TCLKD (input) PA 2 (input/output)/TP2 (output)/TIOCA0 (input/output)/TCLKC (input) PA 1 (input/output)/TP1 (output)/TEND1 (output)/TCLKB (input) PA 0 (input/output)/TP0 (output)/TEND0 (output)/TCLKA (input) Figure 8.10 Port A Pin Configuration Rev. 2.0, 06/04, page 293 of 980 8.11.2 Register Descriptions Table 8.18 summarizes the registers of port A. Table 8.18 Port A Registers Initial Value Address* H'EE009 H'FFFD9 Note: * Name Port A data direction register Port A data register Abbreviati R/W on PADDR PADR W R/W Modes 1, 2, 5, and 7 H'00 H'00 Modes 3, 4 H'80 H'00 Lower 20 bits of the address in advanced mode. Port A Data Direction Register (PADDR): PADDR is an 8-bit write-only register that can select input or output for each pin in port A. When pins are used for TPC output, the corresponding PADDR bits must also be set. Bit 7 6 0 W 0 W 5 0 W 0 W 4 0 W 0 W 3 0 W 0 W 2 0 W 0 W 1 0 W 0 W 0 0 W 0 W PA 7 DDR PA 6 DDR PA 5 DDR PA 4 DDR PA 3 DDR PA 2 DDR PA 1 DDR PA 0 DDR Modes Initial value 1 3, 4 Read/Write -- Modes Initial value 0 1, 2, 5, and 7 Read/Write W Port A data direction 7 to 0 These bits select input or output for port A pins The pin functions that can be selected for pins PA7 to PA4 differ between modes 1, 2, and 7, and modes 3 to 5. For the method of selecting the pin functions, see tables 8.19 and 8.20. The pin functions that can be selected for pins PA3 to PA0 are the same in modes 1 to 5, 7. For the method of selecting the pin functions, see table 8.21. When port A functions as an input/output port, a pin in port A becomes an output port if the corresponding PADDR bit is set to 1, and an input port if this bit is cleared to 0. In modes 3 and 4, PA7DDR is fixed at 1 and PA7 functions as the A20 address output pin. PADDR is a write-only register. Its value cannot be read. All bits return 1 when read. PADDR is initialized to H'00 by a reset and in hardware standby mode in modes 1, 2, 5, and 7. It is initialized to H'80 by a reset and in hardware standby mode in modes 3 and 4. In software Rev. 2.0, 06/04, page 294 of 980 standby mode it retains its previous setting. Therefore, if a transition is made to software standby mode while port A is functioning as an input/output port and a PADDR bit is set to 1, the corresponding pin maintains its output state. Port A Data Register (PADR): PADR is an 8-bit readable/writable register that stores output data for port A. When port A functions as an output port, the value of this register is output. When a bit in PADDR is set to 1, if port A is read the value of the corresponding PADR bit is returned. When a bit in PADDR is cleared to 0, if port A is read the corresponding pin logic level is read. Bit Initial value Read/Write 7 PA 0 R/W 7 6 PA 0 R/W 6 5 PA 0 R/W 5 4 PA 0 R/W 4 3 PA 0 R/W 3 2 PA 0 R/W 2 1 PA 0 R/W 1 0 PA 0 R/W 0 Port A data 7 to 0 These bits store data for port A pins PADR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Table 8.19 Port A Pin Functions (Modes 1, 2, 7) Pin PA7/TP7/ TIOCB2 Pin Functions and Selection Method Bit PWM2 in TMDR, bits IOB2 to IOB0 in TIOR2, bit NDER7 in NDERA, and bit PA7DDR select the pin function as follows. 16-bit timer channel 2 settings PA7DDR NDER7 Pin function (1) in table below -- -- TIOCB2 output 0 -- PA7 input (2) in table below 1 0 PA7 output TIOCB2 input* Note: * TIOCB2 input when IOB2 = 1 and PWM2 = 0. 16-bit timer channel 2 settings IOB2 IOB1 IOB0 0 0 (2) 0 0 1 1 -- (1) (2) 1 -- -- 1 1 TP7 output Rev. 2.0, 06/04, page 295 of 980 Pin PA6/TP6/ TIOCA2 Pin Functions and Selection Method Bit PWM2 in TMDR, bits IOA2 to IOA0 in TIOR2, bit NDER6 in NDERA, and bit PA6DDR select the pin function as follows. 16-bit timer channel 2 settings PA6DDR NDER6 Pin function (1) in table below -- -- TIOCA2 output 0 -- PA6 input (2) in table below 1 0 PA6 output TIOCA2 input* 1 1 TP6 output Note: * TIOCA2 input when IOA2 = 1. 16-bit timer channel 2 settings PWM2 IOA2 IOA1 IOA0 PA5/TP5/ TIOCB1 0 0 0 0 1 1 -- (2) (1) 0 1 -- -- (2) (1) 1 -- -- -- Bit PWM1 in TMDR, bits IOB2 to IOB0 in TIOR1, bit NDER5 in NDERA, and bit PA5DDR select the pin function as follows. 16-bit timer channel 1 settings PA5DDR NDER5 Pin function (1) in table below -- -- TIOCB1 output 0 -- PA5 input (2) in table below 1 0 PA5 output TIOCB1 input* 1 1 TP5 output Note: * TIOCB1 input when IOB2 = 1 and PWM1 = 0. 16-bit timer channel 1 settings IOB2 IOB1 IOB0 0 0 (2) 0 0 1 1 -- (1) (2) 1 -- -- Rev. 2.0, 06/04, page 296 of 980 Pin PA4/TP4/ TIOCA1 Pin Functions and Selection Method Bit PWM1 in TMDR, bits IOA2 to IOA0 in TIOR1, bit NDER4 in NDERA, and bit PA4DDR select the pin function as follows. 16-bit timer channel 1 settings PA4DDR NDER4 Pin function (1) in table below -- -- TIOCA1 output 0 -- PA4 input (2) in table below 1 0 PA4 output TIOCA1 input* 1 1 TP4 output Note: * TIOCA1 input when IOA2 = 1. 16-bit timer channel 1 settings PWM1 IOA2 IOA1 IOA0 0 0 0 0 1 1 -- (2) (1) 0 1 -- -- (2) (1) 1 -- -- -- Rev. 2.0, 06/04, page 297 of 980 Table 8.20 Port A Pin Functions (Modes 3 to 5) Pin PA7/TP7/ TIOCB2/ A20 Pin Functions and Selection Method Modes 3 and 4: Always used as A20 output. Pin function A20 output Mode 5: Bit PWM2 in TMDR, bits IOB2 to IOB0 in TIOR2, bit NDER7 in NDERA, bit A20E in BRCR, and bit PA7DDR select the pin function as follows. A20E 16-bit timer channel 2 settings PA7DDR NDER7 Pin function 1 0 (1) in table below -- -- TIOCB2 output 0 -- PA7 input (2) in table below 1 0 PA7 output TIOCB2 input* 1 1 TP7 output -- -- -- A20 output Note: * TIOCB2 input when IOB2 = 1 and PWM2 = 0. 16-bit timer channel 2 settings IOB2 IOB1 IOB0 PA6/TP6/ TIOCA2/A21 0 0 (2) 0 0 1 1 -- (1) (2) 1 -- -- Bit PWM2 in TMDR, bits IOA2 to IOA0 in TIOR2, bit NDER6 in NDERA, bit A21E in BRCR, and bit PA6DDR select the pin function as follows. A21E 16-bit timer channel 2 settings PA6DDR NDER6 Pin function 1 0 (1) in table below -- -- TIOCA2 output 0 -- PA6 input (2) in table below 1 0 PA6 output TIOCA2 input* 1 1 TP6 output -- -- -- A21 output Note: * TIOCA2 input when IOA2 = 1. 16-bit timer channel 2 settings PWM2 IOA2 IOA1 IOA0 0 0 0 0 1 1 -- (2) (1) 0 1 -- -- (2) (1) 1 -- -- -- Rev. 2.0, 06/04, page 298 of 980 Pin PA5/TP5/ TIOCB1/A22 Pin Functions and Selection Method Bit PWM1 in TMDR, bits IOB2 to IOB0 in TIOR1, bit NDER5 in NDERA, bit A22E in BRCR, and bit PA5DDR select the pin function as follows. A22E 16-bit timer channel 1 settings PA5DDR NDER5 Pin function (1) in table below -- -- TIOCB1 output 0 -- PA5 input 1 (2) in table below 1 0 PA5 output TIOCB1 input* Note: * TIOCB1 input when IOB2 = 1 and PWM1 = 0. 16-bit timer channel 1 settings IOB2 IOB1 IOB0 0 0 (2) 0 0 1 1 -- (1) (2) 1 -- -- 1 1 TP5 output 0 -- -- -- A22 output PA4/TP4/ TIOCA1/A23 Bit PWM1 in TMDR, bits IOA2 to IOA0 in TIOR1, bit NDER4 in NDERA, bit A23E in BRCR, and bit PA4DDR select the pin function as follows. A23E 16-bit timer channel 1 settings PA4DDR NDER4 Pin function (1) in table below -- -- TIOCA1 output 0 -- PA4 input 1 (2) in table below 1 0 PA4 output TIOCA1 input* Note: * TIOCA1 input when IOA2 = 1. 16-bit timer channel 1 settings PWM1 IOA2 IOA1 IOA0 0 0 0 0 1 1 -- (2) (1) 0 1 -- -- (2) (1) 1 -- -- -- 1 1 TP4 output 0 -- -- -- A23 output Rev. 2.0, 06/04, page 299 of 980 Table 8.21 Port A Pin Functions (Modes 1 to 5, 7) Pin PA3/TP3/ TIOCB0/ TCLKD Pin Functions and Selection Method Bit PWM0 in TMDR, bits IOB2 to IOB0 in TIOR0, bits TPSC2 to TPSC0 in 16TCR2 to 16TCR0 of the 16-bit timer, bits CKS2 to CKS0 in 8TCR2 of the 8-bit timer, bit NDER3 in NDERA, and bit PA3DDR select the pin function as follows. 16-bit timer channel 0 settings PA3DDR NDER3 Pin function (1) in table below -- -- TIOCB0 output 0 -- PA3 input (2) in table below 1 0 PA3 output TIOCB0 input*1 TCLKD input* Notes: *1 TIOCB0 input when IOB2 = 1 and PWM0 = 0. *2 TCLKD input when TPSC2 = TPSC1 = TPSC0 = 1 in any of 16TCR2 to 16TCR0, or bits CKS2 to CKS0 in 8TCR2 are as shown in (3) in the table below. 16-bit timer channel 0 settings IOB2 IOB1 IOB0 0 0 (2) 0 0 1 1 -- (1) (2) 1 -- -- 2 1 1 TP3 output 8-bit timer channel 2 settings CKS2 CKS1 CKS0 0 -- -- (4) 1 0 0 1 (3) 1 -- Rev. 2.0, 06/04, page 300 of 980 Pin PA2/TP2/ TIOCA0/ TCLKC Pin Functions and Selection Method Bit PWM0 in TMDR, bits IOA2 to IOA0 in TIOR0, bits TPSC2 to TPSC0 in 16TCR2 to 16TCR0 of the 16-bit timer, bits CKS2 to CKS0 in 8TCR0 of the 8-bit timer, bit NDER2 in NDERA, and bit PA2DDR select the pin function as follows. 16-bit timer channel 0 settings PA2DDR NDER2 Pin function (1) in table below -- -- TIOCA0 output 0 -- PA2 input (2) in table below 1 0 PA2 output TIOCA0 input*1 TCLKC input* Notes: *1 TIOCA0 input when IOA2 = 1. *2 TCLKC input when TPSC2 = TPSC1 = 1 and TPSC0 = 0 in any of 16TCR2 to 16TCR0, or bits CKS2 to CKS0 in 8TCR0 are as shown in (3) in the table below. 16-bit timer channel 0 settings PWM0 IOA2 IOA1 IOA0 0 0 0 0 1 1 -- (2) (1) 0 1 -- -- (2) (1) 1 -- -- -- 2 1 1 TP2 output 8-bit timer channel 0 settings CKS2 CKS1 CKS0 0 -- -- (4) 1 0 0 1 (3) 1 -- Rev. 2.0, 06/04, page 301 of 980 Pin PA1/TP1/ TCLKB/ TEND1 Pin Functions and Selection Method Bit MDF in TMDR, bits TPSC2 to TPSC0 in 16TCR2 to 16TCR0 of the 16-bit timer, bits CKS2 to CKS0 in 8TCR3 of the 8-bit timer, bit NDER1 in NDERA, and bit PA1DDR select the pin function as follows. PA1DDR NDER1 Pin function 0 -- PA1 input 1 0 PA1 output TCLKB output*1 TEND1 output*2 Notes: *1 TCLKB input when MDF = 1 in TMDR, or TPSC2 = 1, TPSC1 = 0, and TPSC0 = 1 in any of 16TCR2 to 16TCR0, or bits CKS2 to CKS0 in 8TCR3 are as shown in (1) in the table below. *2 When an external request is specified as a DMAC activation source, TEND1 output regardless of bits PA1DDR and NDER1. 8-bit timer channel 3 settings CKS2 CKS1 CKS0 0 -- -- 0 0 1 (2) 1 1 -- (1) 1 1 TP1 output PA0/TP0/ TCLKA/ TEND0 Bit MDF in TMDR, bits TPSC2 to TPSC0 in 16TCR2 to 16TCR0 of the 16-bit timer, bits CKS2 to CKS0 in 8TCR1 of the 8-bit timer, bit NDER0 in NDERA, and bit PA0DDR select the pin function as follows. PA0DDR NDER0 Pin function 0 -- PA0 input 0 PA0 output TCLKA output*1 TEND0 output*2 Notes: *1 TCLKA input when MDF = 1 in TMDR, or TPSC2 = 1, TPSC1 = 0 and TPSC0 = 0 in any of 16TCR2 to 16TCR0, or bits CKS2 to CKS0 in 8TCR0 are as shown in (1) in the table below. *2 When an external request is specified as a DMAC activation source, TEND0 output regardless of bits PA0DDR and NDER0. 8-bit timer channel 1 settings CKS2 CKS1 CKS0 0 -- -- 0 0 1 (2) 1 1 -- (1) 1 1 TP0 output Rev. 2.0, 06/04, page 302 of 980 8.12 8.12.1 Port B Overview Port B is an 8-bit input/output port that is also used for output (TP15 to TP8) from the programmable timing pattern controller (TPC), input/output (TMIO3, TMO2, TMIO1, TMO0) by the 8-bit timer, CS7 to CS4 output, input (DREQ1, DREQ0) to the DMA controller (DMAC), input and output (TxD2, RxD2, SCK2) by serial communication interface channel 2 (SCI2), and output (UCAS, LCAS) by the DRAM interface. See table 8.23 to 8.24 for the selection of pin functions. A reset or hardware standby transition leaves port B as an input port. For output of CS7 to CS4 in modes 1 to 5, see section 6.3.4, Chip Select Signals. Pins not assigned to any of these functions are available for generic input/output. Figure 8.11 shows the pin configuration of port B. When DRAM is connected to areas 2, 3, 4, and 5, the CS4 and CS5 output pins become RAS output pins for these areas. For details see section 6.5, DRAM Interface. Pins in port B can drive one TTL load and a 30-pF capacitive load. They can also drive darlington transistor pair. Rev. 2.0, 06/04, page 303 of 980 Port B pins PB7/TP15 /RxD2 PB6/TP14 /TxD2 PB5/TP13 /SCK2/LCAS PB4/TP12 /UCAS Port B PB3/TP11 /TMIO3/DREQ1/CS4 PB2/TP10 /TMO2/CS5 PB1/TP9 /TMIO1/DREQ0/CS6 PB0/TP8 /TMO0/CS7 Pin functions in modes 1 to 5 PB7 (input/output)/TP15 (output) /RxD2 (input) PB6 (input/output)/TP14 (output) /TxD2 (output) PB5 (input/output)/TP13 (output) /SCK2 (input/output) /LCAS (output) PB4 (input/output)/TP12 (output) /UCAS (output) PB3 (input/output)/TP11 (output) /TMIO3 (input/output) /DREQ1 (input) CS4 (output) PB2 (input/output)/TP10 (output) /TMO2 (output) /CS5 (output) PB1 (input/output)/TP9 (output) /TMIO1 (input/output) /DREQ0 (input) /CS6 (output) PB0 (input/output)/TP8 (output) /TMO0 (output) /CS7 (output) Pin functions in mode 7 PB7 (input/output)/TP15 (output) /RxD2 (input) PB6 (input/output)/TP14 (output) /TxD2 (output) PB5 (input/output)/TP13 (output) /SCK2 (input/output) PB4 (input/output)/TP12 (output) PB3 (input/output)/TP11 (output) /TMIO3 (input/output) /DREQ1 (input) PB2 (input/output)/TP10 (output) /TMO2 (output) PB1 (input/output)/TP9 (output) /TMIO1 (input/output) /DREQ0 (input) PB0 (input/output)/TP8 (output) /TMO0 (output) Figure 8.11 Port B Pin Configuration Rev. 2.0, 06/04, page 304 of 980 8.12.2 Register Descriptions Table 8.22 summarizes the registers of port B. Table 8.22 Port B Registers Address* H'EE00A H'FFFDA Name Port B data direction register Port B data register Abbreviation PBDDR PBDR R/W W R/W Initial Value H'00 H'00 Note: * Lower 20 bits of the address in advanced mode. Port B Data Direction Register (PBDDR): PBDDR is an 8-bit write-only register that can select input or output for each pin in port B. When pins are used for TPC output, the corresponding PBDDR bits must also be set. Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W PB7 DDR PB6 DDR PB5 DDR PB4 DDR PB3 DDR PB2 DDR PB1 DDR PB0 DDR Port B data direction 7 to 0 These bits select input or output for port B pins The pin functions that can be selected for port B differ between modes 1 to 5, and mode 7. For the method of selecting the pin functions, see tables 8.23 and 8.24. When port B functions as an input/output port, a pin in port B becomes an output port if the corresponding PBDDR bit is set to 1, and an input port if this bit is cleared to 0. PBDDR is a write-only register. Its value cannot be read. All bits return 1 when read. PBDDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Therefore, if a transition is made to software standby mode while port B is functioning as an input/output port and a PBDDR bit is set to 1, the corresponding pin maintains its output state. Rev. 2.0, 06/04, page 305 of 980 Port B Data Register (PBDR): PBDR is an 8-bit readable/writable register that stores output data for pins port B. When port B functions as an output port, the value of this register is output. When a bit in PBDDR is set to 1, if port B is read the value of the corresponding PBDR bit is returned. When a bit in PBDDR is cleared to 0, if port B is read the corresponding pin logic level is read. Bit Initial value Read/Write 7 PB 7 0 R/W 6 PB 6 0 R/W 5 PB 5 0 R/W 4 PB 4 0 R/W 3 PB 3 0 R/W 2 PB 2 0 R/W 1 PB 1 0 R/W 0 PB 0 0 R/W Port B data 7 to 0 These bits store data for port B pins PBDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Rev. 2.0, 06/04, page 306 of 980 Table 8.23 Port B Pin Functions (Modes 1 to 5) Pin PB7/TP15/ RxD2 Pin Functions and Selection Method Bit RE in SCR of SCI2, bit SMIF in SCMR, bit NDER15 in NDERB, and bit PB7DDR select the pin function as follows. SMIF RE PB7DDR NDER15 Pin function PB6/TP14/ TxD2 0 -- PB7 input 0 1 0 PB7 output 1 1 TP15 output 0 1 -- -- RxD2 input 1 -- -- -- RxD2 input Bit TE in SCR of SCI2, bit SMIF in SCMR, bit NDER14 in NDERB, and bit PB6DDR select the pin function as follows. SMIF TE PB6DDR NDER14 Pin function 0 -- PB6 input 0 1 0 PB6 output 1 1 TP14 output 0 1 -- -- TxD2 output 1 -- -- -- TxD2 output* Note: * Functions as the TxD2 output pin, but there are two states: one in which the pin is driven, and another in which the pin is at high-impedance. PB5/TP13/ Bit C/A in SMR of SCI2, bits CKE0 and CKE1 in SCR, bit NDER13 in NDERB, and bit PB5DDR select the pin SCK2/LCAS function as follows. CKE1 C/A CKE0 PB5DDR NDER13 Pin function 0 -- PB5 input 0 1 0 PB5 output 1 1 TP13 output 0 1 -- -- SCK2 output 0 1 -- -- -- SCK2 output 1 -- -- -- -- SCK2 input LCAS output* Note: * LCAS output depending on bits DRAS2 to DRAS0 in DRCRA and bit CSEL in DRCRB, and regardless of bits C/A, CKE0 and CKE1, NDER13, and PB5DDR. For details, see section 6, Bus Controller. PB4/TP12/ UCAS Bit NDER12 in NDERB and bit PB4DDR select the pin function as follows. PB4DDR NDER12 Pin function 0 -- PB4 input 1 0 PB4 output UCAS output* Note: * UCAS output depending on bits DRAS2 to DRAS0 in DRCRA and bit CSEL in DRCRB, and regardless of bits NDER12 and PB4DDR. For details, see section 6, Bus Controller. 1 1 TP12 output Rev. 2.0, 06/04, page 307 of 980 Pin Pin Functions and Selection Method The DRAM interface settings by bits DRAS2 to DRAS0 in DRCRA, bits OIS3/2 and OS1/0 in 8TCSR3, bits PB3/TP11/ CCLR1 and CCLR0 in 8TCR3, bit CS4E in CSCR, bit NDER11 in NDERB, and bit PB3DDR select the pin TMIO3/ DREQ1/CS4 function as follows. DRAM interface settings OIS3/2 and OS1/0 CS4E PB3DDR NDER11 Pin function 0 -- PB3 input 0 1 0 PB3 output 1 1 TP11 output (1) in table below All 0 1 -- -- CS4 output Not all 0 -- -- -- TMIO3 output (2) in table below -- -- -- -- CS4 output*3 TMIO3 input*1 DREQ1 input*2 Notes: *1 TMIO3 input when CCLR1 = CCLR0 = 1. *2 When an external request is specified as a DMAC activation source, DREQ1 input regardless of bits OIS3 and OIS2, OS1 and OS0, CCLR1 and CCLR0, CS4E, NDER11, and PB3DDR. *3 CS4 is output as RAS4. DRAM interface settings DRAS2 DRAS1 DRAS0 PB2/TP10/ TMO2/CS5 0 0 1 0 (1) 0 1 1 0 0 1 0 (2) 1 1 1 (1) The DRAM interface settings by bits DRAS2 to DRAS0 in DRCRA, bits OIS3/2 and OS1/0 in 8TCSR2, bit CS5E in CSCR, bit NDER10 in NDERB, and bit PB2DDR select the pin function as follows. DRAM interface settings OIS3/2 and OS1/0 CS5E PB2DDR NDER10 Pin function 0 -- PB2 input 0 1 0 PB2 output 1 1 TP10 output (1) in table below All 0 1 -- -- CS5 output Not all 0 -- -- -- TMIO2 output (2) in table below -- -- -- -- CS5 output* Note: * CS5 is output as RAS5. DRAM interface settings DRAS2 DRAS1 DRAS0 0 0 1 0 0 1 1 0 0 1 0 (1) (2) 1 1 1 (1) Rev. 2.0, 06/04, page 308 of 980 Pin Pin Functions and Selection Method Bits OIS3/2 and OS1/0 in 8TCSR1, bits CCLR1 and CCLR0 in TCR1, bit CS6E in CSCR, bit NDER9 in PB1/TP9/ NDERB, and bit PB1DDR select the pin function as follows. TMIO1/ DREQ0/CS6 OIS3/2 and OS1/0 CS6E PB1DDR NDER9 Pin function 0 -- PB1 input 0 1 0 PB1 output 1 1 TP9 output TMIO1 input*1 DREQ0 input*2 Notes: *1 TMIO1 input when CCLR1 = CCLR0 = 1. *2 When an external request is specified as a DMAC activation source, DREQ0 input regardless of bits OIS3/2 and OS1/0, bits CCLR1/0, bit CS6E, bit NDER9, and bit PB1DDR. PB0/TP8/ TMO0/CS7 Bits OIS3/2 and OS1/0 in 8TCSR0, bit CS7E in CSCR, bit NDER8 in NDERB, and bit PB0DDR select the pin function as follows. OIS3/2 and OS1/0 CS7E PB0DDR NDER8 Pin function 0 -- PB0 input 0 1 0 PB0 output 1 1 TP8 output All 0 1 -- -- CS7 output Not all 0 -- -- -- TMO0 output All 0 1 -- -- CS6 output Not all 0 -- -- -- TMIO1 output Rev. 2.0, 06/04, page 309 of 980 Table 8.24 Port B Pin Functions (Mode 7) Pin PB7/TP15/ RxD2 Pin Functions and Selection Method Bit RE in SCR of SCI2, bit SMIF in SCMR, bit NDER15 in NDERB, and bit PB7DDR select the pin function as follows. SMIF RE PB7DDR NDER15 Pin function PB6/TP14/ TxD2 0 -- PB7 input 0 1 0 PB7 output 1 1 TP15 output 0 1 -- -- RxD2 input 1 -- -- -- RxD2 input Bit TE in SCR of SCI2, bit SMIF in SCMR, bit NDER14 in NDERB, and bit PB6DDR select the pin function as follows. SMIF TE PB6DDR NDER14 Pin function 0 -- PB6 input 0 1 0 PB6 output 1 1 TP14 output 0 1 -- -- TxD2 output 1 -- -- -- TxD2 output* Note: * Functions as the TxD2 output pin, but there are two states: one in which the pin is driven, and another in which the pin is at high-impedance. PB5/TP13/ SCK2 Bit C/A in SMR of SCI2, bits CKE0 and CKE1 in SCR, bit NDER13 in NDERB, and bit PB5DDR select the pin function as follows. CKE1 C/A CKE0 PB5DDR NDER13 Pin function PB4/TP12 0 -- PB5 input 0 1 0 PB5 output 1 1 TP13 output 0 1 -- -- SCK2 output 0 1 -- -- -- SCK2 output 1 -- -- -- -- SCK2 input Bit NDER12 in NDERB and bit PB4DDR select the pin function as follows. PB4DDR NDER12 Pin function 0 -- PB4 input 1 0 PB4 output 1 1 TP12 output Rev. 2.0, 06/04, page 310 of 980 Pin PB3/TP11/ TMIO3/ DREQ1 Pin Functions and Selection Method Bits OIS3/2 and OS1/0 in 8TCSR3, bits CCLR1 and CCLR0 in 8TCR3, bit NDER11 in NDERB, and bit PB3DDR select the pin function as follows. OIS3/2 and OS1/0 PB3DDR NDER11 Pin function 0 -- PB3 input All 0 1 0 PB3 output 1 1 TP11 output Not all 0 -- -- TMIO3 output TMIO3 input*1 DREQ1 input*2 Notes: *1 TMIO3 input when CCLR1 = CCLR0 = 1. *2 When an external request is specified as a DMAC activation source, DREQ1 input regardless of bits OIS3/2 and OS1/0, bit NDER11, and bit PB3DDR. PB2/TP10/ TMO2 Bits OIS3/2 and OS1/0 in 8TCSR2, bit NDER10 in NDERB, and bit PB2DDR select the pin function as follows. OIS3/2 and OS1/0 PB2DDR NDER10 Pin function PB1/TP9/ TMIO1/ DREQ0 0 -- PB2 input All 0 1 0 PB2 output 1 1 TP10 output Not all 0 -- -- TMO2 output Bits OIS3/2 and OS1/0 in 8TCSR1, bits CCLR1 and CCLR0 in 8TCR0, bit NDER9 in NDERB, and bit PB1DDR select the pin function as follows. OIS3/2 and OS1/0 PB1DDR NDER9 Pin function 0 -- PB1 input All 0 1 0 PB1 output TMIO1 input*1 DREQ0 input*2 Notes: *1 TMIO1 input when CCLR1 = CCLR0 = 1. *2 When an external request is specified as a DMAC activation source, DREQ0 input regardless of bits OIS3/2 and OS1/0, bit NDER9, and bit PB1DDR. 1 1 TP9 output Not all 0 -- -- TMIO1 output PB0/TP8/ TMO0 Bits OIS3/2 and OS1/0 in 8TCSR0, bit NDER8 in NDERB, and bit PB0DDR select the pin function as follows. OIS3/2 and OS1/0 PB0DDR NDER8 Pin function 0 -- PB0 input All 0 1 0 PB0 output 1 1 TP8 output Not all 0 -- -- TMO0 output Rev. 2.0, 06/04, page 311 of 980 Rev. 2.0, 06/04, page 312 of 980 Section 9 16-Bit Timer 9.1 Overview The H8/3029 has built-in 16-bit timer module with three 16-bit counter channels. 9.1.1 Features 16-bit timer features are listed below. * Capability to process up to 6 pulse outputs or 6 pulse inputs * Six general registers (GRs, two per channel) with independently-assignable output compare or input capture functions * Selection of eight counter clock sources for each channel: Internal clocks: , /2, /4, /8 External clocks: TCLKA, TCLKB, TCLKC, TCLKD * Five operating modes selectable in all channels: Waveform output by compare match Selection of 0 output, 1 output, or toggle output (only 0 or 1 output in channel 2) Input capture function Rising edge, falling edge, or both edges (selectable) Counter clearing function Counters can be cleared by compare match or input capture. Synchronization Two or more timer counters (16TCNTs) can be preset simultaneously, or cleared simultaneously by compare match or input capture. Counter synchronization enables synchronous register input and output. PWM mode PWM output can be provided with an arbitrary duty cycle. With synchronization, up to three-phase PWM output is possible. * Phase counting mode selectable in channel 2 Two-phase encoder output can be counted automatically. * High-speed access via internal 16-bit bus The 16TCNTs and GRs can be accessed at high speed via a 16-bit bus. * Any initial timer output value can be set * Nine interrupt sources Each channel has two compare match/input capture interrupts and an overflow interrupt. All interrupts can be requested independently. Rev. 2.0, 06/04, page 313 of 980 * Output triggering of programmable timing pattern controller (TPC) Compare match/input capture signals from channels 0 to 2 can be used as TPC output triggers. Table 9.1 summarizes the 16-bit timer functions. Table 9.1 Item Clock sources 16-bit timer Functions Channel 0 Channel 1 Channel 2 Internal clocks: , /2, /4, /8 External clocks: TCLKA, TCLKB, TCLKC, TCLKD, selectable independently General registers (output compare/input capture registers) Input/output pins Counter clearing function GRA0, GRB0 GRA1, GRB1 GRA2, GRB2 TIOCA0, TIOCB0 GRA0/GRB0 compare match or input capture TIOCA1, TIOCB1 GRA1/GRB1 compare match or input capture Available Available Available Available Available Available Available Not available Three sources TIOCA2, TIOCB2 GRA2/GRB2 compare match or input capture Available Available Available Not available Available Available Available Available Three sources Compare match/input capture A2 Compare match/input capture B2 Overflow Initial output value setting function Available Compare match output 0 1 Toggle Input capture function Synchronization PWM mode Phase counting mode Interrupt sources Available Available Available Available Available Available Not available Three sources * * * * Compare match/input capture A0 * Compare match/input capture B0 * Overflow * Compare match/input capture A1 * Compare match/input capture B1 * Overflow Rev. 2.0, 06/04, page 314 of 980 9.1.2 Block Diagrams 16-bit timer Block Diagram (Overall): Figure 9.1 is a block diagram of the 16-bit timer. TCLKA to TCLKD , /2, /4, /8 Clock selector Control logic IMIA0 to IMIA2 IMIB0 to IMIB2 OVI0 to OVI2 TIOCA0 to TIOCA2 TIOCB0 to TIOCB2 TSTR 16-bit timer channel 2 16-bit timer channel 1 16-bit timer channel 0 TSNR TOLR TISRA TISRB TISRC Module data bus Legend: TSTR: Timer start register (8 bits) TSNR: Timer synchro register (8 bits) TMDR: Timer mode register (8 bits) TOLR: Timer output level setting register (8 bits) TISRA: Timer interrupt status register A (8 bits) TISRB: Timer interrupt status register B (8 bits) TISRC: Timer interrupt status register C (8 bits) Figure 9.1 16-bit timer Block Diagram (Overall) Rev. 2.0, 06/04, page 315 of 980 Bus interface TMDR Internal data bus Block Diagram of Channels 0 and 1: 16-bit timer channels 0 and 1 are functionally identical. Both have the structure shown in figure 9.2. TCLKA to TCLKD , /2, /4, /8 Clock selector Control logic Comparator TIOCA0 TIOCB0 IMIA0 IMIB0 OVI0 16TCNT 16TCR Module data bus Legend: 16TCNT: GRA, GRB: TCR: TIOR: Timer counter (16 bits) General registers A and B (input capture/output compare registers) (16 bits x 2) Timer control register (8 bits) Timer I/O control register (8 bits) Figure 9.2 Block Diagram of Channels 0 and 1 Rev. 2.0, 06/04, page 316 of 980 TIOR GRA GRB Block Diagram of Channel 2: Figure 9.3 is a block diagram of channel 2 TCLKA to TCLKD , /2, /4, /8 Clock selector Control logic Comparator TIOCA2 TIOCB2 IMIA2 IMIB2 OVI2 16TCNT2 16TCR2 Module data bus Legend: Timer counter 2 (16 bits) 16TCNT2: GRA2, GRB2: General registers A2 and B2 (input capture/output compare registers) (16 bits x 2) Timer control register 2 (8 bits) TCR2: Timer I/O control register 2 (8 bits) TIOR2: Figure 9.3 Block Diagram of Channel 2 Rev. 2.0, 06/04, page 317 of 980 TIOR2 GRA2 GRB2 9.1.3 Pin Configuration Table 9.2 summarizes the 16-bit timer pins. Table 9.2 16-bit timer Pins Abbreviation TCLKA Input/ Output Input Function External clock A input pin (phase-A input pin in phase counting mode) External clock B input pin (phase-B input pin in phase counting mode) External clock C input pin External clock D input pin GRA0 output compare or input capture pin PWM output pin in PWM mode GRB0 output compare or input capture pin GRA1 output compare or input capture pin PWM output pin in PWM mode GRB1 output compare or input capture pin GRA2 output compare or input capture pin PWM output pin in PWM mode GRB2 output compare or input capture pin Channel Name Common Clock input A Clock input B TCLKB Input Clock input C Clock input D 0 TCLKC TCLKD Input Input Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input capture/output TIOCA0 compare A0 Input capture/output TIOCB0 compare B0 1 Input capture/output TIOCA1 compare A1 Input capture/output TIOCB1 compare B1 2 Input capture/output TIOCA2 compare A2 Input capture/output TIOCB2 compare B2 Rev. 2.0, 06/04, page 318 of 980 9.1.4 Register Configuration Table 9.3 summarizes the 16-bit timer registers. Table 9.3 Channel Common 16-bit timer Registers Address* H'FFF60 H'FFF61 H'FFF62 H'FFF63 H'FFF64 H'FFF65 H'FFF66 1 Name Timer start register Timer synchro register Timer mode register Timer output level setting register Timer interrupt status register A Timer interrupt status register B Timer interrupt status register C Timer control register 0 Timer I/O control register 0 Timer counter 0H Timer counter 0L General register A0H General register A0L General register B0H General register B0L Timer control register 1 Timer I/O control register 1 Timer counter 1H Timer counter 1L General register A1H General register A1L General register B1H General register B1L Abbreviation TSTR TSNC TMDR TOLR TISRA TISRB TISRC 16TCR0 TIOR0 R/W R/W R/W R/W W R/(W)* R/(W)* R/(W)* R/W R/W 2 2 2 Initial Value H'F8 H'F8 H'98 H'C0 H'88 H'88 H'88 H'80 H'88 H'00 H'00 H'FF H'FF H'FF H'FF H'80 H'88 H'00 H'00 H'FF H'FF H'FF H'FF 0 H'FFF68 H'FFF69 H'FFF6A H'FFF6B H'FFF6C H'FFF6D H'FFF6E H'FFF6F 16TCNT0H R/W 16TCNT0L R/W GRA0H GRA0L GRB0H GRB0L 16TCR1 TIOR1 R/W R/W R/W R/W R/W R/W 1 H'FFF70 H'FFF71 H'FFF72 H'FFF73 H'FFF74 H'FFF75 H'FFF76 H'FFF77 16TCNT1H R/W 16TCNT1L R/W GRA1H GRA1L GRB1H GRB1L R/W R/W R/W R/W Rev. 2.0, 06/04, page 319 of 980 Channel 2 Address* H'FFF78 H'FFF79 H'FFF7A H'FFF7B H'FFF7C H'FFF7D H'FFF7E H'FFF7F 1 Name Timer control register 2 Timer I/O control register 2 Timer counter 2H Timer counter 2L General register A2H General register A2L General register B2H General register B2L Abbreviation 16TCR2 TIOR2 R/W R/W R/W Initial Value H'80 H'88 H'00 H'00 H'FF H'FF H'FF H'FF 16TCNT2H R/W 16TCNT2L R/W GRA2H GRA2L GRB2H GRB2L R/W R/W R/W R/W Notes: *1 The lower 20 bits of the address in advanced mode are indicated. *2 Only 0 can be written in bits 3 to 0, to clear the flags. 9.2 9.2.1 Register Descriptions Timer Start Register (TSTR) TSTR is an 8-bit readable/writable register that starts and stops the timer counter (16TCNT) in channels 0 to 2. Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- Reserved bits 4 -- 1 -- 3 -- 1 -- 2 STR2 0 R/W 1 STR1 0 R/W 0 STR0 0 R/W Counter start 2 to 0 These bits start and stop 16TCNT2 to 16TCNT0 TSTR is initialized to H'F8 by a reset and in standby mode. Bits 7 to 3--Reserved: These bits cannot be modified and are always read as 1. Bit 2--Counter Start 2 (STR2): Starts and stops timer counter 2 (16TCNT2). Bit 2 STR2 0 1 Description 16TCNT2 is halted 16TCNT2 is counting (Initial value) Rev. 2.0, 06/04, page 320 of 980 Bit 1--Counter Start 1 (STR1): Starts and stops timer counter 1 (16TCNT1). Bit 1 STR1 0 1 Description 16TCNT1 is halted 16TCNT1 is counting (Initial value) Bit 0--Counter Start 0 (STR0): Starts and stops timer counter 0 (16TCNT0). Bit 0 STR0 0 1 Description 16TCNT0 is halted 16TCNT0 is counting (Initial value) 9.2.2 Timer Synchro Register (TSNC) TSNC is an 8-bit readable/writable register that selects whether channels 0 to 2 operate independently or synchronously. Channels are synchronized by setting the corresponding bits to 1. Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- Reserved bits 4 -- 1 -- 3 -- 1 -- 2 SYNC2 0 R/W 1 SYNC1 0 R/W 0 SYNC0 0 R/W Timer sync 2 to 0 These bits synchronize channels 2 to 0 TSNC is initialized to H'F8 by a reset and in standby mode. Bits 7 to 3--Reserved: These bits cannot be modified and are always read as 1. Bit 2--Timer Sync 2 (SYNC2): Selects whether channel 2 operates independently or synchronously. Bit 2 SYNC2 0 1 Description Channel 2's timer counter (16TCNT2) operates independently 16TCNT2 is preset and cleared independently of other channels Channel 2 operates synchronously 16TCNT2 can be synchronously preset and cleared (Initial value) Rev. 2.0, 06/04, page 321 of 980 Bit 1--Timer Sync 1 (SYNC1): Selects whether channel 1 operates independently or synchronously. Bit 1 SYNC1 0 1 Description Channel 1's timer counter (16TCNT1) operates independently 16TCNT1 is preset and cleared independently of other channels Channel 1 operates synchronously 16TCNT1 can be synchronously preset and cleared (Initial value) Bit 0--Timer Sync 0 (SYNC0): Selects whether channel 0 operates independently or synchronously. Bit 0 SYNC0 0 1 Description Channel 0's timer counter (16TCNT0) operates independently 16TCNT0 is preset and cleared independently of other channels Channel 0 operates synchronously 16TCNT0 can be synchronously preset and cleared (Initial value) 9.2.3 Timer Mode Register (TMDR) TMDR is an 8-bit readable/writable register that selects PWM mode for channels 0 to 2. It also selects phase counting mode and the overflow flag (OVF) setting conditions for channel 2. Bit Initial value Read/Write 7 -- 1 -- 6 MDF 0 R/W 5 FDIR 0 R/W 4 -- 1 -- 3 -- 1 -- 2 PWM2 0 R/W 1 PWM1 0 R/W 0 PWM0 0 R/W Reserved bit PWM mode 2 to 0 These bits select PWM mode for channels 2 to 0 Flag direction Selects the setting condition for the overflow flag (OVF) in TISRC Phase counting mode flag Selects phase counting mode for channel 2 Reserved bit TMDR is initialized to H'98 by a reset and in standby mode. Rev. 2.0, 06/04, page 322 of 980 Bit 7--Reserved: This bit cannot be modified and is always read as 1. Bit 6--Phase Counting Mode Flag (MDF): Selects whether channel 2 operates normally or in phase counting mode. Bit 6 MDF 0 1 Description Channel 2 operates normally Channel 2 operates in phase counting mode (Initial value) When MDF is set to 1 to select phase counting mode, 16TCNT2 operates as an up/down-counter and pins TCLKA and TCLKB become counter clock input pins. 16TCNT2 counts both rising and falling edges of TCLKA and TCLKB, and counts up or down as follows. Counting Direction TCLKA pin TCLKB pin Low Down-Counting High High Low Up-Counting Low High High Low In phase counting mode, external clock edge selection by bits CKEG1 and CKEG0 in 16TCR2 and counter clock selection by bits TPSC2 to TPSC0 are invalid, and the above phase counting mode operations take precedence. The counter clearing condition selected by the CCLR1 and CCLR0 bits in 16TCR2 and the compare match/input capture settings and interrupt functions of TIOR2, TISRA, TISRB, TISRC remain effective in phase counting mode. Bit 5--Flag Direction (FDIR): Designates the setting condition for the OVF flag in TISRC. The FDIR designation is valid in all modes in channel 2. Bit 5 FDIR 0 1 Description OVF is set to 1 in TISRC when 16TCNT2 overflows or underflows OVF is set to 1 in TISRC when 16TCNT2 overflows (Initial value) Bits 4 and 3--Reserved: These bits cannot be modified and are always read as 1. Rev. 2.0, 06/04, page 323 of 980 Bit 2--PWM Mode 2 (PWM2): Selects whether channel 2 operates normally or in PWM mode. Bit 2 PWM2 0 1 Description Channel 2 operates normally Channel 2 operates in PWM mode (Initial value) When bit PWM2 is set to 1 to select PWM mode, pin TIOCA2 becomes a PWM output pin. The output goes to 1 at compare match with GRA2, and to 0 at compare match with GRB2. Bit 1--PWM Mode 1 (PWM1): Selects whether channel 1 operates normally or in PWM mode. Bit 1 PWM1 0 1 Description Channel 1 operates normally Channel 1 operates in PWM mode (Initial value) When bit PWM1 is set to 1 to select PWM mode, pin TIOCA1 becomes a PWM output pin. The output goes to 1 at compare match with GRA1, and to 0 at compare match with GRB1. Bit 0--PWM Mode 0 (PWM0): Selects whether channel 0 operates normally or in PWM mode. Bit 0 PWM0 0 1 Description Channel 0 operates normally Channel 0 operates in PWM mode (Initial value) When bit PWM0 is set to 1 to select PWM mode, pin TIOCA0 becomes a PWM output pin. The output goes to 1 at compare match with GRA0, and to 0 at compare match with GRB0. Rev. 2.0, 06/04, page 324 of 980 9.2.4 Timer Interrupt Status Register A (TISRA) TISRA is an 8-bit readable/writable register that indicates GRA compare match or input capture and enables or disables GRA compare match and input capture interrupt requests. Bit 7 -- Initial value Read/Write 1 -- 6 5 4 3 -- 1 -- 2 IMFA2 0 R/(W)* 1 IMFA1 0 R/(W)* 0 IMFA0 0 R/(W)* IMIEA2 IMIEA1 IMIEA0 0 R/W 0 R/W 0 R/W Input capture/compare match flags A2 to A0 Status flags indicating GRA compare match or input capture Reserved bit Input capture/compare match interrupt enable A2 to A0 These bits enable or disable interrupts by the IMFA flags Reserved bit Note: * Only 0 can be written, to clear the flag. TISRA is initialized to H'88 by a reset and in standby mode. Bit 7--Reserved: This bit cannot be modified and is always read as 1. Bit 6--Input Capture/Compare Match Interrupt Enable A2 (IMIEA2): Enables or disables the interrupt requested by the IMFA2 when IMFA2 flag is set to 1. Bit 6 IMIEA2 0 1 Description IMIA2 interrupt requested by IMFA2 flag is disabled IMIA2 interrupt requested by IMFA2 flag is enabled (Initial value) Rev. 2.0, 06/04, page 325 of 980 Bit 5--Input Capture/Compare Match Interrupt Enable A1 (IMIEA1): Enables or disables the interrupt requested by the IMFA1 flag when IMFA1 is set to 1. Bit 5 IMIEA1 0 1 Description IMIA1 interrupt requested by IMFA1 flag is disabled IMIA1 interrupt requested by IMFA1 flag is enabled (Initial value) Bit 4--Input Capture/Compare Match Interrupt Enable A0 (IMIEA0): Enables or disables the interrupt requested by the IMFA0 flag when IMFA0 is set to 1. Bit 4 IMIEA0 0 1 Description IMIA0 interrupt requested by IMFA0 flag is disabled IMIA0 interrupt requested by IMFA0 flag is enabled (Initial value) Bit 3--Reserved: This bit cannot be modified and is always read as 1. Bit 2--Input Capture/Compare Match Flag A2 (IMFA2): This status flag indicates GRA2 compare match or input capture events. Bit 2 IMFA2 0 1 Description [Clearing condition] Read IMFA2 flag when IMFA2 =1, then write 0 in IMFA2 flag [Setting conditions] * * 16TCNT2 = GRA2 when GRA2 functions as an output compare register 16TCNT2 value is transferred to GRA2 by an input capture signal when GRA2 functions as an input capture register (Initial value) Rev. 2.0, 06/04, page 326 of 980 Bit 1--Input Capture/Compare Match Flag A1 (IMFA1): This status flag indicates GRA1 compare match or input capture events. Bit 1 IMFA1 0 1 Description [Clearing condition] Read IMFA1 flag when IMFA1 =1, then write 0 in IMFA1 flag [Setting conditions] * * 16TCNT1 = GRA1 when GRA1 functions as an output compare register 16TCNT1 value is transferred to GRA1 by an input capture signal when GRA1 functions as an input capture register (Initial value) Bit 0--Input Capture/Compare Match Flag A0 (IMFA0): This status flag indicates GRA0 compare match or input capture events. Bit 0 IMFA0 0 1 Description [Clearing condition] Read IMFA0 flag when IMFA0 =1, then write 0 in IMFA0 flag [Setting conditions] * * 16TCNT0 = GRA0 when GRA0 functions as an output compare register 16TCNT0 value is transferred to GRA0 by an input capture signal when GRA0 functions as an input capture register (Initial value) Rev. 2.0, 06/04, page 327 of 980 9.2.5 Timer Interrupt Status Register B (TISRB) TISRB is an 8-bit readable/writable register that indicates GRB compare match or input capture and enables or disables GRB compare match and input capture interrupt requests. Bit 7 -- Initial value Read/Write 1 -- 6 5 4 3 -- 1 -- 2 IMFB2 0 R/(W)* 1 IMFB1 0 R/(W)* 0 IMFB0 0 R/(W)* IMIEB2 IMIEB1 IMIEB0 0 R/W 0 R/W 0 R/W Input capture/compare match flags B2 to B0 Status flags indicating GRB compare match or input capture Reserved bit Input capture/compare match interrupt enable B2 to B0 These bits enable or disable interrupts by the IMFB flags Reserved bit Note: * Only 0 can be written, to clear the flag. TISRB is initialized to H'88 by a reset and in standby mode. Bit 7--Reserved: This bit cannot be modified and is always read as 1. Bit 6--Input Capture/Compare Match Interrupt Enable B2 (IMIEB2): Enables or disables the interrupt requested by the IMFB2 when IMFB2 flag is set to 1. Bit 6 IMIEB2 0 1 Description IMIB2 interrupt requested by IMFB2 flag is disabled IMIB2 interrupt requested by IMFB2 flag is enabled (Initial value) Rev. 2.0, 06/04, page 328 of 980 Bit 5--Input Capture/Compare Match Interrupt Enable B1 (IMIEB1): Enables or disables the interrupt requested by the IMFB1 when IMFB1 flag is set to 1. Bit 5 IMIEB1 0 1 Description IMIB1 interrupt requested by IMFB1 flag is disabled IMIB1 interrupt requested by IMFB1 flag is enabled (Initial value) Bit 4--Input Capture/Compare Match Interrupt Enable B0 (IMIEB0): Enables or disables the interrupt requested by the IMFB0 when IMFB0 flag is set to 1. Bit 4 IMIEB0 0 1 Description IMIB0 interrupt requested by IMFB0 flag is disabled IMIB0 interrupt requested by IMFB0 flag is enabled (Initial value) Bit 3--Reserved: This bit cannot be modified and is always read as 1. Bit 2--Input Capture/Compare Match Flag B2 (IMFB2): This status flag indicates GRB2 compare match or input capture events. Bit 2 IMFB2 0 1 Description [Clearing condition] Read IMFB2 flag when IMFB2 =1, then write 0 in IMFB2 flag [Setting conditions] * * 16TCNT2 = GRB2 when GRB2 functions as an output compare register 16TCNT2 value is transferred to GRB2 by an input capture signal when GRB2 functions as an input capture register (Initial value) Rev. 2.0, 06/04, page 329 of 980 Bit 1--Input Capture/Compare Match Flag B1 (IMFB1): This status flag indicates GRB1 compare match or input capture events. Bit 1 IMFB1 0 1 Description [Clearing condition] Read IMFB1 flag when IMFB1 =1, then write 0 in IMFB1 flag [Setting conditions] * * 16TCNT1 = GRB1 when GRB1 functions as an output compare register 16TCNT1 value is transferred to GRB1 by an input capture signal when GRB1 functions as an input capture register (Initial value) Bit 0--Input Capture/Compare Match Flag B0 (IMFB0): This status flag indicates GRB0 compare match or input capture events. Bit 0 IMFB0 0 1 Description [Clearing condition] Read IMFB0 flag when IMFB0 =1, then write 0 in IMFB0 flag [Setting conditions] * * 16TCNT0 = GRB0 when GRB0 functions as an output compare register 16TCNT0 value is transferred to GRB0 by an input capture signal when GRB0 functions as an input capture register (Initial value) Rev. 2.0, 06/04, page 330 of 980 9.2.6 Timer Interrupt Status Register C (TISRC) TISRC is an 8-bit readable/writable register that indicates 16TCNT overflow or underflow and enables or disables overflow interrupt requests. Bit 7 -- Initial value Read/Write 1 -- 6 OVIE2 0 R/W 5 OVIE1 0 R/W 4 OVIE0 0 R/W 3 -- 1 -- 2 OVF2 0 R/(W)* 1 OVF1 0 R/(W)* 0 OVF0 0 R/(W)* Overflow flags 2 to 0 Status flags indicating interrupts by OVF flags Reserved bit Overflow interrupt enable 2 to 0 These bits enable or disable interrupts by the OVF flags Reserved bit Note: * Only 0 can be written, to clear the flag. TISRC is initialized to H'88 by a reset and in standby mode. Bit 7--Reserved: This bit cannot be modified and is always read as 1. Bit 6--Overflow Interrupt Enable 2 (OVIE2): Enables or disables the interrupt requested by the OVF2 when OVF2 flag is set to 1. Bit 6 OVIE2 0 1 Description OVI2 interrupt requested by OVF2 flag is disabled OVI2 interrupt requested by OVF2 flag is enabled (Initial value) Bit 5--Overflow Interrupt Enable 1 (OVIE1): Enables or disables the interrupt requested by the OVF1 when OVF1 flag is set to 1. Bit 5 OVIE1 0 1 Description OVI1 interrupt requested by OVF1 flag is disabled OVI1 interrupt requested by OVF1 flag is enabled (Initial value) Rev. 2.0, 06/04, page 331 of 980 Bit 4--Overflow Interrupt Enable 0 (OVIE0): Enables or disables the interrupt requested by the OVF0 when OVF0 flag is set to 1. Bit 4 OVIE0 0 1 Description OVI0 interrupt requested by OVF0 flag is disabled OVI0 interrupt requested by OVF0 flag is enabled (Initial value) Bit 3--Reserved: This bit cannot be modified and is always read as 1. Bit 2--Overflow Flag 2 (OVF2): This status flag indicates 16TCNT2 overflow. Bit 2 OVF2 0 1 Description [Clearing condition] Read OVF2 flag when OVF2 =1, then write 0 in OVF2 flag [Setting condition] 16TCNT2 overflowed from H'FFFF to H'0000, or underflowed from H'0000 to H'FFFF Note: 16TCNT underflow occurs when 16TCNT operates as an up/down-counter. Underflow occurs only when channel 2 operates in phase counting mode (MDF = 1 in TMDR). (Initial value) Bit 1--Overflow Flag 1 (OVF1): This status flag indicates 16TCNT1 overflow. Bit 1 OVF1 0 1 Description [Clearing condition] Read OVF1 flag when OVF1 =1, then write 0 in OVF1 flag [Setting condition] 16TCNT1 overflowed from H'FFFF to H'0000 (Initial value) Bit 0--Overflow Flag 0 (OVF0): This status flag indicates 16TCNT0 overflow. Bit 0 OVF0 0 1 Description [Clearing condition] Read OVF0 flag when OVF0 =1, then write 0 in OVF0 flag [Setting condition] 16TCNT0 overflowed from H'FFFF to H'0000 (Initial value) Rev. 2.0, 06/04, page 332 of 980 9.2.7 Timer Counters (16TCNT) 16TCNT is a 16-bit counter. The 16-bit timer has three 16TCNTs, one for each channel. Channel 0 1 2 Abbreviation 16TCNT0 16TCNT1 16TCNT2 Phase counting mode: up/down-counter Other modes: up-counter Function Up-counter Bit Initial value Read/Write 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Each 16TCNT is a 16-bit readable/writable register that counts pulse inputs from a clock source. The clock source is selected by bits TPSC2 to TPSC0 in 16TCR. 16TCNT0 and 16TCNT1 are up-counters. 16TCNT2 is an up/down-counter in phase counting mode and an up-counter in other modes. 16TCNT can be cleared to H'0000 by compare match with GRA or GRB or by input capture to GRA or GRB (counter clearing function). When 16TCNT overflows (changes from H'FFFF to H'0000), the OVF flag is set to 1 in TISRC of the corresponding channel. When 16TCNT underflows (changes from H'0000 to H'FFFF), the OVF flag is set to 1 in TISRC of the corresponding channel. The 16TCNTs are linked to the CPU by an internal 16-bit bus and can be written or read by either word access or byte access. Each 16TCNT is initialized to H'0000 by a reset and in standby mode. Rev. 2.0, 06/04, page 333 of 980 9.2.8 General Registers (GRA, GRB) The general registers are 16-bit registers. The 16-bit timer has 6 general registers, two in each channel. Channel 0 1 2 Abbreviation GRA0, GRB0 GRA1, GRB1 GRA2, GRB2 Function Output compare/input capture register Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W A general register is a 16-bit readable/writable register that can function as either an output compare register or an input capture register. The function is selected by settings in TIOR. When a general register is used as an output compare register, its value is constantly compared with the 16TCNT value. When the two values match (compare match), the IMFA or IMFB flag is set to 1 in TISRA/TISRB. Compare match output can be selected in TIOR. When a general register is used as an input capture register, an external input capture signal are detected and the current 16TCNT value is stored in the general register. The corresponding IMFA or IMFB flag in TISRA/TISRB is set to 1 at the same time. The edges of the input capture signal are selected in TIOR. TIOR settings are ignored in PWM mode. General registers are linked to the CPU by an internal 16-bit bus and can be written or read by either word access or byte access. General registers are set as output compare registers (with no pin output) and initialized to H'FFFF by a reset and in standby mode. Rev. 2.0, 06/04, page 334 of 980 9.2.9 Timer Control Registers (16TCR) 16TCR is an 8-bit register. The 16-bit timer has three 16TCRs, one in each channel. Channel 0 1 2 Abbreviation 16TCR0 16TCR1 16TCR2 Function 16TCR controls the timer counter. The 16TCRs in all channels are functionally identical. When phase counting mode is selected in channel 2, the settings of bits CKEG1 and CKEG0 and TPSC2 to TPSC0 in 16TCR2 are ignored. Bit Initial value Read/Write 7 -- 1 -- 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 CKEG1 0 R/W 3 CKEG0 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W Timer prescaler 2 to 0 These bits select the timer counter clock Clock edge 1/0 These bits select external clock edges Counter clear 1/0 These bits select the counter clear source Reserved bit Each 16TCR is an 8-bit readable/writable register that selects the timer counter clock source, selects the edge or edges of external clock sources, and selects how the counter is cleared. 16TCR is initialized to H'80 by a reset and in standby mode. Bit 7--Reserved: This bit cannot be modified and is always read as 1. Rev. 2.0, 06/04, page 335 of 980 Bits 6 and 5--Counter Clear 1 and 0 (CCLR1, CCLR0): These bits select how 16TCNT is cleared. Bit 6 CCLR1 0 1 Bit 5 CCLR0 0 1 0 1 Description 16TCNT is not cleared 16TCNT is cleared by GRA compare match or input capture* 16TCNT is cleared by GRB compare match or input capture* 1 1 (Initial value) Synchronous clear: 16TCNT is cleared in synchronization with other 2 synchronized timers* Notes: *1 16TCNT is cleared by compare match when the general register functions as an output compare register, and by input capture when the general register functions as an input capture register. *2 Selected in TSNC. Bits 4 and 3--Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select external clock input edges when an external clock source is used. Bit 4 CKEG1 0 1 Bit 3 CKEG0 0 1 -- Description Count rising edges Count falling edges Count both edges (Initial value) When channel 2 is set to phase counting mode, bits CKEG1 and CKEG0 in 16TCR2 are ignored. Phase counting takes precedence. Bits 2 to 0--Timer Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the counter clock of 16TCNT. Bit 2 TPSC2 0 Bit 1 TPSC1 0 1 1 0 1 Bit 0 TPSC0 0 1 0 1 0 1 0 1 Function Internal clock: Internal clock: /2 Internal clock: /4 Internal clock: /8 External clock A: TCLKA input External clock B: TCLKB input External clock C: TCLKC input External clock D: TCLKD input (Initial value) Rev. 2.0, 06/04, page 336 of 980 When bit TPSC2 is cleared to 0 an internal clock source is selected, and the timer counts only falling edges. When bit TPSC2 is set to 1 an external clock source is selected, and the timer counts the edges selected by bits CKEG1 and CKEG0. When channel 2 is set to phase counting mode (MDF = 1 in TMDR), the settings of bits TPSC2 to TPSC0 in 16TCR2 are ignored. Phase counting takes precedence. 9.2.10 Timer I/O Control Register (TIOR) TIOR is an 8-bit register. The 16-bit timer has three TIORs, one in each channel. Channel Abbreviation Function 0 1 2 TIOR0 TIOR1 TIOR2 TIOR controls the general registers. Some functions differ in PWM mode. Bit Initial value Read/Write 7 -- 1 -- 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 -- 1 -- 2 IOA2 0 R/W 1 IOA1 0 R/W 0 IOA0 0 R/W I/O control A2 to A0 These bits select GRA functions Reserved bit I/O control B2 to B0 These bits select GRB functions Reserved bit Each TIOR is an 8-bit readable/writable register that selects the output compare or input capture function for GRA and GRB, and specifies the functions of the TIORA and TIORB pins. If the output compare function is selected, TIOR also selects the type of output. If input capture is selected, TIOR also selects the edges of the input capture signal. TIOR is initialized to H'88 by a reset and in standby mode. Bit 7--Reserved: This bit cannot be modified and is always read as 1. Rev. 2.0, 06/04, page 337 of 980 Bits 6 to 4--I/O Control B2 to B0 (IOB2 to IOB0): These bits select the GRB function. Bit 6 IOB2 0 Bit 5 IOB1 0 1 Bit 4 IOB0 0 1 0 1 1 0 1 0 1 0 1 Notes: *1 After a reset, the output conforms to the TOLR setting until the first compare match. *2 Channel 2 output cannot be toggled by compare match. When this setting is made, 1 output is selected automatically. GRB is an input compare register Function GRB is an output compare register No output at compare match (Initial value) 1 1 0 output at GRB compare match* 1 output at GRB compare match* Output toggles at GRB compare match 12 (1 output in channel 2)* * GRB captures rising edge of input GRB captures falling edge of input GRB captures both edges of input Bit 3--Reserved: This bit cannot be modified and is always read as 1. Bits 2 to 0--I/O Control A2 to A0 (IOA2 to IOA0): These bits select the GRA function. Bit 2 IOA2 0 Bit 1 IOA1 0 1 Bit 0 IOA0 0 1 0 1 1 0 1 0 1 0 1 Notes: *1 After a reset, the output conforms to the TOLR setting until the first compare match. *2 Channel 2 output cannot be toggled by compare match. When this setting is made, 1 output is selected automatically. GRA is an input compare register Function GRA is an output compare register No output at compare match (Initial value) 1 1 0 output at GRA compare match* 1 output at GRA compare match* Output toggles at GRA compare match 12 (1 output in channel 2)* * GRA captures rising edge of input GRA captures falling edge of input GRA captures both edges of input Rev. 2.0, 06/04, page 338 of 980 9.2.11 Timer Output Level Setting Register C (TOLR) TOLR is an 8-bit write-only register that selects the timer output level for channels 0 to 2. Bit 7 -- Initial value Read/Write 1 -- 6 -- 1 -- 5 TOB2 0 W 4 TOA2 0 W 3 TOB1 0 W 2 TOA1 0 W 1 TOB0 0 W 0 TOA0 0 W Output level setting A2 to A0, B2 to B0 These bits set the levels of the timer outputs (TIOCA2 to TIOCA0, and TIOCB2 to TIOCB0) Reserved bits A TOLR setting can only be made when the corresponding bit in TSTR is 0. TOLR is a write-only register, and cannot be read. If it is read, all bits will return a value of 1. TOLR is initialized to H'C0 by a reset and in standby mode. Bits 7 and 6--Reserved: These bits cannot be modified. Bit 5--Output Level Setting B2 (TOB2): Sets the value of timer output TIOCB2. Bit 5 TOB2 0 1 Description TIOCB2 is 0 TIOCB2 is 1 (Initial value) Bit 4--Output Level Setting A2 (TOA2): Sets the value of timer output TIOCA2. Bit 4 TOA2 0 1 Description TIOCA2 is 0 TIOCA2 is 1 (Initial value) Rev. 2.0, 06/04, page 339 of 980 Bit 3--Output Level Setting B1 (TOB1): Sets the value of timer output TIOCB1. Bit 3 TOB1 0 1 Description TIOCB1 is 0 TIOCB1 is 1 (Initial value) Bit 2--Output Level Setting A1 (TOA1): Sets the value of timer output TIOCA1. Bit 2 TOA1 0 1 Description TIOCA1 is 0 TIOCA1 is 1 (Initial value) Bit 1--Output Level Setting B0 (TOB0): Sets the value of timer output TIOCB0. Bit 0 TOB0 0 1 Description TIOCB0 is 0 TIOCB0 is 1 (Initial value) Bit 0--Output Level Setting A0 (TOA0): Sets the value of timer output TIOCA0. Bit 0 TOA0 0 1 Description TIOCA0 is 0 TIOCA0 is 1 (Initial value) Rev. 2.0, 06/04, page 340 of 980 9.3 9.3.1 CPU Interface 16-Bit Accessible Registers The timer counters (16TCNTs), general registers A and B (GRAs and GRBs) are 16-bit registers, and are linked to the CPU by an internal 16-bit data bus. These registers can be written or read a word at a time, or a byte at a time. Figures 9.4 and 9.5 show examples of word read/write access to a timer counter (16TCNT). Figures 9.6 to 9.9 show examples of byte read/write access to 16TCNTH and 16TCNTL. On-chip data bus H CPU L Bus interface H L Module data bus 16TCNTH 16TCNTL Figure 9.4 16TCNT Access Operation [CPU Writes to 16TCNT, Word] On-chip data bus H CPU L Bus interface H L Module data bus 16TCNTH 16TCNTL Figure 9.5 Access to Timer Counter (CPU Reads 16TCNT, Word) Rev. 2.0, 06/04, page 341 of 980 On-chip data bus H CPU L Bus interface H L Module data bus 16TCNTH 16TCNTL Figure 9.6 Access to Timer Counter H (CPU Writes to 16TCNTH, Upper Byte) On-chip data bus H CPU L Bus interface H L Module data bus 16TCNTH 16TCNTL Figure 9.7 Access to Timer Counter L (CPU Writes to 16TCNTL, Lower Byte) On-chip data bus H CPU L Bus interface H L Module data bus 16TCNTH 16TCNTL Figure 9.8 Access to Timer Counter H (CPU Reads 16TCNTH, Upper Byte) Rev. 2.0, 06/04, page 342 of 980 On-chip data bus H CPU L Bus interface H L Module data bus 16TCNTH 16TCNTL Figure 9.9 Access to Timer Counter L (CPU Reads 16TCNTL, Lower Byte) 9.3.2 8-Bit Accessible Registers The registers other than the timer counters and general registers are 8-bit registers. These registers are linked to the CPU by an internal 8-bit data bus. Figures 9.10 and 9.11 show examples of byte read and write access to a 16TCR. If a word-size data transfer instruction is executed, two byte transfers are performed. On-chip data bus H CPU L Bus interface H L Module data bus 16TCR Figure 9.10 16TCR Access (CPU Writes to 16TCR) On-chip data bus H CPU L Bus interface H L Module data bus 16TCR Figure 9.11 16TCR Access (CPU Reads 16TCR) Rev. 2.0, 06/04, page 343 of 980 9.4 9.4.1 Operation Overview A summary of operations in the various modes is given below. Normal Operation: Each channel has a timer counter and general registers. The timer counter counts up, and can operate as a free-running counter, periodic counter, or external event counter. GRA and GRB can be used for input capture or output compare. Synchronous Operation: The timer counters in designated channels are preset synchronously. Data written to the timer counter in any one of these channels is simultaneously written to the timer counters in the other channels as well. The timer counters can also be cleared synchronously if so designated by the CCLR1 and CCLR0 bits in the TCRs. PWM Mode: A PWM waveform is output from the TIOCA pin. The output goes to 1 at compare match A and to 0 at compare match B. The duty cycle can be varied from 0% to 100% depending on the settings of GRA and GRB. When a channel is set to PWM mode, its GRA and GRB automatically become output compare registers. Phase Counting Mode: The phase relationship between two clock signals input at TCLKA and TCLKB is detected and 16TCNT2 counts up or down accordingly. When phase counting mode is selected TCLKA and TCLKB become clock input pins and 16TCNT2 operates as an up/downcounter. 9.4.2 Basic Functions Counter Operation: When one of bits STR0 to STR2 is set to 1 in the timer start register (TSTR), the timer counter (16TCNT) in the corresponding channel starts counting. The counting can be free-running or periodic. * Sample setup procedure for counter Figure 9.12 shows a sample procedure for setting up a counter. Rev. 2.0, 06/04, page 344 of 980 Counter setup Select counter clock 1 Count operation Yes Periodic counting No Free-running counting Select counter clear source 2 Select output compare register function 3 Set period 4 Start counter Periodic counter 5 Start counter Free-running counter 5 Figure 9.12 Counter Setup Procedure (Example) 1. Set bits TPSC2 to TPSC0 in 16TCR to select the counter clock source. If an external clock source is selected, set bits CKEG1 and CKEG0 in 16TCR to select the desired edge(s) of the external clock signal. 2. For periodic counting, set CCLR1 and CCLR0 in 16TCR to have 16TCNT cleared at GRA compare match or GRB compare match. 3. Set TIOR to select the output compare function of GRA or GRB, whichever was selected in step 2. 4. Write the count period in GRA or GRB, whichever was selected in step 2. 5. Set the STR bit to 1 in TSTR to start the timer counter. Rev. 2.0, 06/04, page 345 of 980 * Free-running and periodic counter operation A reset leaves the counters (16TCNTs) in 16-bit timer channels 0 to 2 all set as free-running counters. A free-running counter starts counting up when the corresponding bit in TSTR is set to 1. When the count overflows from H'FFFF to H'0000, the OVF flag is set to 1 in TISRC. After the overflow, the counter continues counting up from H'0000. Figure 9.13 illustrates free-running counting. 16TCNT value H'FFFF H'0000 STR0 to STR2 bit OVF Time Figure 9.13 Free-Running Counter Operation When a channel is set to have its counter cleared by compare match, in that channel 16TCNT operates as a periodic counter. Select the output compare function of GRA or GRB, set bit CCLR1 or CCLR0 in 16TCR to have the counter cleared by compare match, and set the count period in GRA or GRB. After these settings, the counter starts counting up as a periodic counter when the corresponding bit is set to 1 in TSTR. When the count matches GRA or GRB, the IMFA or IMFB flag is set to 1 in TISRA/TISRB and the counter is cleared to H'0000. If the corresponding IMIEA or IMIEB bit is set to 1 in TISRA/TISRB, a CPU interrupt is requested at this time. After the compare match, 16TCNT continues counting up from H'0000. Figure 9.14 illustrates periodic counting. 16TCNT value GR Counter cleared by general register compare match H'0000 STR bit IMF Time Figure 9.14 Periodic Counter Operation Rev. 2.0, 06/04, page 346 of 980 * 16TCNT count timing Internal clock source Bits TPSC2 to TPSC0 in 16TCR select the system clock () or one of three internal clock sources obtained by prescaling the system clock (/2, /4, /8). Figure 9.15 shows the timing. Internal clock 16TCNT input clock 16TCNT N-1 N N+1 Figure 9.15 Count Timing for Internal Clock Sources External clock source The external clock pin (TCLKA to TCLKD) can be selected by bits TPSC2 to TPSC0 in 16TCR, and the detected edge by bits CKEG1 and CKEG0. The rising edge, falling edge, or both edges can be selected. The pulse width of the external clock signal must be at least 1.5 system clocks when a single edge is selected, and at least 2.5 system clocks when both edges are selected. Shorter pulses will not be counted correctly. Figure 9.16 shows the timing when both edges are detected. External clock input 16TCNT input clock 16TCNT N-1 N N+1 Figure 9.16 Count Timing for External Clock Sources (when Both Edges are Detected) Rev. 2.0, 06/04, page 347 of 980 Waveform Output by Compare Match: In 16-bit timer channels 0, 1 compare match A or B can cause the output at the TIOCA or TIOCB pin to go to 0, go to 1, or toggle. In channel 2 the output can only go to 0 or go to 1. * Sample setup procedure for waveform output by compare match Figure 9.17 shows an example of the setup procedure for waveform output by compare match. Output setup Select waveform output mode 1 1. Select the compare match output mode (0, 1, or toggle) in TIOR. When a waveform output mode is selected, the pin switches from its generic input/ output function to the output compare function (TIOCA or TIOCB). An output compare pin outputs the value set in TOLR until the first compare match occurs. 2. Set a value in GRA or GRB to designate the compare match timing. Set output timing 2 Start counter 3 3. Set the STR bit in TSTR to 1 to make 16TCNT start counting. Waveform output Figure 9.17 Setup Procedure for Waveform Output by Compare Match (Example) Rev. 2.0, 06/04, page 348 of 980 * Examples of waveform output Figure 9.18 shows examples of 0 and 1 output. 16TCNT operates as a free-running counter, 0 output is selected for compare match A, and 1 output is selected for compare match B. When the pin is already at the selected output level, the pin level does not change. 16TCNT value H'FFFF GRB GRA H'0000 TIOCB Time No change No change 1 output TIOCA No change No change 0 output Figure 9.18 0 and 1 Output (TOA = 1, TOB = 0) Figure 9.19 shows examples of toggle output. 16TCNT operates as a periodic counter, cleared by compare match B. Toggle output is selected for both compare match A and B. 16TCNT value GRB Counter cleared by compare match with GRB GRA H'0000 TIOCB Time Toggle output Toggle output TIOCA Figure 9.19 Toggle Output (TOA = 1, TOB = 0) Rev. 2.0, 06/04, page 349 of 980 * Output compare output timing The compare match signal is generated in the last state in which 16TCNT and the general register match (when 16TCNT changes from the matching value to the next value). When the compare match signal is generated, the output value selected in TIOR is output at the output compare pin (TIOCA or TIOCB). When 16TCNT matches a general register, the compare match signal is not generated until the next counter clock pulse. Figure 9.20 shows the output compare timing. 16TCNT input clock 16TCNT N N+1 GR Compare match signal TIOCA, TIOCB N Figure 9.20 Output Compare Output Timing Input Capture Function: The 16TCNT value can be transferred to a general register when an input edge is detected at an input capture input/output compare pin (TIOCA or TIOCB). Risingedge, falling-edge, or both-edge detection can be selected. The input capture function can be used to measure pulse width or period. Rev. 2.0, 06/04, page 350 of 980 * Sample setup procedure for input capture Figure 9.21 shows a sample procedure for setting up input capture. Input selection 1. Set TIOR to select the input capture function of a general register and the rising edge, falling edge, or both edges of the input capture signal. Clear the DDR bit to 0 before making these TIOR settings. 1 Select input-capture input Start counter 2 2. Set the STR bit in TSTR to 1 to make 16TCNT start counting. Input capture Figure 9.21 Setup Procedure for Input Capture (Example) * Examples of input capture Figure 9.22 illustrates input capture when the falling edge of TIOCB and both edges of TIOCA are selected as capture edges. 16TCNT is cleared by input capture into GRB. 16TCNT value H'0180 H'0160 H'0005 H'0000 TIOCB TIOCA GRA H'0005 H'0160 GRB H'0180 Figure 9.22 Input Capture (Example) Rev. 2.0, 06/04, page 351 of 980 * Input capture signal timing Input capture on the rising edge, falling edge, or both edges can be selected by settings in TIOR. Figure 9.23 shows the timing when the rising edge is selected. The pulse width of the input capture signal must be at least 1.5 system clocks for single-edge capture, and 2.5 system clocks for capture of both edges. Input-capture input Input capture signal 16TCNT N GRA, GRB N Figure 9.23 Input Capture Signal Timing 9.4.3 Synchronization The synchronization function enables two or more timer counters to be synchronized by writing the same data to them simultaneously (synchronous preset). With appropriate 16TCR settings, two or more timer counters can also be cleared simultaneously (synchronous clear). Synchronization enables additional general registers to be associated with a single time base. Synchronization can be selected for all channels (0 to 2). Sample Setup Procedure for Synchronization: Figure 9.24 shows a sample procedure for setting up synchronization. Rev. 2.0, 06/04, page 352 of 980 Setup for synchronization Select synchronization 1 Synchronous preset Synchronous clear Write to 16TCNT 2 Clearing synchronized to this channel? Yes Select counter clear source No 3 Select counter clear source 4 Start counter 5 Start counter 5 Synchronous preset Counter clear Synchronous clear 1. Set the SYNC bits to 1 in TSNC for the channels to be synchronized. 2. When a value is written in 16TCNT in one of the synchronized channels, the same value is simultaneously written in 16TCNT in the other channels. 3. Set the CCLR1 or CCLR0 bit in 16TCR to have the counter cleared by compare match or input capture. 4. Set the CCLR1 and CCLR0 bits in 16TCR to have the counter cleared synchronously. 5. Set the STR bits in TSTR to 1 to start the synchronized counters. Figure 9.24 Setup Procedure for Synchronization (Example) Example of Synchronization: Figure 9.25 shows an example of synchronization. Channels 0, 1, and 2 are synchronized, and are set to operate in PWM mode. Channel 0 is set for counter clearing by compare match with GRB0. Channels 1 and 2 are set for synchronous counter clearing. The timer counters in channels 0, 1, and 2 are synchronously preset, and are synchronously cleared by compare match with GRB0. A three-phase PWM waveform is output from pins TIOCA0, TIOCA1, and TIOCA2. For further information on PWM mode, see section 9.4.4, PWM Mode. Rev. 2.0, 06/04, page 353 of 980 Value of 16TCNT0 to 16TCNT2 Cleared by compare match with GRB0 GRB0 GRB1 GRA0 GRB2 GRA1 GRA2 H'0000 TIOCA0 TIOCA1 TIOCA2 Figure 9.25 Synchronization (Example) 9.4.4 PWM Mode In PWM mode GRA and GRB are paired and a PWM waveform is output from the TIOCA pin. GRA specifies the time at which the PWM output changes to 1. GRB specifies the time at which the PWM output changes to 0. If either GRA or GRB compare match is selected as the counter clear source, a PWM waveform with a duty cycle from 0% to 100% is output at the TIOCA pin. PWM mode can be selected in all channels (0 to 2). Table 9.4 summarizes the PWM output pins and corresponding registers. If the same value is set in GRA and GRB, the output does not change when compare match occurs. Table 9.4 Channel 0 1 2 PWM Output Pins and Registers Output Pin TIOCA0 TIOCA1 TIOCA2 1 Output GRA0 GRA1 GRA2 0 Output GRB0 GRB1 GRB2 Rev. 2.0, 06/04, page 354 of 980 Sample Setup Procedure for PWM Mode: Figure 9.26 shows a sample procedure for setting up PWM mode. PWM mode Select counter clock 1 1. Set bits TPSC2 to TPSC0 in 16TCR to select the counter clock source. If an external clock source is selected, set bits CKEG1 and CKEG0 in 16TCR to select the desired edge(s) of the external clock signal. 2. Set bits CCLR1 and CCLR0 in 16TCR to select the counter clear source. 3. Set the time at which the PWM waveform should go to 1 in GRA. Select counter clear source 2 Set GRA 3 4. Set the time at which the PWM waveform should go to 0 in GRB. 5. Set the PWM bit in TMDR to select PWM mode. When PWM mode is selected, regardless of the TIOR contents, GRA and GRB become output compare registers specifying the times at which the PWM output goes to 1 and 0. The TIOCA pin automatically becomes the PWM output pin. The TIOCB pin conforms to the settings of bits IOB1 and IOB0 in TIOR. If TIOCB output is not desired, clear both IOB1 and IOB0 to 0. 6. Set the STR bit to 1 in TSTR to start the timer counter. Set GRB 4 Select PWM mode 5 Start counter 6 PWM mode Figure 9.26 Setup Procedure for PWM Mode (Example) Rev. 2.0, 06/04, page 355 of 980 Examples of PWM Mode: Figure 9.27 shows examples of operation in PWM mode. In PWM mode TIOCA becomes an output pin. The output goes to 1 at compare match with GRA, and to 0 at compare match with GRB. In the examples shown, 16TCNT is cleared by compare match with GRA or GRB. Synchronized operation and free-running counting are also possible. 16TCNT value Counter cleared by compare match A GRA GRB H'0000 Time TIOCA a. Counter cleared by GRA (TOA = 1) 16TCNT value Counter cleared by compare match B GRB GRA H'0000 Time TIOCA b. Counter cleared by GRB (TOA = 0) Figure 9.27 PWM Mode (Example 1) Rev. 2.0, 06/04, page 356 of 980 Figure 9.28 shows examples of the output of PWM waveforms with duty cycles of 0% and 100%. If the counter is cleared by compare match with GRB, and GRA is set to a higher value than GRB, the duty cycle is 0%. If the counter is cleared by compare match with GRA, and GRB is set to a higher value than GRA, the duty cycle is 100%. 16TCNT value GRB Counter cleared by compare match B GRA H'0000 Time TIOCA Write to GRA Write to GRA a. 0% duty cycle (TOA=0) 16TCNT value GRA Counter cleared by compare match A GRB H'0000 Time TIOCA Write to GRB Write to GRB b. 100% duty cycle (TOA=1) Figure 9.28 PWM Mode (Example 2) Rev. 2.0, 06/04, page 357 of 980 9.4.5 Phase Counting Mode In phase counting mode the phase difference between two external clock inputs (at the TCLKA and TCLKB pins) is detected, and 16TCNT2 counts up or down accordingly. In phase counting mode, the TCLKA and TCLKB pins automatically function as external clock input pins and 16TCNT2 becomes an up/down-counter, regardless of the settings of bits TPSC2 to TPSC0, CKEG1, and CKEG0 in 16TCR2. Settings of bits CCLR1, CCLR0 in 16TCR2, and settings in TIOR2, TISRA, TISRB, TISRC, setting of STR2 bit in TSTR, GRA2, and GRB2 are valid. The input capture and output compare functions can be used, and interrupts can be generated. Phase counting is available only in channel 2. Sample Setup Procedure for Phase Counting Mode: Figure 9.29 shows a sample procedure for setting up phase counting mode. Phase counting mode Select phase counting mode 1 1. Set the MDF bit in TMDR to 1 to select phase counting mode. 2. Select the flag setting condition with the FDIR bit in TMDR. Select flag setting condition 2 3. Set the STR2 bit to 1 in TSTR to start the timer counter. Start counter 3 Phase counting mode Figure 9.29 Setup Procedure for Phase Counting Mode (Example) Rev. 2.0, 06/04, page 358 of 980 Example of Phase Counting Mode: Figure 9.30 shows an example of operations in phase counting mode. Table 9.5 lists the up-counting and down-counting conditions for 16TCNT2. In phase counting mode both the rising and falling edges of TCLKA and TCLKB are counted. The phase difference between TCLKA and TCLKB must be at least 1.5 states, the phase overlap must also be at least 1.5 states, and the pulse width must be at least 2.5 states. 16TCNT2 value Counting up Counting down TCLKB TCLKA Figure 9.30 Operation in Phase Counting Mode (Example) Table 9.5 Counting Direction TCLKB pin TCLKA pin Low Up/Down Counting Conditions Up-Counting High High Low Down-Counting HIgh Low Low HIgh Phase difference Phase difference Pulse width Pulse width TCLKA TCLKB Phase difference and overlap: at least 1.5 states Pulse width: at least 2.5 states Overlap Overlap Figure 9.31 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode Rev. 2.0, 06/04, page 359 of 980 9.4.6 16-Bit Timer Output Timing The initial value of 16-bit timer output when a timer count operation begins can be specified arbitrarily by making a setting in TOLR. Figure 9.32 shows the timing for setting the initial value with TOLR. Only write to TOLR when the corresponding bit in TSTR is cleared to 0. T1 T2 T3 Address bus TOLR address TOLR N ITU output pin N Figure 9.32 Timing for Setting 16-Bit Timer Output Level by Writing to TOLR Rev. 2.0, 06/04, page 360 of 980 9.5 Interrupts The 16-bit timer has two types of interrupts: input capture/compare match interrupts, and overflow interrupts. 9.5.1 Setting of Status Flags Timing of Setting of IMFA and IMFB at Compare Match: IMFA and IMFB are set to 1 by a compare match signal generated when 16TCNT matches a general register (GR). The compare match signal is generated in the last state in which the values match (when 16TCNT is updated from the matching count to the next count). Therefore, when 16TCNT matches a general register, the compare match signal is not generated until the next 16TCNT clock input. Figure 9.33 shows the timing of the setting of IMFA and IMFB. 16TCNT input clock 16TCNT N N+1 GR N Compare match signal IMF IMI Figure 9.33 Timing of Setting of IMFA and IMFB by Compare Match Rev. 2.0, 06/04, page 361 of 980 Timing of Setting of IMFA and IMFB by Input Capture: IMFA and IMFB are set to 1 by an input capture signal. The 16TCNT contents are simultaneously transferred to the corresponding general register. Figure 9.34 shows the timing. Input capture signal IMF 16TCNT N GR N IMI Figure 9.34 Timing of Setting of IMFA and IMFB by Input Capture Rev. 2.0, 06/04, page 362 of 980 Timing of Setting of Overflow Flag (OVF): OVF is set to 1 when 16TCNT overflows from H'FFFF to H'0000 or underflows from H'0000 to H'FFFF. Figure 9.35 shows the timing. 16TCNT Overflow signal OVF OVI Figure 9.35 Timing of Setting of OVF 9.5.2 Timing of Clearing of Status Flags If the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is cleared. Figure 9.36 shows the timing. TISR write cycle T1 T2 T3 Address TISR address IMF, OVF Figure 9.36 Timing of Clearing of Status Flags Rev. 2.0, 06/04, page 363 of 980 9.5.3 Interrupt Sources Each 16-bit timer channel can generate a compare match/input capture A interrupt, a compare match/input capture B interrupt, and an overflow interrupt. In total there are nine interrupt sources of three kinds, all independently vectored. An interrupt is requested when the interrupt request flag are set to 1. The priority order of the channels can be modified in interrupt priority registers A (IPRA). For details see section 5, Interrupt Controller. Table 9.6 lists the interrupt sources. Table 9.6 16-bit timer Interrupt Sources Interrupt Source IMIA0 IMIB0 OVI0 IMIA1 IMIB1 OVI1 IMIA2 IMIB2 OVI2 Channel 0 Description Compare match/input capture A0 Compare match/input capture B0 Overflow 0 Compare match/input capture A1 Compare match/input capture B1 Overflow 1 Compare match/input capture A2 Compare match/input capture B2 Overflow 2 Priority* High 1 2 Low Note: * The priority immediately after a reset is indicated. Inter-channel priorities can be changed by settings in IPRA. Rev. 2.0, 06/04, page 364 of 980 9.6 Usage Notes This section describes contention and other matters requiring special attention during 16-bit timer operations. Contention between 16TCNT Write and Clear: If a counter clear signal occurs in the T3 state of a 16TCNT write cycle, clearing of the counter takes priority and the write is not performed. See figure 9.37. 16TCNT write cycle T1 T2 T3 Address bus 16TCNT address Internal write signal Counter clear signal 16TCNT N H'0000 Figure 9.37 Contention between 16TCNT Write and Clear Rev. 2.0, 06/04, page 365 of 980 Contention between 16TCNT Word Write and Increment: If an increment pulse occurs in the T3 state of a 16TCNT word write cycle, writing takes priority and 16TCNT is not incremented. Figure 9.38 shows the timing in this case. 16TCNT word write cycle T1 T2 T3 Address bus 16TCNT address Internal write signal 16TCNT input clock 16TCNT N M 16TCNT write data Figure 9.38 Contention between 16TCNT Word Write and Increment Rev. 2.0, 06/04, page 366 of 980 Contention between 16TCNT Byte Write and Increment: If an increment pulse occurs in the T2 or T3 state of a 16TCNT byte write cycle, writing takes priority and 16TCNT is not incremented. The byte data for which a write was not performed is not incremented, and retains its pre-write value. See figure 9.39, which shows an increment pulse occurring in the T2 state of a byte write to 16TCNTH. 16TCNTH byte write cycle T1 T2 T3 Address bus 16TCNTH address Internal write signal 16TCNT input clock 16TCNTH N 16TCNT write data M 16TCNTL X X+1 X Figure 9.39 Contention between 16TCNT Byte Write and Increment Rev. 2.0, 06/04, page 367 of 980 Contention between General Register Write and Compare Match: If a compare match occurs in the T3 state of a general register write cycle, writing takes priority and the compare match signal is inhibited. See figure 9.40. General register write cycle T1 T2 T3 Address bus GR address Internal write signal 16TCNT N N+1 GR N M General register write data Compare match signal Inhibited Figure 9.40 Contention between General Register Write and Compare Match Rev. 2.0, 06/04, page 368 of 980 Contention between 16TCNT Write and Overflow or Underflow: If an overflow occurs in the T3 state of a 16TCNT write cycle, writing takes priority and the counter is not incremented. OVF is set to 1. The same holds for underflow. See figure 9.41. 16TCNT write cycle T1 T2 T3 Address bus 16TCNT address Internal write signal 16TCNT input clock Overflow signal 16TCNT H'FFFF 16TCNT write data M OVF Figure 9.41 Contention between 16TCNT Write and Overflow Rev. 2.0, 06/04, page 369 of 980 Contention between General Register Read and Input Capture: If an input capture signal occurs during the T3 state of a general register read cycle, the value before input capture is read. See figure 9.42. General register read cycle T1 T2 T3 Address bus GR address Internal read signal Input capture signal GR X M Internal data bus X Figure 9.42 Contention between General Register Read and Input Capture Rev. 2.0, 06/04, page 370 of 980 Contention between Counter Clearing by Input Capture and Counter Increment: If an input capture signal and counter increment signal occur simultaneously, the counter is cleared according to the input capture signal. The counter is not incremented by the increment signal. The value before the counter is cleared is transferred to the general register. See figure 9.43. Input capture signal Counter clear signal 16TCNT input clock 16TCNT N H'0000 GR N Figure 9.43 Contention between Counter Clearing by Input Capture and Counter Increment Rev. 2.0, 06/04, page 371 of 980 Contention between General Register Write and Input Capture: If an input capture signal occurs in the T3 state of a general register write cycle, input capture takes priority and the write to the general register is not performed. See figure 9.44. General register write cycle T1 T2 T3 Address bus GR address Internal write signal Input capture signal 16TCNT M GR M Figure 9.44 Contention between General Register Write and Input Capture Rev. 2.0, 06/04, page 372 of 980 Note on Waveform Period Setting: When a counter is cleared by compare match, the counter is cleared in the last state at which the 16TCNT value matches the general register value, at the time when this value would normally be updated to the next count. The actual counter frequency is therefore given by the following formula: f= (N+1) (f: counter frequency. : system clock frequency. N: value set in general register.) Note on Writes in Synchronized Operation: When channels are synchronized, if a 16TCNT value is modified by byte write access, all 16 bits of all synchronized counters assume the same value as the counter that was addressed. (Example) When channels 1 and 2 are synchronized * Byte write to channel 1 or byte write to channel 2 Write A to upper byte of channel 1 16TCNT1 16TCNT2 W Y X Z 16TCNT1 16TCNT2 A A X X Upper byte Lower byte Write A to lower byte of channel 2 16TCNT1 16TCNT2 Upper byte Lower byte Y Y A A Upper byte Lower byte * Word write to channel 1 or word write to channel 2 16TCNT1 16TCNT2 W Y X Z Write AB word to channel 1 or 2 16TCNT1 16TCNT2 A A B B Upper byte Lower byte Upper byte Lower byte Rev. 2.0, 06/04, page 373 of 980 16-bit timer Operating Modes Table 9.7 (a)16-bit timer Operating Modes (Channel 0) Register Settings TSNC Operating Mode Synchronous preset PWM mode Output compare A Synchronization MDF TMDR FDIR PWM IOA TIOR0 IOB 16TCR0 Clear Select Clock Select SYNC0 = 1 -- -- -- -- -- -- PWM0 = 1 PWM0 = 0 -- IOA2 = 0 Other bits unrestricted * Output compare B -- -- IOB2 = 0 Other bits unrestricted PWM0 = 0 IOA2 = 1 Other bits unrestricted IOB2 = 1 Other bits unrestricted CCLR1 = 0 CCLR0 = 1 CCLR1 = 1 CCLR0 = 0 CCLR1 = 1 CCLR0 = 1 Input capture A -- -- Input capture B -- -- PWM0 = 0 Counter By compare clearing match/input capture A By compare match/input capture B Synchronous clear Legend: -- -- -- -- SYNC0 = 1 -- -- Setting available (valid). -- Setting does not affect this mode. Note: * The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited. Rev. 2.0, 06/04, page 374 of 980 Table 9.7 (b) 16-bit timer Operating Modes (Channel 1) Register Settings TSNC TMDR MDF FDIR PWM -- -- -- PWM1 = 1 PWM1 = 0 -- IOA2 = 0 Other bits unrestricted IOB2 = 0 Other bits unrestricted PWM1 = 0 IOA2 = 1 Other bits unrestricted IOB2 = 1 Other bits unrestricted CCLR1 = 0 CCLR0 = 1 CCLR1 = 1 CCLR0 = 0 CCLR1 = 1 CCLR0 = 1 * IOA TIOR1 IOB 16TCR1 Clear Select Clock Select Operating Mode Synchronous preset PWM mode Output compare A Synchronization SYNC1 = 1 -- -- -- Output compare B -- -- Input capture A -- -- Input capture B -- -- PWM1 = 0 Counter By compare clearing match/input capture A By compare match/input capture B Synchronous clear -- -- -- -- SYNC1 = 1 -- -- Legend: Setting available (valid). -- Setting does not affect this mode. Note: * The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited. Rev. 2.0, 06/04, page 375 of 980 Table 9.7 (c) 16-bit timer Operating Modes (Channel 2) Register Settings TSNC Operating Mode Synchronous preset PWM mode Output compare A Synchronization SYNC2 = 1 MDF TMDR FDIR PWM -- -- -- PWM2 = 1 PWM2 = 0 -- IOA2 = 0 Other bits unrestricted IOB2 = 0 Other bits unrestricted PWM2 = 0 IOA2 = 1 Other bits unrestricted IOB2 = 1 Other bits unrestricted CCLR1 = 0 CCLR0 = 1 CCLR1 = 1 CCLR0 = 0 CCLR1 = 1 CCLR0 = 1 -- * IOA TIOR2 IOB 16TCR2 Clear Select Clock Select Output compare B -- Input capture A -- Input capture B -- PWM2 = 0 Counter By compare clearing match/input capture A By compare match/input capture B Synchronous clear Phase counting mode SYNC2 = 1 -- -- -- MDF = 1 Legend: Setting available (valid). -- Setting does not affect this mode. Note: * The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited. Rev. 2.0, 06/04, page 376 of 980 Section 10 8-Bit Timers 10.1 Overview The H8/3029 has a built-in 8-bit timer module with four channels (TMR0, TMR1, TMR2, and TMR3), based on 8-bit counters. Each channel has an 8-bit timer counter (8TCNT) and two 8-bit time constant registers (TCORA and TCORB) that are constantly compared with the 8TCNT value to detect compare match events. The timers can be used as multifunctional timers in a variety of applications, including the generation of a rectangular-wave output with an arbitrary duty cycle. 10.1.1 Features The features of the 8-bit timer module are listed below. * Selection of four clock sources The counters can be driven by one of three internal clock signals (/8, /64, or /8192) or an external clock input (enabling use as an external event counter). * Selection of three ways to clear the counters The counters can be cleared on compare match A or B, or input capture B. * Timer output controlled by two compare match signals The timer output signal in each channel is controlled by two independent compare match signals, enabling the timer to generate output waveforms with an arbitrary duty cycle or PWM output. * A/D converter can be activated by a compare match * Two channels can be cascaded Channels 0 and 1 can be operated as the upper and lower halves of a 16-bit timer (16-bit count mode). Channels 2 and 3 can be operated as the upper and lower halves of a 16-bit timer (16-bit count mode). Channel 1 can count channel 0 compare match events (compare match count mode). Channel 3 can count channel 2 compare match events (compare match count mode). * Input capture function can be set 8-bit or 16-bit input capture operation is available. Rev. 2.0, 06/04, page 377 of 980 * Twelve interrupt sources There are twelve interrupt sources: four compare match sources, four compare match/input capture sources, four overflow sources. Two of the compare match sources and two of the combined compare match/input capture sources each have an independent interrupt vector. The remaining compare match interrupts, combined compare match/input capture interrupts, and overflow interrupts have one interrupt vector for two sources. Rev. 2.0, 06/04, page 378 of 980 10.1.2 Block Diagram The 8-bit timers are divided into two groups of two channels each: group 0 comprising channels 0 and 1, and group 1 comprising channels 2 and 3. Figure 10.1 shows a block diagram of 8-bit timer group 0. External clock sources TCLKA TCLKC Internal clock sources /8 /64 /8192 Clock 1 Clock select Clock 0 TCORA0 Compare match A1 Compare match A0 Comparator A0 Overflow 1 Overflow 0 TMO0 TMIO1 Control logic Compare match B0 Comparator B0 Input capture B1 TCORB0 Comparator B1 8TCNT0 8TCNT1 Internal bus TCORA1 Comparator A1 Compare match B1 TCORB1 8TCSR0 8TCSR1 8TCR0 CMIA0 CMIB0 CMIA1/CMIB1 OVI0/OVI1 Interrupt signals Time constant register A Time constant register B Timer counter Timer control/status register Timer control register 8TCR1 Legend: TCORA: TCORB: 8TCNT: 8TCSR: 8TCR: Figure 10.1 Block Diagram of 8-Bit Timer Unit (Two Channels: Group 0) Rev. 2.0, 06/04, page 379 of 980 10.1.3 Pin Configuration Table 10.1 summarizes the input/output pins of the 8-bit timer module. Table 10.1 8-Bit Timer Pins Group 0 Channel Name 0 1 Timer output Timer clock input Abbreviation I/O TMO0 TCLKC Function Output Compare match output Input I/O Input Input I/O Input Counter external clock input Compare match output/input capture input Counter external clock input Counter external clock input Compare match output/input capture input Counter external clock input Timer input/output TMIO1 Timer clock input TCLKA TMO2 TCLKD 1 2 3 Timer output Timer clock input Output Compare match output Timer input/output TMIO3 Timer clock input TCLKB Rev. 2.0, 06/04, page 380 of 980 10.1.4 Register Configuration Table 10.2 summarizes the registers of the 8-bit timer module. Table 10.2 8-Bit Timer Registers Channel Address* 0 H'FFF80 H'FFF82 H'FFF84 H'FFF86 H'FFF88 1 H'FFF81 H'FFF83 H'FFF85 H'FFF87 H'FFF89 2 H'FFF90 H'FFF92 H'FFF94 H'FFF96 H'FFF98 3 H'FFF91 H'FFF93 H'FFF95 H'FFF97 H'FFF99 1 Name Timer control register 0 Timer control/status register 0 Time constant register A0 Time constant register B0 Timer counter 0 Timer control register 1 Timer control/status register 1 Time constant register A1 Time constant register B1 Timer counter 1 Timer control register 2 Timer control/status register 2 Time constant register A2 Time constant register B2 Timer counter 2 Timer control register 3 Timer control/status register 3 Time constant register A3 Time constant register B3 Timer counter 3 Abbreviation R/W 8TCR0 8TCSR0 TCORA0 TCORB0 8TCNT0 8TCR1 8TCSR1 TCORA1 TCORB1 8TCNT1 8TCR2 8TCSR2 TCORA2 TCORB2 8TCNT2 8TCR3 8TCSR3 TCORA3 TCORB3 8TCNT3 R/W 2 Initial value H'00 H'FF H'FF H'00 H'00 2 R/(W)* H'00 R/W R/W R/W R/W R/W R/W R/W R/W 2 R/(W)* H'00 H'FF H'FF H'00 H'00 H'FF H'FF H'00 H'00 2 R/(W)* H'10 R/W R/W R/W R/W R/W R/W R/W R/(W)* H'00 H'FF H'FF H'00 Notes: *1 Indicates the lower 20 bits of the address in advanced mode. *2 Only 0 can be written to bits 7 to 5, to clear these flags. Each pair of registers for channel 0 and channel 1 comprises a 16-bit register with the channel 0 register as the upper 8 bits and the channel 1 register as the lower 8 bits, so they can be accessed together by word access. Similarly, each pair of registers for channel 2 and channel 3 comprises a 16-bit register with the channel 2 register as the upper 8 bits and the channel 3 register as the lower 8 bits, so they can be accessed together by word access. Rev. 2.0, 06/04, page 381 of 980 10.2 10.2.1 Register Descriptions Timer Counters (8TCNT) 8TCNT0 Bit 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 8TCNT1 4 0 3 0 2 0 1 0 0 0 Initial value Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8TCNT2 8TCNT3 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Bit Initial value Read/Write 15 0 14 0 13 0 12 0 11 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The timer counters (8TCNT) are 8-bit readable/writable up-counters that increment on pulses generated from an internal or external clock source. The clock source is selected by clock select bits 2 to 0 (CKS2 to CKS0) in the timer control register (8TCR). The CPU can always read or write to the timer counters. The 8TCNT0 and 8TCNT1 pair, and the 8TCNT2 and 8TCNT3 pair, can each be accessed as a 16-bit register by word access. 8TCNT can be cleared by an input capture signal or compare match signal. Counter clear bits 1 and 0 (CCLR1 and CCLR0) in 8TCR select the method of clearing. When 8TCNT overflows from H'FF to H'00, the overflow flag (OVF) in the timer control/status register (8TCSR) is set to 1. Each 8TCNT is initialized to H'00 by a reset and in standby mode. Rev. 2.0, 06/04, page 382 of 980 10.2.2 Time Constant Registers A (TCORA) TCORA0 to TCORA3 are 8-bit readable/writable registers. TCORA0 Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 TCORA1 4 1 3 1 2 1 1 1 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCORA2 TCORA3 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The TCORA0 and TCORA1 pair, and the TCORA2 and TCORA3 pair, can each be accessed as a 16-bit register by word access. The TCORA value is constantly compared with the 8TCNT value. When a match is detected, the corresponding compare match flag A (CMFA) is set to 1 in 8TCSR. The timer output can be freely controlled by these compare match signals and the settings of output select bits 1 and 0 (OS1, OS0) in 8TCSR. Each TCORA register is initialized to H'FF by a reset and in standby mode. Rev. 2.0, 06/04, page 383 of 980 10.2.3 Time Constant Registers B (TCORB) TCORB0 Bit 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 TCORB1 4 1 3 1 2 1 1 1 0 1 Initial value Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCORB2 TCORB3 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCORB0 to TCORB3 are 8-bit readable/writable registers. The TCORB0 and TCORB1 pair, and the TCORB2 and TCORB3 pair, can each be accessed as a 16-bit register by word access. The TCORB value is constantly compared with the 8TCNT value. When a match is detected, the corresponding compare match flag B (CMFB) is set to 1 in 8TCSR*. The timer output can be freely controlled by these compare match signals and the settings of output/input capture edge select bits 3 and 2 (OIS3, OIS2) in 8TCSR. When TCORB is used for input capture, it stores the 8TCNT value on detection of an external input capture signal. At this time, the CMFB flag is set to 1 in the corresponding 8TCSR register. The detected edge of the input capture signal is set in 8TCSR. Each TCORB register is initialized to H'FF by a reset and in standby mode. Note: * When channel 1 and channel 3 are designated for TCORB input capture, the CMFB flag is not set by a channel 0 or channel 2 compare match B. Rev. 2.0, 06/04, page 384 of 980 10.2.4 Timer Control Register (8TCR) Bit 7 CMIEB 0 R/W 6 CMIEA 0 R/W 5 OVIE 0 R/W 4 CCLR1 0 R/W 3 CCLR0 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Initial value Read/Write 8TCR is an 8-bit readable/writable register that selects the 8TCNT input clock, gives the 8TCNT clearing specification, and enables interrupt requests. 8TCR is initialized to H'00 by a reset and in standby mode. For the timing, see section 10.4, Operation. Bit 7--Compare Match Interrupt Enable B (CMIEB): Enables or disables the CMIB interrupt request when the CMFB flag is set to 1 in 8TCSR. Bit 7 CMIEB 0 1 Description CMIB interrupt requested by CMFB is disabled CMIB interrupt requested by CMFB is enabled (Initial value) Bit 6--Compare Match Interrupt Enable A (CMIEA): Enables or disables the CMIA interrupt request when the CMFA flag is set to 1 in 8TCSR. Bit 6 CMIEA 0 1 Description CMIA interrupt requested by CMFA is disabled CMIA interrupt requested by CMFA is enabled (Initial value) Bit 5--Timer Overflow Interrupt Enable (OVIE): Enables or disables the OVI interrupt request when the OVF flag is set to 1 in 8TCSR. Bit 5 OVIE 0 1 Description OVI interrupt requested by OVF is disabled OVI interrupt requested by OVF is enabled (Initial value) Rev. 2.0, 06/04, page 385 of 980 Bits 4 and 3--Counter Clear 1 and 0 (CCLR1, CCLR0): These bits specify the 8TCNT clearing source. Compare match A or B, or input capture B, can be selected as the clearing source. Bit 4 CCLR1 0 1 Bit 3 CCLR0 0 1 0 1 Description Clearing is disabled Cleared by compare match A Cleared by compare match B/input capture B Cleared by input capture B (Initial value) Note: When input capture B is set as the 8TCNT1 and 8TCNT3 counter clear source, 8TCNT0 and 8TCNT2 are not cleared by compare match B. Bits 2 to 0--Clock Select 2 to 0 (CSK2 to CSK0): These bits select whether the clock input to 8TCNT is an internal or external clock. Three internal clocks can be selected, all divided from the system clock (): /8, /64, and /8192. The rising edge of the selected internal clock triggers the count. When use of an external clock is selected, three types of count can be selected: at the rising edge, the falling edge, and both rising and falling edges. When CKS2, CKS1, CKS0 = 1, 0, 0, channels 0 and 1 and channels 2 and 3 are cascaded. The incrementing clock source is different when 8TCR0 and 8TCR2 are set, and when 8TCR1 and 8TCR3 are set. Rev. 2.0, 06/04, page 386 of 980 Bit 2 CSK2 0 Bit 1 CSK1 0 1 Bit 0 CSK0 0 1 0 1 0 Description Clock input disabled Internal clock, counted on falling edge of /8 Internal clock, counted on falling edge of /64 Internal clock, counted on falling edge of /8192 Channel 0 (16-bit count mode): Count on 8TCNT1 overflow 1 signal* Channel 1 (compare match count mode): Count on 8TCNT0 1 compare match A* Channel 2 (16-bit count mode): Count on 8TCNT3 overflow 2 signal* Channel 3 (compare match count mode): Count on 8TCNT2 2 compare match A* (Initial value) 1 0 1 1 0 1 External clock, counted on rising edge External clock, counted on falling edge External clock, counted on both rising and falling edges Notes: *1 If the clock input of channel 0 is the 8TCNT1 overflow signal and that of channel 1 is the 8TCNT0 compare match signal, no incrementing clock is generated. Do not use this setting. *2 If the clock input of channel 2 is the 8TCNT3 overflow signal and that of channel 3 is the 8TCNT2 compare match signal, no incrementing clock is generated. Do not use this setting. Rev. 2.0, 06/04, page 387 of 980 10.2.5 Timer Control/Status Registers (8TCSR) 8TCSR0 Bit Initial value Read/Write 7 CMFB 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 ADTE 0 R/W 3 OIS3 0 R/W 2 OIS2 0 R/W 1 OS1 0 R/W 0 OS0 0 R/W 8TCSR2 Bit Initial value Read/Write 7 CMFB 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 -- 1 -- 3 OIS3 0 R/W 2 OIS2 0 R/W 1 OS1 0 R/W 0 OS0 0 R/W 8TCSR1, 8TCSR3 7 Bit CMFB Initial value Read/Write 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 ICE 0 R/W 3 OIS3 0 R/W 2 OIS2 0 R/W 1 OS1 0 R/W 0 OS0 0 R/W Note: * Only 0 can be written to bits 7 to 5, to clear these flags. The timer control/status registers 8TCSR are 8-bit registers that indicate compare match/input capture and overflow statuses, and control compare match output/input capture edge selection. 8TCSR2 is initialized to H'10, and 8TCSR0, 8TCSR1, and 8TCSR3 to H'00, by a reset and in standby mode. Rev. 2.0, 06/04, page 388 of 980 Bit 7--Compare Match/Input Capture Flag B (CMFB): Status flag that indicates the occurrence of a TCORB compare match or input capture. Bit 7 CMFB 0 1 Description [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB [Setting conditions] * 8TCNT = TCORB* * Note: * The 8TCNT value is transferred to TCORB by an input capture signal when TCORB functions as an input capture register (Initial value) When bit ICE is set to 1 in 8TCSR1 and 8TCSR3, the CMFB flag is not set when 8TCNT0 = TCORB0 or 8TCNT2 = TCORB2. Bit 6--Compare Match Flag A (CMFA): Status flag that indicates the occurrence of a TCORA compare match. Bit 6 CMFA 0 1 Description [Clearing condition] Read CMFA when CMFA = 1, then write 0 in CMFA [Setting condition] 8TCNT = TCORA (Initial value) Bit 5--Timer Overflow Flag (OVF): Status flag that indicates that the 8TCNT has overflowed from H'FF to H'00. Bit 5 OVF 0 1 Description [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF [Setting condition] 8TCNT overflows from H'FF to H'00 (Initial value) Rev. 2.0, 06/04, page 389 of 980 Bit 4--A/D Trigger Enable (ADTE) (In 8TCSR0): In combination with TRGE in the A/D control register (ADCR), enables or disables A/D converter start requests by compare match A or an external trigger. TRGE* 0 Bit 4 ADTE 0 1 1 0 1 Note: * Description A/D converter start requests by compare match A or external trigger pin (ADTRG) input are disabled (Initial value) A/D converter start requests by compare match A or external trigger pin (ADTRG) input are disabled A/D converter start requests by external trigger pin (ADTRG) input are enabled, and A/D converter start requests by compare match A are disabled A/D converter start requests by compare match A are enabled, and A/D converter start requests by external trigger pin (ADTRG) input are disabled TRGE is bit 7 of the A/D control register (ADCR). Bit 4--Reserved (In 8TCSR1): This bit is a reserved bit, but can be read and written. Bit 4--Input Capture Enable (ICE) (In 8TCSR1 and 8TCSR3): Selects the function of TCORB1 and TCORB3. Bit 4 ICE 0 1 Description TCORB1 and TCORB3 are compare match registers TCORB1 and TCORB3 are input capture registers (Initial value) When bit ICE is set to 1 in 8TCSR1 or 8TCSR3, the operation of the TCORA and TCORB registers in channels 0 to 3 is as shown in the tables below. Rev. 2.0, 06/04, page 390 of 980 Table 10.3 Operation of Channels 0 and 1 when Bit ICE is Set to 1 in 8TCSR1 Register Register Register Function Status Flag Change Timer Output Capture Input Interrupt Request CMIA0 interrupt request generated by compare match CMIB0 interrupt request not generated by compare match TCORA0 Compare match CMFA changed from 0 TMO0 output controllable operation to 1 in 8TCSR0 by compare match TCORB0 Compare match CMFB not changed No output from operation from 0 to 1 in 8TCSR0 TMO0 by compare match TCORA1 Compare match CMFA changed from 0 TMIO1 is dedicated CMIA1 interrupt request operation to 1 in 8TCSR1 by input capture pin generated by compare compare match match TCORB1 Input capture operation CMFB changed from 0 TMIO1 is dedicated CMIB1 interrupt request to 1 in 8TCSR1 by input capture pin generated by input input capture capture Table 10.4 Operation of Channels 2 and 3 when Bit ICE is Set to 1 in 8TCSR3 Register Register Register Function Status Flag Change Timer Output Capture Input Interrupt Request CMIA2 interrupt request generated by compare match CMIB2 interrupt request not generated by compare match TCORA2 Compare match CMFA changed from 0 TMO2 output controllable operation to 1 in 8TCSR2 by compare match TCORB2 Compare match CMFB not changed No output from operation from 0 to 1 in 8TCSR2 TMO2 by compare match TCORA3 Compare match CMFA changed from 0 TMIO3 is dedicated CMIA3 interrupt request operation to 1 in 8TCSR3 by input capture pin generated by compare compare match match TCORB3 Input capture operation CMFB changed from 0 TMIO3 is dedicated CMIB3 interrupt request to 1 in 8TCSR3 by input capture pin generated by input input capture capture Rev. 2.0, 06/04, page 391 of 980 Bits 3 and 2--Output/Input Capture Edge Select B3 and B2 (OIS3, OIS2): In combination with the ICE bit in 8TCSR1 (8TCSR3), these bits select the compare match B output level or the input capture input detected edge. The function of TCORB1 (TCORB3) depends on the setting of bit 4 of 8TCSR1 (8TCSR3). ICE Bit in 8TCSR1 Bit 3 Bit 2 (8TCSR3) OIS3 OIS2 Description 0 0 1 1 0 1 0 1 0 1 0 1 0 1 No change when compare match B occurs 0 is output when compare match B occurs 1 is output when compare match B occurs Output is inverted when compare match B occurs (toggle output) TCORB input capture on rising edge TCORB input capture on falling edge TCORB input capture on both rising and falling edges (Initial value) * When the compare match register function is used, the timer output priority order is: toggle output > 1 output > 0 output. * If compare match A and B occur simultaneously, the output changes in accordance with the higher-priority compare match. * When bits OIS3, OIS2, OS1, and OS0 are all cleared to 0, timer output is disabled. Bits 1 and 0--Output Select A1 and A0 (OS1, OS0): These bits select the compare match A output level. Bit 1 OS1 0 1 Bit 0 OS0 0 1 0 1 Description No change when compare match A occurs 0 is output when compare match A occurs 1 is output when compare match A occurs Output is inverted when compare match A occurs (toggle output) (Initial value) * When the compare match register function is used, the timer output priority order is: toggle output > 1 output > 0 output. * If compare match A and B occur simultaneously, the output changes in accordance with the higher-priority compare match. * When bits OIS3, OIS2, OS1, and OS0 are all cleared to 0, timer output is disabled. Rev. 2.0, 06/04, page 392 of 980 10.3 10.3.1 CPU Interface 8-Bit Registers 8TCNT, TCORA, TCORB, 8TCR, and 8TCSR are 8-bit registers. These registers are connected to the CPU by an internal 16-bit data bus and can be read and written a word at a time or a byte at a time. Figures 10.2 and 10.3 show the operation in word read and write accesses to 8TCNT. Figures 10.4 to 10.7 show the operation in byte read and write accesses to 8TCNT0 and 8TCNT1. Internal data bus H C P U L Bus interface H L Module data bus 8TCNT0 8TCNT1 Figure 10.2 8TCNT Access Operation (CPU Writes to 8TCNT, Word) Internal data bus H C P U L Bus interface H L Module data bus 8TCNT0 8TCNT1 Figure 10.3 8TCNT Access Operation (CPU Reads 8TCNT, Word) Internal data bus H C P U L Bus interface H L Module data bus 8TCNTH0 8TCNTL1 Figure 10.4 8TCNT0 Access Operation (CPU Writes to 8TCNT0, Upper Byte) Rev. 2.0, 06/04, page 393 of 980 Internal data bus H C P U L Bus interface H L Module data bus 8TCNTH0 8TCNTL1 Figure 10.5 8TCNT1 Access Operation (CPU Writes to 8TCNT1, Lower Byte) Internal data bus H C P U L Bus interface H L Module data bus 8TCNT0 8TCNT1 Figure 10.6 8TCNT0 Access Operation (CPU Reads 8TCNT0, Upper Byte) Internal data bus H C P U L Bus interface H L Module data bus 8TCNT0 8TCNT1 Figure 10.7 8TCNT1 Access Operation (CPU Reads 8TCNT1, Lower Byte) Rev. 2.0, 06/04, page 394 of 980 10.4 10.4.1 Operation 8TCNT Count Timing 8TCNT is incremented by input clock pulses (either internal or external). Internal Clock: Three different internal clock signals (/8, /64, or /8192) divided from the system clock () can be selected, by setting bits CKS2 to CKS0 in 8TCR. Figure 10.8 shows the count timing. Internal clock 8TCNT input clock 8TCNT N-1 N N+1 Note: Even if the same internal clock is selected for the 16-bit timer and the 8-bit timer, the same operation will not be performed since the incrementing edge is different in each case. Figure 10.8 Count Timing for Internal Clock Input External Clock: Three incrementation methods can be selected by setting bits CKS2 to CKS0 in 8TCR: on the rising edge, the falling edge, and both rising and falling edges. The pulse width of the external clock signal must be at least 1.5 system clocks when a single edge is selected, and at least 2.5 system clocks when both edges are selected. Shorter pulses will not be counted correctly. Figure 10.9 shows the timing for incrementation on both edges of the external clock signal. Rev. 2.0, 06/04, page 395 of 980 External clock input 8TCNT input clock 8TCNT N-1 N N+1 Figure 10.9 Count Timing for External Clock Input (Both-Edge Detection) 10.4.2 Compare Match Timing Timer Output Timing: When compare match A or B occurs, the timer output is as specified by the OIS3, OIS2, OS1, and OS0 bits in 8TCSR (unchanged, 0 output, 1 output, or toggle output). Figure 10.10 shows the timing when the output is set to toggle on compare match A. Compare match A signal Timer output Figure 10.10 Timing of Timer Output Rev. 2.0, 06/04, page 396 of 980 Clear by Compare Match: Depending on the setting of the CCLR1 and CCLR0 bits in 8TCR, 8TCNT can be cleared when compare match A or B occurs, Figure 10.11 shows the timing of this operation. Compare match signal 8TCNT N H'00 Figure 10.11 Timing of Clear by Compare Match Clear by Input Capture: Depending on the setting of the CCLR1 and CCLR0 bits in 8TCR, 8TCNT can be cleared when input capture B occurs. Figure 10.12 shows the timing of this operation. Input capture input Input capture signal 8TCNT N H '00 Figure 10.12 Timing of Clear by Input Capture 10.4.3 Input Capture Signal Timing Input capture on the rising edge, falling edge, or both edges can be selected by settings in 8TCSR. Figure 10.13 shows the timing when the rising edge is selected. The pulse width of the input capture input signal must be at least 1.5 system clocks when a single edge is selected, and at least 2.5 system clocks when both edges are selected. Rev. 2.0, 06/04, page 397 of 980 Input capture input Input capture signal 8TCNT N TCORB N Figure 10.13 Timing of Input Capture Input Signal 10.4.4 Timing of Status Flag Setting Timing of CMFA/CMFB Flag Setting when Compare Match Occurs: The CMFA and CMFB flags in 8TCSR are set to 1 by the compare match signal output when the TCORA or TCORB and 8TCNT values match. The compare match signal is generated in the last state of the match (when the matched 8TCNT count value is updated). Therefore, after the 8TCNT and TCORA or TCORB values match, the compare match signal is not generated until an incrementing clock pulse signal is generated. Figure 10.14 shows the timing in this case. 8TCNT TCOR N N N+1 Compare match signal CMF Figure 10.14 CMF Flag Setting Timing when Compare Match Occurs Timing of CMFB Flag Setting when Input Capture Occurs: On generation of an input capture signal, the CMFB flag is set to 1 and at the same time the 8TCNT value is transferred to TCORB. Figure 10.15 shows the timing in this case. Rev. 2.0, 06/04, page 398 of 980 8TCNT TCORB N N Input capture signal CMFB Figure 10.15 CMFB Flag Setting Timing when Input Capture Occurs Timing of Overflow Flag (OVF) Setting: The OVF flag in 8TCSR is set to 1 by the overflow signal generated when 8TCNT overflows (from H'FF to H'00). Figure 10.16 shows the timing in this case. 8TCNT H'FF H'00 Overflow signal OVF Figure 10.16 Timing of OVF Setting 10.4.5 Operation with Cascaded Connection If bits CKS2 to CKS0 are set to (100) in either 8TCR0 or 8TCR1, the 8-bit timers of channels 0 and 1 are cascaded. With this configuration, the two timers can be used as a single 16-bit timer (16-bit timer mode), or channel 0 8-bit timer compare matches can be counted in channel 1 (compare match count mode). Similarly, if bits CKS2 to CKS0 are set to (100) in either 8TCR2 or 8TCR3, the 8-bit timers of channels 2 and 3 are cascaded. With this configuration, the two timers can be used as a single 16-bit timer (16-bit timer mode),or channel 2 8-bit timer compare matches can be counted in channel 3 (compare match count mode). In this case, the timer operates as below. Rev. 2.0, 06/04, page 399 of 980 16-Bit Count Mode * Channels 0 and 1: When bits CKS2 to CKS0 are set to (100) in 8TCR0, the timer functions as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits. Setting when Compare Match Occurs * The CMFA or CMFB flag is set to 1 in 8TCSR0 when a 16-bit compare match occurs. * The CMFA or CMFB flag is set to 1 in 8TCSR1 when a lower 8-bit compare match occurs. * TMO0 pin output control by bits OIS3, OIS2, OS1, and OS0 in 8TCSR0 is in accordance with the 16-bit compare match conditions. * TMIO1 pin output control by bits OIS3, OIS2, OS1, and OS0 in 8TCSR1 is in accordance with the lower 8-bit compare match conditions. Setting when Input Capture Occurs * The CMFB flag is set to 1 in 8TCSR0 and 8TCSR1 when the ICE bit is 1 in TCSR1 and input capture occurs. * TMIO1 pin input capture input signal edge detection is selected by bits OIS3 and OIS2 in 8TCSR0. Counter Clear Specification * If counter clear on compare match or input capture has been selected by the CCLR1 and CCLR0 bits in 8TCR0, the 16-bit counter (both 8TCNT0 and 8TCNT1) is cleared. * The settings of the CCLR1 and CCLR0 bits in 8TCR1 are ignored. The lower 8 bits cannot be cleared independently. OVF Flag Operation * The OVF flag is set to 1 in 8TCSR0 when the 16-bit counter (8TCNT0 and 8TCNT1) overflows (from H'FFFF to H'0000). * The OVF flag is set to 1 in 8TCSR1 when the 8-bit counter (8TCNT1) overflows (from H'FF to H'00). * Channels 2 and 3: When bits CKS2 to CKS0 are set to (100) in 8TCR2, the timer functions as a single 16-bit timer with channel 2 occupying the upper 8 bits and channel 3 occupying the lower 8 bits. Setting when Compare Match Occurs * The CMFA or CMFB flag is set to 1 in 8TCSR2 when a 16-bit compare match occurs. * The CMFA or CMFB flag is set to 1 in 8TCSR3 when a lower 8-bit compare match occurs. * TMO2 pin output control by bits OIS3, OIS2, OS1, and OS0 in 8TCSR2 is in accordance with the 16-bit compare match conditions. * TMIO3 pin output control by bits OIS3, OIS2, OS1, and OS0 in 8TCSR3 is in accordance with the lower 8-bit compare match conditions. Rev. 2.0, 06/04, page 400 of 980 Setting when Input Capture Occurs * The CMFB flag is set to 1 in 8TCSR2 and 8TCSR3 when the ICE bit is 1 in TCSR3 and input capture occurs. * TMIO3 pin input capture input signal edge detection is selected by bits OIS3 and OIS2 in 8TCSR2. Counter Clear Specification * If counter clear on compare match has been selected by the CCLR1 and CCLR0 bits in 8TCR2, the 16-bit counter (both 8TCNT2 and 8TCNT3) is cleared. * The settings of the CCLR1 and CCLR0 bits in 8TCR3 are ignored. The lower 8 bits cannot be cleared independently. OVF Flag Operation * The OVF flag is set to 1 in 8TCSR2 when the 16-bit counter (8TCNT2 and 8TCNT3) overflows (from H'FFFF to H'0000). * The OVF flag is set to 1 in 8TCSR3 when the 8-bit counter (8TCNT3) overflows (from H'FF to H'00). Compare Match Count Mode * Channels 0 and 1: When bits CKS2 to CKS0 are set to (100) in 8TCR1, 8TCNT1 counts channel 0 compare match A events. CMF flag setting, interrupt generation, TMO pin output, counter clearing, and so on, is in accordance with the settings for each channel. Note: When bit ICE = 1 in 8TCSR1, the compare match register function of TCORB0 in channel 0 cannot be used. * Channels 2 and 3: When bits CKS2 to CKS0 are set to (100) in 8TCR3, 8TCNT3 counts channel 2 compare match A events. CMF flag setting, interrupt generation, TMO pin output, counter clearing, and so on, is in accordance with the settings for each channel. Caution Do not set 16-bit counter mode and compare match count mode simultaneously within the same group, as the 8TCNT input clock will not be generated and the counters will not operate. Rev. 2.0, 06/04, page 401 of 980 10.4.6 Input Capture Setting The 8TCNT value can be transferred to TCORB on detection of an input edge on the input capture/output compare pin (TMIO1 or TMIO3). Rising edge, falling edge, or both edge detection can be selected. In 16-bit count mode, 16-bit input capture can be used. Setting Input Capture Operation in 8-Bit Timer Mode (Normal Operation) * Channel 1: Set TCORB1 as an 8-bit input capture register with the ICE bit in 8TCSR1. Select rising edge, falling edge, or both edges as the input edge(s) for the input capture signal (TMIO1) with bits OIS3 and OIS2 in 8TCSR1. Select the input clock with bits CKS2 to CKS0 in 8TCR1, and start the 8TCNT count. * Channel 3: Set TCORB3 as an 8-bit input capture register with the ICE bit in 8TCSR3. Select rising edge, falling edge, or both edges as the input edge(s) for the input capture signal (TMIO3) with bits OIS3 and OIS2 in 8TCSR3. Select the input clock with bits CKS2 to CKS0 in 8TCR3, and start the 8TCNT count. Note: When TCORB1 in channel 1 is used for input capture, TCORB0 in channel 0 cannot be used as a compare match register. Similarly, when TCORB3 in channel 3 is used for input capture, TCORB2 in channel 2 cannot be used as a compare match register. Setting Input Capture Operation in 16-Bit Count Mode * Channels 0 and 1: In 16-bit count mode, TCORB0 and TCORB1 function as a 16-bit input capture register when the ICE bit is set to 1 in 8TCSR1. Select rising edge, falling edge, or both edges as the input edge(s) for the input capture signal (TMIO1) with bits OIS3 and OIS2 in 8TCSR0. (In 16-bit count mode, the settings of bits OIS3 and OIS2 in 8TCSR1 are ignored.) Select the input clock with bits CKS2 to CKS0 in 8TCR1, and start the 8TCNT count. * Channels 2 and 3: In 16-bit count mode, TCORB2 and TCORB3 function as a 16-bit input capture register when the ICE bit is set to 1 in 8TCSR3. Select rising edge, falling edge, or both edges as the input edge(s) for the input capture signal (TMIO3) with bits OIS3 and OIS2 in 8TCSR2. (In 16-bit count mode, the settings of bits OIS3 and OIS2 in 8TCSR3 are ignored.) Select the input clock with bits CKS2 to CKS0 in 8TCR3, and start the 8TCNT count. Rev. 2.0, 06/04, page 402 of 980 10.5 10.5.1 Interrupt Interrupt Sources The 8-bit timer unit can generate three types of interrupt: compare match A and B (CMIA and CMIB) and overflow (TOVI). Table 10.5 shows the interrupt sources and their priority order. Each interrupt source is enabled or disabled by the corresponding interrupt enable bit in 8TCR. A separate interrupt request signal is sent to the interrupt controller by each interrupt source. Table 10.5 Types of 8-Bit Timer Interrupt Sources and Priority Order Interrupt Source CMIA CMIB TOVI Description Interrupt by CMFA Interrupt by CMFB Interrupt by OVF Low Priority High For compare match interrupts (CMIA1/CMIB1 and CMIA3/CMIB3) and the overflow interrupts (TOVI0/TOVI1 and TOVI2/TOVI3), one vector is shared by two interrupts. Table 10.6 lists the interrupt sources. Table 10.6 8-Bit Timer Interrupt Sources Channel 0 1 0, 1 2 3 2, 3 Interrupt Source CMIA0 CMIB0 CMIA1/CMIB1 TOVI0/TOVI1 CMIA2 CMIB2 CMIA3/CMIB3 TOVI2/TOVI3 Description TCORA0 compare match TCORB0 compare match/input capture TCORA1 compare match, or TCORB1 compare match/input capture Counter 0 or counter 1 overflow TCORA2 compare match TCORB2 compare match/input capture TCORA3 compare match, or TCORB3 compare match/input capture Counter 2 or counter 3 overflow Rev. 2.0, 06/04, page 403 of 980 10.5.2 A/D Converter Activation The A/D converter can only be activated by channel 0 compare match A. If the ADTE bit setting is 1 when the CMFA flag in 8TCSR0 is set to 1 by generation of channel 0 compare match A, an A/D conversion start request will be issued to the A/D converter. If the TRGE bit in ADCR is 1 at this time, the A/D converter will be started. If the ADTE bit in 8TCSR0 is 1, A/D converter external trigger pin (ADTRG) input is disabled. 10.6 8-Bit Timer Application Example Figure 10.17 shows how the 8-bit timer module can be used to output pulses with any desired duty cycle. The settings for this example are as follows: * Clear the CCLR1 bit to 0 and set the CCLR0 bit to 1 in 8TCR so that 8TCNT is cleared by a TCORA compare match. * Set bits OIS3, OIS2, OS1, and OS0 to (0110) in 8TCSR so that 1 is output on a TCORA compare match and 0 is output on a TCORB compare match. The above settings enable a waveform with the cycle determined by TCORA and the pulse width detected by TCORB to be output without software intervention. 8TCNT H'FF TCORA TCORB H'00 Counter clear TMO Figure 10.17 Example of Pulse Output Rev. 2.0, 06/04, page 404 of 980 10.7 Usage Notes Note that the following kinds of contention can occur in 8-bit timer operation. 10.7.1 Contention between 8TCNT Write and Clear If a timer counter clear signal occurs in the T3 state of a 8TCNT write cycle, clearing of the counter takes priority and the write is not performed. Figure 10.18 shows the timing in this case. 8TCNT write cycle T1 T2 T3 Address bus 8TCNT address Internal write signal Counter clear signal 8TCNT N H'00 Figure 10.18 Contention between 8TCNT Write and Clear Rev. 2.0, 06/04, page 405 of 980 10.7.2 Contention between 8TCNT Write and Increment If an increment pulse occurs in the T3 state of a 8TCNT write cycle, writing takes priority and 8TCNT is not incremented. Figure 10.19 shows the timing in this case. 8TCNT write cycle T1 T2 T3 Address bus 8 TCNT address Internal write signal 8TCNT input clock 8TCNT N 8TCNT write data M Figure 10.19 Contention between 8TCNT Write and Increment Rev. 2.0, 06/04, page 406 of 980 10.7.3 Contention between TCOR Write and Compare Match If a compare match occurs in the T3 state of a TCOR write cycle, writing takes priority and the compare match signal is inhibited. Figure 10.20 shows the timing in this case. TCOR write cycle T1 T2 T3 Address bus TCOR address Internal write signal 8TCNT N N+1 TCOR N TCOR write data M Compare match signal Inhibited Figure 10.20 Contention between TCOR Write and Compare Match Rev. 2.0, 06/04, page 407 of 980 10.7.4 Contention between TCOR Read and Input Capture If an input capture signal occurs in the T3 state of a TCOR read cycle, the value before input capture is read. Figure 10.21 shows the timing in this case. TCORB read cycle T1 T2 T3 Address bus TCORB address Internal read signal Input capture signal TCORB N M Internal data bus N Figure 10.21 Contention between TCOR Read and Input Capture Rev. 2.0, 06/04, page 408 of 980 10.7.5 Contention between Counter Clearing by Input Capture and Counter Increment If an input capture signal and counter increment signal occur simultaneously, counter clearing by the input capture signal takes priority and the counter is not incremented. The value before the counter is cleared is transferred to TCORB. Figure 10.22 shows the timing in this case. T1 T2 T3 Input capture signal Counter clear signal 8TCNT internal clock 8TCNT N H'00 TCORB X N Figure 10.22 Contention between Counter Clearing by Input Capture and Counter Increment Rev. 2.0, 06/04, page 409 of 980 10.7.6 Contention between TCOR Write and Input Capture If an input capture signal occurs in the T3 state of a TCOR write cycle, input capture takes priority and the write to TCOR is not performed. Figure 10.23 shows the timing in this case. TCOR write cycle T1 T2 T3 Address bus TCOR address Internal write signal Input capture signal 8TCNT M TCOR X M Figure 10.23 Contention between TCOR Write and Input Capture Rev. 2.0, 06/04, page 410 of 980 10.7.7 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode (Cascaded Connection) If an increment pulse occurs in the T3 state of an 8TCNT byte write cycle in 16-bit count mode, the counter write takes priority and the byte data for which the write was performed is not incremented. The byte data for which a write was not performed is incremented. Figure 10.24 shows the timing when an increment pulse occurs in the T2 state of a byte write to 8TCNT (upper byte). If an increment pulse occurs in the T2 state, on the other hand, the increment takes priority. 8TCNT (upper byte) byte write cycle T1 T2 T3 Address bus 8TCNTH address Internal write signal 8TCNT input clock 8TCNT (upper byte) N N+1 8TCNT write data 8TCNT (lower byte) X X+1 Figure 10.24 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode Rev. 2.0, 06/04, page 411 of 980 10.7.8 Contention between Compare Matches A and B If compare matches A and B occur at the same time, the 8-bit timer operates according to the relative priority of the output states set for compare match A and compare match B, as shown in Table 10.7. Table 10.7 Timer Output Priority Order Output Setting Toggle output 1 output 0 output No change Low Priority High 10.7.9 8TCNT Operation and Internal Clock Source Switchover Switching internal clock sources may cause 8TCNT to increment, depending on the switchover timing. Table 10.8 shows the relation between the time of the switchover (by writing to bits CKS1 and CKS0) and the operation of 8TCNT. The 8TCNT input clock is generated from the internal clock source by detecting the rising edge of the internal clock. If a switchover is made from a low clock source to a high clock source, as in case No. 3 in Table 10.8, the switchover will be regarded as a falling edge, a 8TCNT clock pulse will be generated, and 8TCNT will be incremented. 8TCNT may also be incremented when switching between internal and external clocks. Rev. 2.0, 06/04, page 412 of 980 Table 10.8 Internal Clock Switchover and 8TCNT Operation No. 1 CKS1 and CKS0 Write Timing High high switchover* 1 8TCNT Operation Old clock source New clock source 8TCNT clock 8TCNT N CKS bits rewritten N+1 2 High low switchover* 2 Old clock source New clock source 8TCNT clock 8TCNT N N+1 N+2 CKS bits rewritten 3 Low high switchover* 3 Old clock source New clock source *4 8TCNT clock 8TCNT N N+1 CKS bits rewritten N+2 Rev. 2.0, 06/04, page 413 of 980 No. 4 CKS1 and CKS0 Write Timing Low low switchover* 4 8TCNT Operation Old clock source New clock source 8TCNT clock 8TCNT N N+1 N+2 CKS bits rewritten Notes: *1 Including switchovers from the high level to the halted state, and from the halted state to the high level. *2 Including switchover from the halted state to the low level. *3 Including switchover from the low level to the halted state. *4 The switchover is regarded as a rising edge, causing 8TCNT to increment. Rev. 2.0, 06/04, page 414 of 980 Section 11 Programmable Timing Pattern Controller (TPC) 11.1 Overview The H8/3029 has a built-in programmable timing pattern controller (TPC) that provides pulse outputs by using the 16-bit timer as a time base. The TPC pulse outputs are divided into 4-bit groups (group 3 to group 0) that can operate simultaneously and independently. 11.1.1 Features TPC features are listed below. * 16-bit output data Maximum 16-bit data can be output. TPC output can be enabled on a bit-by-bit basis. * Four output groups Output trigger signals can be selected in 4-bit groups to provide up to four different 4-bit outputs. * Selectable output trigger signals Output trigger signals can be selected for each group from the compare match signals of three 16-bit timer channels. * Non-overlap mode A non-overlap margin can be provided between pulse outputs. * Can operate together with the DMA controller (DMAC) The compare-match signals selected as trigger signals can activate the DMAC for sequential output of data without CPU intervention. Rev. 2.0, 06/04, page 415 of 980 11.1.2 Block Diagram Figure 11.1 shows a block diagram of the TPC. 16-bit timer compare match signals PADDR Control logic NDERA TPMR PBDDR NDERB TPCR TP15 TP14 TP13 TP12 TP11 TP10 TP 9 TP 8 TP 7 TP 6 TP 5 TP 4 TP 3 TP 2 TP 1 TP 0 Legend TPMR: TPCR: NDERB: NDERA: PBDDR: PADDR: NDRB: NDRA: PBDR: PADR: Pulse output pins, group 3 PBDR Pulse output pins, group 2 NDRB Internal data bus Pulse output pins, group 1 PADR Pulse output pins, group 0 NDRA TPC output mode register TPC output control register Next data enable register B Next data enable register A Port B data direction register Port A data direction register Next data register B Next data register A Port B data register Port A data register Figure 11.1 TPC Block Diagram Rev. 2.0, 06/04, page 416 of 980 11.1.3 TPC Pins Table 11.1 summarizes the TPC output pins. Table 11.1 TPC Pins Name TPC output 0 TPC output 1 TPC output 2 TPC output 3 TPC output 4 TPC output 5 TPC output 6 TPC output 7 TPC output 8 TPC output 9 TPC output 10 TPC output 11 TPC output 12 TPC output 13 TPC output 14 TPC output 15 Symbol TP0 TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 I/O Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Group 3 pulse output Group 2 pulse output Group 1 pulse output Function Group 0 pulse output Rev. 2.0, 06/04, page 417 of 980 11.1.4 Registers Table 11.2 summarizes the TPC registers. Table 11.2 TPC Registers Address* H'EE009 H'FFFD9 H'EE00A H'FFFDA H'FFFA0 H'FFFA1 H'FFFA2 H'FFFA3 H'FFFA5/ 3 H'FFFA7* H'FFFA4/ 3 H'FFFA6* 1 Name Port A data direction register Port A data register Port B data direction register Port B data register TPC output mode register TPC output control register Next data enable register B Next data enable register A Next data register A Next data register B Abbreviation PADDR PADR PBDDR PBDR TPMR TPCR NDERB NDERA NDRA NDRB R/W W R/(W)* W R/(W)* R/W R/W R/W R/W R/W R/W 2 2 Function H'00 H'00 H'00 H'00 H'F0 H'FF H'00 H'00 H'00 H'00 Notes: *1 Lower 20 bits of the address in advanced mode. *2 Bits used for TPC output cannot be written. *3 The NDRA address is H'FFFA5 when the same output trigger is selected for TPC output groups 0 and 1 by settings in TPCR. When the output triggers are different, the NDRA address is H'FFFA7 for group 0 and H'FFFA5 for group 1. Similarly, the address of NDRB is H'FFFA4 when the same output trigger is selected for TPC output groups 2 and 3 by settings in TPCR. When the output triggers are different, the NDRB address is H'FFFA6 for group 2 and H'FFFA4 for group 3. Rev. 2.0, 06/04, page 418 of 980 11.2 11.2.1 Register Descriptions Port A Data Direction Register (PADDR) PADDR is an 8-bit write-only register that selects input or output for each pin in port A. Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W PA 7 DDR PA 6 DDR PA 5 DDR PA 4 DDR PA 3 DDR PA 2 DDR PA 1 DDR PA 0 DDR Port A data direction 7 to 0 These bits select input or output for port A pins Port A is multiplexed with pins TP7 to TP0. Bits corresponding to pins used for TPC output must be set to 1. For further information about PADDR, see section 8.11, Port A. 11.2.2 Port A Data Register (PADR) PADR is an 8-bit readable/writable register that stores TPC output data for groups 0 and 1, when these TPC output groups are used. Bit Initial value Read/Write 7 PA 7 0 R/(W) * 6 PA 6 0 R/(W) * 5 PA 5 0 R/(W) * 4 PA 4 0 R/(W) * 3 PA 3 0 R/(W) * 2 PA 2 0 R/(W) * 1 PA 1 0 R/(W) * 0 PA 0 0 R/(W) * Port A data 7 to 0 These bits store output data for TPC output groups 0 and 1 Note: * Bits selected for TPC output by NDERA settings become read-only bits. For further information about PADR, see section 8.11, Port A. Rev. 2.0, 06/04, page 419 of 980 11.2.3 Port B Data Direction Register (PBDDR) PBDDR is an 8-bit write-only register that selects input or output for each pin in port B. Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Port B direction 7 to 0 These bits select input or output for port B pins Port B is multiplexed with pins TP15 to TP8. Bits corresponding to pins used for TPC output must be set to 1. For further information about PBDDR, see section 8.12, Port B. 11.2.4 Port B Data Register (PBDR) PBDR is an 8-bit readable/writable register that stores TPC output data for groups 2 and 3, when these TPC output groups are used. Bit Initial value Read/Write 7 PB7 0 R/(W)* 6 PB6 0 R/(W)* 5 PB5 0 R/(W)* 4 PB4 0 R/(W)* 3 PB3 0 R/(W)* 2 PB2 0 R/(W)* 1 PB1 0 R/(W)* 0 PB0 0 R/(W)* Port B data 7 to 0 These bits store output data for TPC output groups 2 and 3 Note: * Bits selected for TPC output by NDERB settings become read-only bits. For further information about PBDR, see section 8.12, Port B. Rev. 2.0, 06/04, page 420 of 980 11.2.5 Next Data Register A (NDRA) NDRA is an 8-bit readable/writable register that stores the next output data for TPC output groups 1 and 0 (pins TP7 to TP0). During TPC output, when an 16-bit timer compare match event specified in TPCR occurs, NDRA contents are transferred to the corresponding bits in PADR. The address of NDRA differs depending on whether TPC output groups 0 and 1 have the same output trigger or different output triggers. NDRA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Same Trigger for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered by the same compare match event, the NDRA address is H'FFFA5. The upper 4 bits belong to group 1 and the lower 4 bits to group 0. Address H'FFFA7 consists entirely of reserved bits that cannot be modified and always read 1. Address H'FFFA5 Bit Initial value Read/Write 7 NDR7 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W Next data 7 to 4 These bits store the next output data for TPC output group 1 Next data 3 to 0 These bits store the next output data for TPC output group 0 Address H'FFFA7 Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Reserved bits Rev. 2.0, 06/04, page 421 of 980 Different Triggers for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered by different compare match events, the address of the upper 4 bits of NDRA (group 1) is H'FFFA5 and the address of the lower 4 bits (group 0) is H'FFFA7. Bits 3 to 0 of address H'FFFA5 and bits 7 to 4 of address H'FFFA7 are reserved bits that cannot be modified and always read 1. Address H'FFFA5 Bit Initial value Read/Write 7 NDR7 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Next data 7 to 4 These bits store the next output data for TPC output group 1 Reserved bits Address H'FFFA7 Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W Reserved bits Next data 3 to 0 These bits store the next output data for TPC output group 0 Rev. 2.0, 06/04, page 422 of 980 11.2.6 Next Data Register B (NDRB) NDRB is an 8-bit readable/writable register that stores the next output data for TPC output groups 3 and 2 (pins TP15 to TP8). During TPC output, when an 16-bit timer compare match event specified in TPCR occurs, NDRB contents are transferred to the corresponding bits in PBDR. The address of NDRB differs depending on whether TPC output groups 2 and 3 have the same output trigger or different output triggers. NDRB is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Same Trigger for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are triggered by the same compare match event, the NDRB address is H'FFFA4. The upper 4 bits belong to group 3 and the lower 4 bits to group 2. Address H'FFFA6 consists entirely of reserved bits that cannot be modified and always read 1. Address H'FFFA4 Bit Initial value Read/Write 7 NDR15 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W 3 NDR11 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W Next data 15 to 12 These bits store the next output data for TPC output group 3 Next data 11 to 8 These bits store the next output data for TPC output group 2 Address H'FFFA6 Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Reserved bits Rev. 2.0, 06/04, page 423 of 980 Different Triggers for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are triggered by different compare match events, the address of the upper 4 bits of NDRB (group 3) is H'FFFA4 and the address of the lower 4 bits (group 2) is H'FFFA6. Bits 3 to 0 of address H'FFFA4 and bits 7 to 4 of address H'FFFA6 are reserved bits that cannot be modified and always read 1. Address H'FFFA4 Bit Initial value Read/Write 7 NDR15 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Next data 15 to 12 These bits store the next output data for TPC output group 3 Reserved bits Address H'FFFA6 Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 NDR11 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W Reserved bits Next data 11 to 8 These bits store the next output data for TPC output group 2 Rev. 2.0, 06/04, page 424 of 980 11.2.7 Next Data Enable Register A (NDERA) NDERA is an 8-bit readable/writable register that enables or disables TPC output groups 1 and 0 (TP7 to TP0) on a bit-by-bit basis. Bit Initial value Read/Write 7 NDER7 0 R/W 6 NDER6 0 R/W 5 NDER5 0 R/W 4 NDER4 0 R/W 3 NDER3 0 R/W 2 NDER2 0 R/W 1 NDER1 0 R/W 0 NDER0 0 R/W Next data enable 7 to 0 These bits enable or disable TPC output groups 1 and 0 If a bit is enabled for TPC output by NDERA, then when the 16-bit timer compare match event selected in the TPC output control register (TPCR) occurs, the NDRA value is automatically transferred to the corresponding PADR bit, updating the output value. If TPC output is disabled, the bit value is not transferred from NDRA to PADR and the output value does not change. NDERA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 0--Next Data Enable 7 to 0 (NDER7 to NDER0): These bits enable or disable TPC output groups 1 and 0 (TP7 to TP0) on a bit-by-bit basis. Bits 7 to 0 NDER7 to NDER0 0 1 Description TPC outputs TP7 to TP0 are disabled (NDR7 to NDR0 are not transferred to PA7 to PA0) TPC outputs TP7 to TP0 are enabled (NDR7 to NDR0 are transferred to PA7 to PA0) (Initial value) Rev. 2.0, 06/04, page 425 of 980 11.2.8 Next Data Enable Register B (NDERB) NDERB is an 8-bit readable/writable register that enables or disables TPC output groups 3 and 2 (TP15 to TP8) on a bit-by-bit basis. Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 NDER8 0 R/W NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 Next data enable 15 to 8 These bits enable or disable TPC output groups 3 and 2 If a bit is enabled for TPC output by NDERB, then when the 16-bit timer compare match event selected in the TPC output control register (TPCR) occurs, the NDRB value is automatically transferred to the corresponding PBDR bit, updating the output value. If TPC output is disabled, the bit value is not transferred from NDRB to PBDR and the output value does not change. NDERB is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 0--Next Data Enable 15 to 8 (NDER15 to NDER8): These bits enable or disable TPC output groups 3 and 2 (TP15 to TP8) on a bit-by-bit basis. Bits 7 to 0 NDER15 to NDER8 0 1 Description TPC outputs TP15 to TP8 are disabled (NDR15 to NDR8 are not transferred to PB7 to PB0) TPC outputs TP15 to TP8 are enabled (NDR15 to NDR8 are transferred to PB7 to PB0) (Initial value) Rev. 2.0, 06/04, page 426 of 980 11.2.9 TPC Output Control Register (TPCR) TPCR is an 8-bit readable/writable register that selects output trigger signals for TPC outputs on a group-by-group basis. Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Group 3 compare match select 1 and 0 These bits select the compare match Group 2 compare event that triggers match select 1 and 0 TPC output group 3 These bits select (TP15 to TP12) the compare match Group 1 compare event that triggers TPC output group 2 match select 1 and 0 These bits select (TP11 to TP8) the compare match Group 0 compare event that triggers match select 1 and 0 TPC output group 1 These bits select (TP7 to TP4) the compare match event that triggers TPC output group 0 (TP3 to TP0) TPCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software standby mode. Rev. 2.0, 06/04, page 427 of 980 Bits 7 and 6--Group 3 Compare Match Select 1 and 0 (G3CMS1, G3CMS0): These bits select the compare match event that triggers TPC output group 3 (TP15 to TP12). Bit 7 G3CMS1 0 Bit 6 G3CMS0 0 1 1 0 1 Description TPC output group 3 (TP15 to TP12) is triggered by compare match in 16-bit timer channel 0 TPC output group 3 (TP15 to TP12) is triggered by compare match in 16-bit timer channel 1 TPC output group 3 (TP15 to TP12) is triggered by compare match in 16-bit timer channel 2 TPC output group 3 (TP15 to TP12) is triggered by compare match in 16-bit timer channel 2 (Initial value) Bits 5 and 4--Group 2 Compare Match Select 1 and 0 (G2CMS1, G2CMS0): These bits select the compare match event that triggers TPC output group 2 (TP11 to TP8). Bit 5 G2CMS1 0 Bit 4 G2CMS0 0 1 1 0 1 Description TPC output group 2 (TP11 to TP8) is triggered by compare match in 16-bit timer channel 0 TPC output group 2 (TP11 to TP8) is triggered by compare match in 16-bit timer channel 1 TPC output group 2 (TP11 to TP8) is triggered by compare match in 16-bit timer channel 2 TPC output group 2 (TP11 to TP8) is triggered by compare match in 16-bit timer channel 2 (Initial value) Rev. 2.0, 06/04, page 428 of 980 Bits 3 and 2--Group 1 Compare Match Select 1 and 0 (G1CMS1, G1CMS0): These bits select the compare match event that triggers TPC output group 1 (TP7 to TP4). Bit 3 G1CMS1 0 Bit 2 G1CMS0 0 1 1 0 1 Description TPC output group 1 (TP7 to TP4) is triggered by compare match in 16-bit timer channel 0 TPC output group 1 (TP7 to TP4) is triggered by compare match in 16-bit timer channel 1 TPC output group 1 (TP7 to TP4) is triggered by compare match in 16-bit timer channel 2 TPC output group 1 (TP7 to TP4) is triggered by compare match in 16-bit timer channel 2 (Initial value) Bits 1 and 0--Group 0 Compare Match Select 1 and 0 (G0CMS1, G0CMS0): These bits select the compare match event that triggers TPC output group 0 (TP3 to TP0). Bit 1 G0CMS1 0 Bit 0 G0CMS0 0 1 1 0 1 Description TPC output group 0 (TP3 to TP0) is triggered by compare match in 16-bit timer channel 0 TPC output group 0 (TP3 to TP0) is triggered by compare match in 16-bit timer channel 1 TPC output group 0 (TP3 to TP0) is triggered by compare match in 16-bit timer channel 2 TPC output group 0 (TP3 to TP0) is triggered by compare match in 16-bit timer channel 2 (Initial value) Rev. 2.0, 06/04, page 429 of 980 11.2.10 TPC Output Mode Register (TPMR) TPMR is an 8-bit readable/writable register that selects normal or non-overlapping TPC output for each group. Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W G3NOV G2NOV G1NOV G0NOV Reserved bits Group 3 non-overlap Selects non-overlapping TPC output for group 3 (TP15 to TP12) Group 2 non-overlap Selects non-overlapping TPC output for group 2 (TP11 to TP8 ) Group 1 non-overlap Selects non-overlapping TPC output for group 1 (TP7 to TP4 ) Group 0 non-overlap Selects non-overlapping TPC output for group 0 (TP3 to TP0 ) The output trigger period of a non-overlapping TPC output waveform is set in general register B (GRB) in the 16-bit timer channel selected for output triggering. The non-overlap margin is set in general register A (GRA). The output values change at compare match A and B. For details see section 11.3.4, Non-Overlapping TPC Output. TPMR is initialized to H'F0 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 4--Reserved: These bits cannot be modified and are always read as 1. Rev. 2.0, 06/04, page 430 of 980 Bit 3--Group 3 Non-Overlap (G3NOV): Selects normal or non-overlapping TPC output for group 3 (TP15 to TP12). Bit 3 G3NOV 0 1 Description Normal TPC output in group 3 (output values change at compare match A in the selected 16-bit timer channel) Non-overlapping TPC output in group 3 (independent 1 and 0 output at compare match A and B in the selected 16-bit timer channel) (Initial value) Bit 2--Group 2 Non-Overlap (G2NOV): Selects normal or non-overlapping TPC output for group 2 (TP11 to TP8). Bit 2 G2NOV 0 1 Description Normal TPC output in group 2 (output values change at compare match A in the selected 16-bit timer channel) Non-overlapping TPC output in group 2 (independent 1 and 0 output at compare match A and B in the selected 16-bit timer channel) (Initial value) Bit 1--Group 1 Non-Overlap (G1NOV): Selects normal or non-overlapping TPC output for group 1 (TP7 to TP4). Bit 1 G1NOV 0 1 Description Normal TPC output in group 1 (output values change at compare match A in the selected 16-bit timer channel) Non-overlapping TPC output in group 1 (independent 1 and 0 output at compare match A and B in the selected 16-bit timer channel) (Initial value) Bit 0--Group 0 Non-Overlap (G0NOV): Selects normal or non-overlapping TPC output for group 0 (TP3 to TP0). Bit 0 G0NOV 0 1 Description Normal TPC output in group 0 (output values change at compare match A in the selected 16-bit timer channel) Non-overlapping TPC output in group 0 (independent 1 and 0 output at compare match A and B in the selected 16-bit timer channel) (Initial value) Rev. 2.0, 06/04, page 431 of 980 11.3 11.3.1 Operation Overview When corresponding bits in PADDR or PBDDR and NDERA or NDERB are set to 1, TPC output is enabled. The TPC output initially consists of the corresponding PADR or PBDR contents. When a compare-match event selected in TPCR occurs, the corresponding NDRA or NDRB bit contents are transferred to PADR or PBDR to update the output values. Figure 11.2 illustrates the TPC output operation. Table 11.3 summarizes the TPC operating conditions. DDR Q NDER Q Output trigger signal C Q TPC output pin DR D Q NDR D Internal data bus Figure 11.2 TPC Output Operation Table 11.3 TPC Operating Conditions NDER 0 DDR 0 1 1 0 1 Pin Function Generic input port Generic output port Generic input port (but the DR bit is a read-only bit, and when compare match occurs, the NDR bit value is transferred to the DR bit) TPC pulse output Sequential output of up to 16-bit patterns is possible by writing new output data to NDRA and NDRB before the next compare match. For information on non-overlapping operation, see section 11.3.4, Non-Overlapping TPC Output. Rev. 2.0, 06/04, page 432 of 980 11.3.2 Output Timing If TPC output is enabled, NDRA/NDRB contents are transferred to PADR/PBDR and output when the selected compare match event occurs. Figure 11.3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A. TCNT N N+1 GRA Compare match A signal N NDRB n PBDR TP8 to TP15 m m n n Figure 11.3 Timing of Transfer of Next Data Register Contents and Output (Example) Rev. 2.0, 06/04, page 433 of 980 11.3.3 Normal TPC Output Sample Setup Procedure for Normal TPC Output: Figure 11.4 shows a sample procedure for setting up normal TPC output. Normal TPC output Select GR functions Set GRA value Select counting operation Select interrupt request 1 2 3 4 1. 16-bit timer setup Set initial output data Select port output Port and TPC setup Enable TPC output Select TPC output trigger Set next TPC output data 16-bit timer setup 5 6 7 8 9 Start counter 10 Set TIOR to make GRA an output compare register (with output inhibited). 2. Set the TPC output trigger period. 3. Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR1 and CCLR0. 4. Enable the IMFA interrupt in TISRA. The DMAC can also be set up to transfer data to the next data register. 5. Set the initial output values in the DR bits of the input/output port pins to be used for TPC output. 6. Set the DDR bits of the input/output port pins to be used for TPC output to 1. 7. Set the NDER bits of the pins to be used for TPC output to 1. 8. Select the 16-bit timer compare match event to be used as the TPC output trigger in TPCR. 9. Set the next TPC output values in the NDR bits. 10. Set the STR bit to 1 in TSTR to start the timer counter. 11. At each IMFA interrupt, set the next output values in the NDR bits. Compare match? Yes Set next TPC output data No 11 Figure 11.4 Setup Procedure for Normal TPC Output (Example) Rev. 2.0, 06/04, page 434 of 980 Example of Normal TPC Output (Example of Five-Phase Pulse Output): Figure 11.5 shows an example in which the TPC is used for cyclic five-phase pulse output. TCNT value TCNT GRA Compare match H'0000 NDRB 80 C0 40 60 20 30 10 18 08 88 80 C0 40 Time PBDR 00 80 C0 40 60 20 30 10 18 08 88 80 C0 TP15 TP14 TP13 TP12 TP11 * * * * The 16-bit timer channel to be used as the output trigger channel is set up so that GRA is an output compare register and the counter will be cleared by compare match A. The trigger period is set in GRA. The IMIEA bit is set to 1 in TISRA to enable the compare match A interrupt. H'F8 is written in PBDDR and NDERB, and bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 are set in TPCR to select compare match in the 16-bit timer channel set up in step 1 as the output trigger. Output data H'80 is written in NDRB. The timer counter in this 16-bit timer channel is started. When compare match A occurs, the NDRB contents are transferred to PBDR and output. The compare match/input capture A (IMFA) interrupt service routine writes the next output data (H'C0) in NDRB. Five-phase overlapping pulse output (one or two phases active at a time) can be obtained by writing H'40, H'60, H'20, H'30, H'10, H'18, H'08, H'88... at successive IMFA interrupts. If the DMAC is set for activation by this interrupt, pulse output can be obtained without loading the CPU. Figure 11.5 Normal TPC Output Example (Five-Phase Pulse Output) Rev. 2.0, 06/04, page 435 of 980 11.3.4 Non-Overlapping TPC Output Sample Setup Procedure for Non-Overlapping TPC Output: Figure 11.6 shows a sample procedure for setting up non-overlapping TPC output. Non-overlapping TPC output Select GR functions Set GR values Select counting operation Select interrupt requests 1 2 3 4 1. Set TIOR to make GRA and GRB output compare registers (with output inhibited). 2. Set the TPC output trigger period in GRB and the non-overlap margin in GRA. 3. Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR1 and CCLR0. 4. Enable the IMFA interrupt in TISRA. The DMAC can also be set up to transfer data to the next data register. 5. Set the initial output values in the DR bits of the input/output port pins to be used for TPC output. 6. Set the DDR bits of the input/output port pins to be used for TPC output to 1. 7. Set the NDER bits of the pins to be used for TPC output to 1. 8. In TPCR, select the 16-bit timer compare match event to be used as the TPC output trigger. 9. In TPMR, select the groups that will operate in non-overlap mode. 10. Set the next TPC output values in the NDR bits. 11. Set the STR bit to 1 in TSTR to start the timer counter. 12. At each IMFA interrupt, write the next output value in the NDR bits. 16-bit timer setup Set initial output data Set up TPC output Enable TPC transfer Port and TPC setup Select TPC transfer trigger Select non-overlapping groups Set next TPC output data 5 6 7 8 9 10 16-bit timer setup Start counter 11 Compare match A? Yes Set next TPC output data No 12 Figure 11.6 Setup Procedure for Non-Overlapping TPC Output (Example) Rev. 2.0, 06/04, page 436 of 980 Example of Non-Overlapping TPC Output (Example of Four-Phase Complementary NonOverlapping Output): Figure 11.7 shows an example of the use of TPC output for four-phase complementary non-overlapping pulse output. TCNT value GRB GRA H'0000 NDRB 95 65 59 56 95 65 Time TCNT PBDR 00 95 05 65 41 59 50 56 14 95 05 65 Non-overlap margin TP15 TP14 TP13 TP12 TP11 TP10 TP9 TP8 * The 16-bit timer channel to be used as the output trigger channel is set up so that GRA and GRB are output compare registers and the counter will be cleared by compare match B. The TPC output trigger period is set in GRB. The non-overlap margin is set in GRA. The IMIEA bit is set to 1 in TISRA to enable IMFA interrupts. * H'FF is written in PBDDR and NDERB, and bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 are set in TPCR to select compare match in the 16-bit timer channel set up in step 1 as the output trigger. Bits G3NOV and G2NOV are set to 1 in TPMR to select non-overlapping output. Output data H'95 is written in NDRB. * The timer counter in this 16-bit timer channel is started. When compare match B occurs, outputs change from 1 to 0. When compare match A occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed by the value of GRA). The IMFA interrupt service routine writes the next output data (H'65) in NDRB. * Four-phase complementary non-overlapping pulse output can be obtained by writing H'59, H'56, H'95... at successive IMFA interrupts. If the DMAC is set for activation by this interrupt, pulse output can be obtained without loading the CPU. Figure 11.7 Non-Overlapping TPC Output Example (Four-Phase Complementary Non-Overlapping Pulse Output) Rev. 2.0, 06/04, page 437 of 980 11.3.5 TPC Output Triggering by Input Capture TPC output can be triggered by 16-bit timer input capture as well as by compare match. If GRA functions as an input capture register in the 16-bit timer channel selected in TPCR, TPC output will be triggered by the input capture signal. Figure 11.8 shows the timing. TIOC pin Input capture signal NDR N DR M N Figure 11.8 TPC Output Triggering by Input Capture (Example) Rev. 2.0, 06/04, page 438 of 980 11.4 11.4.1 Usage Notes Operation of TPC Output Pins TP0 to TP15 are multiplexed with 16-bit timer, DMAC, address bus, and other pin functions. When 16-bit timer, DMAC, or address output is enabled, the corresponding pins cannot be used for TPC output. The data transfer from NDR bits to DR bits takes place, however, regardless of the usage of the pin. Pin functions should be changed only under conditions in which the output trigger event will not occur. 11.4.2 Note on Non-Overlapping Output During non-overlapping operation, the transfer of NDR bit values to DR bits takes place as follows. 1. NDR bits are always transferred to DR bits at compare match A. 2. At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred if their value is 1. Figure 11.9 illustrates the non-overlapping TPC output operation. DDR Q NDER Q Compare match A Compare match B C Q TPC output pin DR D Q NDR D Figure 11.9 Non-Overlapping TPC Output Rev. 2.0, 06/04, page 439 of 980 Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before compare match A. NDR contents should not be altered during the interval from compare match B to compare match A (the non-overlap margin). This can be accomplished by having the IMFA interrupt service routine write the next data in NDR, or by having the IMFA interrupt activate the DMAC. The next data must be written before the next compare match B occurs. Figure 11.10 shows the timing relationships. Compare match A Compare match B NDR write NDR write NDR DR 0 output 0/1 output Write to NDR in this interval Do not write to NDR in this interval Do not write to NDR in this interval 0 output 0/1 output Write to NDR in this interval Figure 11.10 Non-Overlapping Operation and NDR Write Timing Rev. 2.0, 06/04, page 440 of 980 Section 12 Watchdog Timer 12.1 Overview The H8/3029 has an on-chip watchdog timer (WDT). The WDT has two selectable functions: it can operate as a watchdog timer to supervise system operation, or it can operate as an interval timer. As a watchdog timer, it generates a reset signal for the H8/3029 chip if a system crash allows the timer counter (TCNT) to overflow before being rewritten. In interval timer operation, an interval timer interrupt is requested at each TCNT overflow. 12.1.1 Features WDT features are listed below. * Selection of eight counter clock sources /2, /32, /64, /128, /256, /512, /2048, or /4096 * Interval timer option * Timer counter overflow generates a reset signal or interrupt. The reset signal is generated in watchdog timer operation. An interval timer interrupt is generated in interval timer operation. * Watchdog timer reset signal resets the entire H8/3029 internally. The reset signal generated by timer counter overflow during watchdog timer operation resets the entire H8/3029 internally. Rev. 2.0, 06/04, page 441 of 980 12.1.2 Block Diagram Figure 12.1 shows a block diagram of the WDT. Overflow TCNT Interrupt signal (interval timer) Interrupt control TCSR Read/ write control Internal data bus RSTCSR Internal clock sources /2 /32 /64 Clock Clock selector /128 /256 /512 /2048 /4096 Reset (internal) Reset control Legend TCNT: Timer counter TCSR: Timer control/status register RSTCSR: Reset control/status register Figure 12.1 WDT Block Diagram 12.1.3 Register Configuration Table 12.1 summarizes the WDT registers. Table 12.1 WDT Registers Address* Write* 2 1 Read Name Abbreviation TCSR TCNT RSTCSR R/W R/(W)* R/W R/(W)* 3 3 Initial Value H'18 H'00 H'3F H'FFF8C H'FFF8C Timer control/status register H'FFF8D Timer counter H'FFF8E H'FFF8F Reset control/status register Notes: *1 Lower 20 bits of the address in advanced mode. *2 Write word data starting at this address. *3 Only 0 can be written in bit 7, to clear the flag. Rev. 2.0, 06/04, page 442 of 980 12.2 12.2.1 Register Descriptions Timer Counter (TCNT) TCNT is an 8-bit readable and writable up-counter. Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Note: TCNT is write-protected by a password. For details see section 12.2.4, Notes on Register Access. When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from an internal clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from H'FF to H'00), the OVF bit is set to 1 in TCSR. TCNT is initialized to H'00 by a reset and when the TME bit is cleared to 0. Rev. 2.0, 06/04, page 443 of 980 12.2.2 Timer Control/Status Register (TCSR) TCSR is an 8-bit readable and writable register. Its functions include selecting the timer mode and clock source. Bit Initial value Read/Write 7 OVF 0 R/(W) * 6 WT/IT 0 R/W 5 TME 0 R/W 4 -- 1 -- 3 -- 1 -- 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Clock select These bits select the TCNT clock source Reserved bits Timer enable Selects whether TCNT runs or halts Timer mode select Selects the mode Overflow flag Status flag indicating overflow Notes: TCSR is write-protected by a password. For details see section 12.2.4, Notes on Register Access. * Only 0 can be written, to clear the flag. Bits 7 to 5 are initialized to 0 by a reset and in standby mode. Bits 2 to 0 are initialized to 0 by a reset. In software standby mode bits 2 to 0 are not initialized, but retain their previous values. Rev. 2.0, 06/04, page 444 of 980 Bit 7--Overflow Flag (OVF): This status flag indicates that the timer counter has overflowed from H'FF to H'00. Bit 7 OVF 0 1 Description [Clearing condition] Cleared by reading OVF when OVF = 1, then writing 0 in OVF [Setting condition] Set when TCNT changes from H'FF to H'00 (Initial value) IT): Bit 6--Timer Mode Select (WT/IT Selects whether to use the WDT as a watchdog timer or IT interval timer. If used as an interval timer, the WDT generates an interval timer interrupt request when TCNT overflows. If used as a watchdog timer, the WDT generates a reset signal when TCNT overflows. Bit 6 WT/IT IT 0 1 Description Interval timer: requests interval timer interrupts Watchdog timer: generates a reset signal (Initial value) Bit 5--Timer Enable (TME): Selects whether TCNT runs or is halted. When WT/IT = 1, clear the software standby bit (SSBY) to 0 in SYSCR before setting TME. When setting SSBY to 1, TME should be cleared to 0. Bit 5 TME 0 1 Description TCNT is initialized to H'00 and halted TCNT is counting (Initial value) Bits 4 and 3--Reserved: These bits cannot be modified and are always read as 1. Rev. 2.0, 06/04, page 445 of 980 Bits 2 to 0--Clock Select 2 to 0 (CKS2/1/0): These bits select one of eight internal clock sources, obtained by prescaling the system clock (), for input to TCNT. Bit 2 CKS2 0 Bit 1 CKS1 0 1 1 0 1 Bit 0 CKS0 0 1 0 1 0 1 0 1 Description /2 /32 /64 /128 /256 /512 /2048 /4096 (Initial value) 12.2.3 Reset Control/Status Register (RSTCSR) RSTCSR is an 8-bit readable and writable register that indicates when a reset signal has been generated by watchdog timer overflow, and controls external output of the reset signal. Bit Initial value Read/Write 7 WRST 0 R/(W)* 6 -- 0 R/W 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Reserved bits Watchdog timer reset Indicates that a reset signal has been generated Notes: RSTCSR is write-protected by a password. For details see section 12.2.4, Notes on Register Access. * Only 0 can be written in bit 7, to clear the flag. Bits 7 and 6 are initialized by input of a reset signal at the RES pin. They are not initialized by reset signals generated by watchdog timer overflow. Rev. 2.0, 06/04, page 446 of 980 Bit 7--Watchdog Timer Reset (WRST): During watchdog timer operation, this bit indicates that TCNT has overflowed and generated a reset signal. This reset signal resets the entire H8/3029 chip internally. Bit 7 WRST 0 Description [Clearing condition] Reset signal at RES pin. Read WRST when WRST =1, then write 0 in WRST. (Initial value) 1 [Setting condition] Set when TCNT overflow generates a reset signal during watchdog timer operation Bit 6--Reserved: The write value should always be 0. Bits 5 to 0--Reserved: These bits are always read as 1. The write value should always be 1. 12.2.4 Notes on Register Access The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write. The procedures for writing and reading these registers are given below. Writing to TCNT and TCSR: These registers must be written by a word transfer instruction. They cannot be written by byte instructions. Figure 12.2 shows the format of data written to TCNT and TCSR. TCNT and TCSR both have the same write address. The write data must be contained in the lower byte of the written word. The upper byte must contain H'5A (password for TCNT) or H'A5 (password for TCSR). This transfers the write data from the lower byte to TCNT or TCSR. TCNT write Address H'FFF8C * 15 H'5A 87 Write data 0 TCSR write Address H'FFF8C * 15 H'A5 87 Write data 0 Note: * Lower 20 bits of the address in advanced mode. Figure 12.2 Format of Data Written to TCNT and TCSR Rev. 2.0, 06/04, page 447 of 980 Writing to RSTCSR: RSTCSR must be written by a word transfer instruction. It cannot be written by byte transfer instructions. Figure 12.3 shows the format of data written to RSTCSR. To write 0 in the WRST bit, the write data must have H'A5 in the upper byte and H'00 in the lower byte. The data (H'00) in the lower byte is written to RSTCSR, clearing the WRST bit to 0. 15 H'A5 87 H'00 0 Writing 0 in WRST bit Address H'FFF8E* Note: * Lower 20 bits of the address in advanced mode. Figure 12.3 Format of Data Written to RSTCSR Reading TCNT, TCSR, and RSTCSR: These registers are read like other registers. Reading TCNT, TCSR, and RSTCSR: These registers are read like other registers. Byte transfer instructions can be used. The read addresses are H'FFF8C for TCSR, H'FFF8D for TCNT, and H'FFF8F for RSTCSR, as listed in table 12.2. Table 12.2 Read Addresses of TCNT, TCSR, and RSTCSR Address* H'FFF8C H'FFF8D H'FFF8F Note: * Register TCSR TCNT RSTCSR Lower 20 bits of the address in advanced mode. Rev. 2.0, 06/04, page 448 of 980 12.3 Operation Operations when the WDT is used as a watchdog timer and as an interval timer are described below. 12.3.1 Watchdog Timer Operation Figure 12.4 illustrates watchdog timer operation. To use the WDT as a watchdog timer, set the WT/IT and TME bits to 1 in TCSR. Software must prevent TCNT overflow by rewriting the TCNT value (normally by writing H'00) before overflow occurs. If TCNT fails to be rewritten and overflows due to a system crash etc., the H8/3029 is internally reset for a duration of 518 states. A watchdog reset has the same vector as a reset generated by input at the RES pin. Software can distinguish a RES reset from a watchdog reset by checking the WRST bit in RSTCSR. If a RES reset and a watchdog reset occur simultaneously, the RES reset takes priority. WDT overflow H'FF TCNT count value H'00 TME set to 1 OVF = 1 Start Internal reset signal H'00 written in TCNT Reset H'00 written in TCNT 518 states Figure 12.4 Operation in Watchdog Timer Mode Rev. 2.0, 06/04, page 449 of 980 12.3.2 Interval Timer Operation Figure 12.5 illustrates interval timer operation. To use the WDT as an interval timer, clear bit WT/IT to 0 and set bit TME to 1 in TCSR. An interval timer interrupt request is generated at each TCNT overflow. This function can be used to generate interval timer interrupts at regular intervals. H'FF TCNT count value Time t H'00 WT/ 16 = 0 TME = 1 Interval timer interrupt Interval timer interrupt Interval timer interrupt Interval timer interrupt Figure 12.5 Interval Timer Operation Rev. 2.0, 06/04, page 450 of 980 12.3.3 Timing of Setting of Overflow Flag (OVF) Figure 12.6 shows the timing of setting of the OVF flag. The OVF flag is set to 1 when TCNT overflows. At the same time, a reset signal is generated in watchdog timer operation, or an interval timer interrupt is generated in interval timer operation. TCNT H'FF H'00 Overflow signal OVF Figure 12.6 Timing of Setting of OVF Rev. 2.0, 06/04, page 451 of 980 12.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) The WRST bit in RSTCSR is valid when bits WT/IT and TME are both set to 1 in TCSR. Figure 12.7 shows the timing of setting of WRST and the internal reset timing. The WRST bit is set to 1 when TCNT overflows and OVF is set to 1. At the same time an internal reset signal is generated for the entire H8/3029 chip. This internal reset signal clears OVF to 0, but the WRST bit remains set to 1. The reset routine must therefore clear the WRST bit. TCNT H'FF H'00 Overflow signal OVF WDT internal reset WRST Figure 12.7 Timing of Setting of WRST Bit and Internal Reset Rev. 2.0, 06/04, page 452 of 980 12.4 Interrupts During interval timer operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF bit is set to 1 in TCSR. 12.5 Usage Notes Contention between TCNT Write and Increment: If a timer counter clock pulse is generated during the T3 state of a write cycle to TCNT, the write takes priority and the timer count is not incremented. See figure 12.8. CPU: TCNT write cycle T1 T2 T3 TCNT Internal write signal TCNT input clock TCNT N M Counter write data Figure 12.8 Contention between TCNT Write and Count up Changing CKS2 to CKS0 Bit: Halt TCNT by clearing the TME bit to 0 in TCSR before changing the values of bits CKS2 to CKS0. Rev. 2.0, 06/04, page 453 of 980 Rev. 2.0, 06/04, page 454 of 980 Section 13 Serial Communication Interface 13.1 Overview The H8/3029 has a serial communication interface (SCI) with three independent channels. All three channels have identical functions. The SCI can communicate in both asynchronous and synchronous mode. It also has a multiprocessor communication function for serial communication among two or more processors. When the SCI is not used, it can be halted to conserve power. Each SCI channel can be halted independently. For details, see section 20.6, Module Standby Function. The SCI also has a smart card interface function conforming to the ISO/IEC 7816-3 (Identification Card) standard. This function supports serial communication with a smart card. Switching between the normal serial communication interface and the smart card interface is carried out by means of a register setting. 13.1.1 Features SCI features are listed below. * Selection of synchronous or asynchronous mode for serial communication Asynchronous mode Serial data communication is synchronized one channel at a time. The SCI can communicate with a universal asynchronous receiver/transmitter (UART), asynchronous communication interface adapter (ACIA), or other chip that employs standard asynchronous communication. It can also communicate with two or more other processors using the multiprocessor communication function. There are 12 selectable serial data transfer formats. Data length: Stop bit length: Parity: Multiprocessor bit: Receive error detection: Break detection: Synchronous mode Serial data communication is synchronized with a clock signal. The SCI can communicate with other chips having a synchronous communication function. There is a single serial data communication format. Data length: Receive error detection: 8 bits overrun errors Rev. 2.0, 06/04, page 455 of 980 7 or 8 bits 1 or 2 bits even/odd/none 1 or 0 parity, overrun, and framing errors by reading the RxD level directly when a framing error occurs * Full-duplex communication The transmitting and receiving sections are independent, so the SCI can transmit and receive simultaneously. The transmitting and receiving sections are both double-buffered, so serial data can be transmitted and received continuously. * The following settings can be made for the serial data to be transferred: LSB-first or MSB-first transfer Inversion of data logic level * Built-in baud rate generator with selectable bit rates * Selectable transmit/receive clock sources: internal clock from baud rate generator, or external clock from the SCK pin * Four types of interrupts Transmit-data-empty, transmit-end, receive-data-full, and receive-error interrupts are requested independently. The transmit-data-empty and receive-data-full interrupts from SCI0 can activate the DMA controller (DMAC) to transfer data. Features of the smart card interface are listed below. * Asynchronous communication Data length: 8 bits Parity bits generated and checked Error signal output in receive mode (parity error) Error signal detect and automatic data retransmit in transmit mode Supports both direct convention and inverse convention * Built-in baud rate generator with selectable bit rates * Three types of interrupts Transmit-data-empty, receive-data-full, and transmit/receive-error interrupts are requested independently. The transmit-data-empty and receive-data-full interrupts can activate the DMA controller (DMAC) to transfer data. Rev. 2.0, 06/04, page 456 of 980 13.1.2 Block Diagram Figure 13.1 shows a block diagram of the SCI. Module data bus Bus interface Internal data bus RDR TDR SSR SCR SMR SCMR Transmit/receive control BRR Baud rate generator / 4 /16 /64 RxD RSR TSR TxD Parity generate Parity check Clock External clock TEI TXI RXI ERI SCK Legend RSR : Receive shift register RDR : Receive data register TSR : Transmit shift register TDR : Transmit data register SMR : Serial mode register SCR : Serial control register SSR : Serial status register BRR : Bit rate register SCMR : Smart card mode register Figure 13.1 SCI Block Diagram Rev. 2.0, 06/04, page 457 of 980 13.1.3 Input/Output Pins The SCI has serial pins for each channel as listed in table 13.1. Table 13.1 SCI Pins Channel Name 0 Serial clock pin Receive data pin Transmit data pin 1 Serial clock pin Receive data pin Transmit data pin 2 Serial clock pin Receive data pin Transmit data pin Abbreviation SCK0 RxD0 TxD0 SCK1 RxD1 TxD1 SCK2 RxD2 TxD2 I/O Input/output Input Output Input/output Input Output Input/output Input Output Function SCI0 clock input/output SCI0 receive data input SCI0 transmit data output SCI1 clock input/output SCI1 receive data input SCI1 transmit data output SCI2 clock input/output SCI2 receive data input SCI2 transmit data output Rev. 2.0, 06/04, page 458 of 980 13.1.4 Register Configuration The SCI has internal registers as listed in table 13.2. These registers select asynchronous or synchronous mode, specify the data format and bit rate, control the transmitter and receiver sections, and specify switching between the serial communication interface and smart card interface. Table 13.2 SCI Registers Channel 0 Address* H'FFFB0 H'FFFB1 H'FFFB2 H'FFFB3 H'FFFB4 H'FFFB5 H'FFFB6 1 H'FFFB8 H'FFFB9 H'FFFBA H'FFFBB H'FFFBC H'FFFBD H'FFFBE 2 H'FFFC0 H'FFFC1 H'FFFC2 H'FFFC3 H'FFFC4 H'FFFC5 H'FFFC6 1 Name Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Smart card mode register Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Smart card mode register Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Smart card mode register Abbreviation SMR BRR SCR TDR SSR RDR SCMR SMR BRR SCR TDR SSR RDR SCMR SMR BRR SCR TDR SSR RDR SCMR R/W R/W R/W R/W R/W 2 Initial Value H'00 H'FF H'00 H'FF H'00 H'F2 H'00 H'FF H'00 H'FF 2 R/(W)* H'84 R R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W 2 R/(W)* H'84 H'00 H'F2 H'00 H'FF H'00 H'FF H'00 H'F2 R/(W)* H'84 R R/W Notes: *1 Indicates the lower 20 bits of the address in advanced mode. *2 Only 0 can be written, to clear flags. Rev. 2.0, 06/04, page 459 of 980 13.2 13.2.1 Register Descriptions Receive Shift Register (RSR) RSR is the register that receives serial data. Bit 7 6 5 4 3 2 1 0 Read/Write The SCI loads serial data input at the RxD pin into RSR in the order received, LSB (bit 0) first, thereby converting the data to parallel data. When one byte of data has been received, it is automatically transferred to RDR. The CPU cannot read or write RSR directly. 13.2.2 Receive Data Register (RDR) RDR is the register that stores received serial data. Bit 7 6 5 4 3 2 1 0 Initial value Read/Write 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R When the SCI has received one byte of serial data, it transfers the received data from RSR into RDR for storage, completing the receive operation. RSR is then ready to receive the next data. This double-buffering allows data to be received continuously. RDR is a read-only register. Its contents cannot be modified by the CPU. RDR is initialized to H'00 by a reset and in standby mode. Rev. 2.0, 06/04, page 460 of 980 13.2.3 Transmit Shift Register (TSR) TSR is the register that transmits serial data. Bit 7 6 5 4 3 2 1 0 Read/Write The SCI loads transmit data from TDR to TSR, then transmits the data serially from the TxD pin, LSB (bit 0) first. After transmitting one data byte, the SCI automatically loads the next transmit data from TDR into TSR and starts transmitting it. If the TDRE flag is set to 1 in SSR, however, the SCI does not load the TDR contents into TSR. The CPU cannot read or write RSR directly. 13.2.4 Transmit Data Register (TDR) TDR is an 8-bit register that stores data for serial transmission. Bit 7 6 5 4 3 2 1 0 Initial value Read/Write 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W When the SCI detects that TSR is empty, it moves transmit data written in TDR from TDR into TSR and starts serial transmission. Continuous serial transmission is possible by writing the next transmit data in TDR during serial transmission from TSR. The CPU can always read and write TDR. TDR is initialized to H'FF by a reset and in standby mode. Rev. 2.0, 06/04, page 461 of 980 13.2.5 Serial Mode Register (SMR) SMR is an 8-bit register that specifies the SCI's serial communication format and selects the clock source for the baud rate generator. Bit 7 C/) Initial value Read/Write 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Clock select 1/0 These bits select the baud rate generator's clock source Multiprocessor mode Selects the multiprocessor function Stop bit length Selects the stop bit length Parity mode Selects even or odd parity Parity enable Enables or disables the addition of a parity bit Character length Selects character length in asynchronous mode Communication mode Selects asynchronous or synchronous mode The CPU can always read and write SMR. SMR is initialized to H'00 by a reset and in standby mode. Bit 7--Communication Mode (C/A)/GSM Mode (GM): The function of this bit differs for the A normal serial communication interface and for the smart card interface. Its function is switched with the SMIF bit in SCMR. Rev. 2.0, 06/04, page 462 of 980 For serial communication interface (SMIF bit in SCMR cleared to 0): Selects whether the SCI operates in asynchronous or synchronous mode. Bit 7 C/A A 0 1 Description Asynchronous mode Synchronous mode (Initial value) For smart card interface (SMIF bit in SCMR set to 1): Selects GSM mode for the smart card interface. Bit 7 GM 0 1 Description The TEND flag is set 12.5 etu after the start bit The TEND flag is set 11.0 etu after the start bit (Initial value) Note: etu: Elementary time unit (time required to transmit one bit) Bit 6--Character Length (CHR): Selects 7-bit or 8-bits data length in asynchronous mode. In synchronous mode, the data length is 8 bits regardless of the CHR setting. Bit 6 CHR 0 1 Note: * Description 8-bit data 7-bit data* When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted. (Initial value) Bit 5--Parity Enable (PE): In asynchronous mode, this bit enables or disables the addition of a parity bit to transmit data, and the checking of the parity bit in receive data. In synchronous mode, the parity bit is neither added nor checked, regardless of the PE bit setting. Bit 5 PE 0 1 Note: * Description Parity bit not added or checked Parity bit added and checked* When PE bit is set to 1, an even or odd parity bit is added to transmit data according to the even or odd parity mode selection by the O/E bit, and the parity bit in receive data is checked to see that it matches the even or odd mode selected by the O/E bit. (Initial value) Rev. 2.0, 06/04, page 463 of 980 Bit 4--Parity Mode (O/E): Selects even or odd parity. The O/E bit setting is only valid when the E PE bit is set to 1, enabling parity bit addition and checking, in asynchronous mode. The O/E bit setting is ignored in synchronous mode, or when parity addition and checking is disabled in asynchronous mode. Bit 4 O/E E 0 1 Description Even parity* Odd parity* 2 1 (Initial value) Notes: *1 When even parity is selected, the parity bit added to transmit data makes an even number of 1s in the transmitted character and parity bit combined. Receive data must have an even number of 1s in the received character and parity bit combined. *2 When odd parity is selected, the parity bit added to transmit data makes an odd number of 1s in the transmitted character and parity bit combined. Receive data must have an odd number of 1s in the received character and parity bit combined. Bit 3--Stop Bit Length (STOP): Selects one or two stop bits in asynchronous mode. This setting is used only in asynchronous mode. In synchronous mode no stop bit is added, so the STOP bit setting is ignored. Bit 3 STOP 0 1 Description 1 stop bit* 1 2 (Initial value) 2 stop bits* Notes: *1 One stop bit (with value 1) is added to the end of each transmitted character. *2 Two stop bits (with value 1) are added to the end of each transmitted character. In receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit. If the second stop bit is 0, it is treated as the start bit of the next incoming character. Bit 2--Multiprocessor Mode (MP): Selects a multiprocessor format. When a multiprocessor format is selected, parity settings made by the PE and O/E bits are ignored. The MP bit setting is valid only in asynchronous mode. It is ignored in synchronous mode. For further information on the multiprocessor communication function, see section 13.3.3, Multiprocessor Communication. Bit 2 MP 0 1 Description Multiprocessor function disabled Multiprocessor format selected (Initial value) Rev. 2.0, 06/04, page 464 of 980 Bits 1 and 0--Clock Select 1 and 0 (CKS1/0): These bits select the clock source for the on-chip baud rate generator. Four clock sources are available: , /4, /16, and /64. For the relationship between the clock source, bit rate register setting, and baud rate, see section 13.2.8, Bit Rate Register (BRR). Bit 1 CKS1 0 0 1 1 Bit 0 CKS0 0 1 0 1 Description /4 /16 /64 (Initial value) Rev. 2.0, 06/04, page 465 of 980 13.2.6 Serial Control Register (SCR) SCR register enables or disables the SCI transmitter and receiver, enables or disables serial clock output in asynchronous mode, enables or disables interrupts, and selects the transmit/receive clock source. Bit 7 TIE Initial value Read/Write 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W Clock enable 1/0 These bits select the SCI clock source Transmit-end interrupt enable Enables or disables transmit-end interrupts (TEI) Multiprocessor interrupt enable Enables or disables multiprocessor interrupts Receive enable Enables or disables the receiver Transmit enable Enables or disables the transmitter Receive interrupt enable Enables or disables receive-data-full interrupts (RXI) and receive-error interrupts (ERI) Transmit interrupt enable Enables or disables transmit-data-empty interrupts (TXI) The CPU can always read and write SCR. SCR is initialized to H'00 by a reset and in standby mode. Rev. 2.0, 06/04, page 466 of 980 Bit 7--Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt (TXI) requested when the TDRE flag in SSR is set to 1 due to transfer of serial transmit data from TDR to TSR. Bit 7 TIE 0 1 Note: * Description Transmit-data-empty interrupt request (TXI) is disabled* Transmit-data-empty interrupt request (TXI) is enabled TXI interrupt requests can be cleared by reading the value 1 from the TDRE flag, then clearing it to 0; or by clearing the TIE bit to 0. (Initial value) Bit 6--Receive Interrupt Enable (RIE): Enables or disables the receive-data-full interrupt (RXI) requested when the RDRF flag in SSR is set to 1 due to transfer of serial receive data from RSR to RDR; also enables or disables the receive-error interrupt (ERI). Bit 6 RIE 0 1 Note: * Description Receive-data-full (RXI) and receive-error (ERI) interrupt requests are disabled* (Initial value) Receive-data-full (RXI) and receive-error (ERI) interrupt requests are enabled RXI and ERI interrupt requests can be cleared by reading the value 1 from the RDRF, FER, PER, or ORER flag, then clearing the flag to 0; or by clearing the RIE bit to 0. Bit 5--Transmit Enable (TE): Enables or disables the start of SCI serial transmitting operations. Bit 5 TE 0 1 Description Transmitting disabled* Transmitting enabled* 1 (Initial value) 2 Notes: *1 The TDRE flag is fixed at 1 in SSR. *2 In the enabled state, serial transmission starts when the TDRE flag in SSR is cleared to 0 after writing of transmit data into TDR. Select the transmit format in SMR before setting the TE bit to 1. Rev. 2.0, 06/04, page 467 of 980 Bit 4--Receive Enable (RE): Enables or disables the start of SCI serial receiving operations. Bit 4 RE 0 1 Description Receiving disabled* Receiving enabled* 1 (Initial value) 2 Notes: *1 Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags. These flags retain their previous values. *2 In the enabled state, serial receiving starts when a start bit is detected in asynchronous mode, or serial clock input is detected in synchronous mode. Select the receive format in SMR before setting the RE bit to 1. Bit 3--Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE bit setting is valid only in asynchronous mode, and only if the MP bit is set to 1 in SMR. The MPIE bit setting is ignored in synchronous mode or when the MP bit is cleared to 0. Bit 3 MPIE 0 Description Multiprocessor interrupts are disabled (normal receive operation) (Initial value) Clearing conditions (1) The MPIE bit is cleared to 0 (2) MPB = 1 in received data Multiprocessor interrupts are enabled* Receive-data-full interrupts (RXI), receive-error interrupts (ERI), and setting of the RDRF, FER, and ORER status flags in SSR are disabled until data with the multiprocessor bit set to 1 is received. * The SCI does not transfer receive data from RSR to RDR, does not detect receive errors, and does not set the RDRF, FER, and ORER flags in SSR. When it receives data in which MPB = 1, the SCI sets the MPB bit to 1 in SSR, automatically clears the MPIE bit to 0, enables RXI and ERI interrupts (if the TIE and RIE bits in SCR are set to 1), and allows the FER and ORER flags to be set. 1 Note: Bit 2--Transmit-End interrupt Enable (TEIE): Enables or disables the transmit-end interrupt (TEI) requested if TDR does not contain valid transmit data when the MSB is transmitted. Bit 2 TEIE 0 1 Note: * Description Transmit-end interrupt requests (TEI) are disabled* Transmit-end interrupt requests (TEI) are enabled* TEI interrupt requests can be cleared by reading the value 1 from the TDRE flag in SSR, then clearing the TDRE flag to 0, thereby also clearing the TEND flag to 0; or by clearing the TEIE bit to 0. (Initial value) Rev. 2.0, 06/04, page 468 of 980 Bits 1 and 0--Clock Enable 1 and 0 (CKE1/0): The function of these bits differs for the normal serial communication interface and for the smart card interface. Their function is switched with the SMIF bit in SCMR. For serial communication interface (SMIF bit in SCMR cleared to 0): These bits select the SCI clock source and enable or disable clock output from the SCK pin. Depending on the settings of CKE1 and CKE0, the SCK pin can be used for generic input/output, serial clock output, or serial clock input. The CKE0 setting is valid only in asynchronous mode, and only when the SCI is internally clocked (CKE1 = 0). The CKE0 setting is ignored in synchronous mode, or when an external clock source is selected (CKE1 = 1). Select the SCI operating mode in SMR before setting the CKE1 and CKE0 bits . For further details on selection of the SCI clock source, see table 13.9 in section 13.3, Operation. Bit 1 Bit 0 CKE1 CKE0 Description 0 0 1 1 0 1 0 1 Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode Internal clock, SCK pin available for generic input/output* Internal clock, SCK pin used for serial clock output* Internal clock, SCK pin used for clock output* External clock, SCK pin used for clock input* External clock, SCK pin used for clock input* 2 1 1 Internal clock, SCK pin used for serial clock output 3 External clock, SCK pin used for serial clock input 3 External clock, SCK pin used for serial clock input Notes: *1 Initial value *2 The output clock frequency is the same as the bit rate. *3 The input clock frequency is 16 times the bit rate. Rev. 2.0, 06/04, page 469 of 980 For smart card interface (SMIF bit in SCMR set to 1): These bits, together with the GM bit in SMR, determine whether the SCK pin is used for generic input/output or as the serial clock output pin. SMR GM 0 0 1 1 1 1 Bit 1 Bit 0 CKE1 CKE0 Description 0 0 0 0 1 1 0 1 0 1 0 1 SCK pin available for generic input/output SCK pin used for clock output SCK pin output fixed low SCK pin used for clock output SCK pin output fixed high SCK pin used for clock output (Initial value) Rev. 2.0, 06/04, page 470 of 980 13.2.7 Serial Status Register (SSR) SSR is an 8-bit register containing multiprocessor bit values, and status flags that indicate the operating status of the SCI. Bit 7 TDRE Initial value Read/Write 1 R/(W)* 1 6 RDRF 0 R/(W)* 1 5 4 3 PER 0 1 2 TEND 1 1 1 MPB 0 R 0 MPBT 0 R/W Multiprocessor bit transfer Value of multiprocessor bit to be transmitted Multiprocessor bit Stores the received multiprocessor bit value ORER FER/ERS 0 R/(W)* 1 0 R/(W)* R/(W)* R Transmit end*2 Status flag indicating end of transmission Parity error Status flag indicating detection of a receive parity error Framing error (FER)/Error signal status (ERS)*2 Status flag indicating detection of a receive framing error, or flag indicating detection of an error signal Overrun error Status flag indicating detection of a receive overrun error Receive data register full Status flag indicating that data has been received and stored in RDR Transmit data register empty Status flag indicating that transmit data has been transferred from TDR into TSR and new data can be written in TDR Notes: *1 Only 0 can be written, to clear the flag. *2 Function differs between the normal serial communication interface and the smart card interface. The CPU can always read and write SSR, but cannot write 1 in the TDRE, RDRF, ORER, PER, and FER flags. These flags can be cleared to 0 only if they have first been read while set to 1. The TEND and MPB flags are read-only bits that cannot be written. SSR is initialized to H'84 by a reset and in standby mode. Rev. 2.0, 06/04, page 471 of 980 Bit 7--Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data from TDR into TSR and the next serial data can be written in TDR. Bit 7 TDRE 0 Description TDR contains valid transmit data [Clearing conditions] Read TDRE when TDRE = 1, then write 0 in TDRE The DMAC writes data in TDR TDR does not contain valid transmit data (Initial value) [Setting conditions] The chip is reset or enters standby mode The TE bit in SCR is cleared to 0 TDR contents are loaded into TSR, so new data can be written in TDR 1 Bit 6--Receive Data Register Full (RDRF): Indicates that RDR contains new receive data. Bit 6 RDRF 0 Description RDR does not contain new receive data [Clearing conditions] The chip is reset or enters standby mode Read RDRF when RDRF = 1, then write 0 in RDRF The DMAC reads data from RDR (Initial value) 1 RDR contains new receive data [Setting condition] Serial data is received normally and transferred from RSR to RDR Note: The RDR contents and the RDRF flag are not affected by detection of receive errors or by clearing of the RE bit to 0 in SCR. They retain their previous values. If the RDRF flag is still set to 1 when reception of the next data ends, an overrun error will occur and the receive data will be lost. Rev. 2.0, 06/04, page 472 of 980 Bit 5--Overrun Error (ORER): Indicates that data reception ended abnormally due to an overrun error. Bit 5 ORER 0 Description Receiving is in progress or has ended normally* [Clearing conditions] The chip is reset or enters standby mode Read ORER when ORER = 1, then write 0 in ORER A receive overrun error occurred* [Setting condition] Reception of the next serial data ends when RDRF = 1 2 1 (Initial value) 1 Notes: *1 Clearing the RE bit to 0 in SCR does not affect the ORER flag, which retains its previous value. *2 RDR continues to hold the receive data prior to the overrun error, so subsequent receive data is lost. Serial receiving cannot continue while the ORER flag is set to 1. In synchronous mode, serial transmitting is also disabled. Bit 4--Framing Error (FER)/Error Signal Status (ERS): The function of this bit differs for the normal serial communication interface and for the smart card interface. Its function is switched with the SMIF bit in SCMR. For serial communication interface (SMIF bit in SCMR cleared to 0): Indicates that data reception ended abnormally due to a framing error in asynchronous mode. Bit 4 FER 0 Description Receiving is in progress or has ended normally* [Clearing conditions] The chip is reset or enters standby mode Read FER when FER = 1, then write 0 in FER 2 1 (Initial value) 1 A receive framing error occurred* [Setting condition] The stop bit at the end of the receive data is checked and found to be 0 Notes: *1 Clearing the RE bit to 0 in SCR does not affect the FER flag, which retains its previous value. *2 When the stop bit length is 2 bits, only the first bit is checked. The second stop bit is not checked. When a framing error occurs the SCI transfers the receive data into RDR but does not set the RDRF flag. Serial receiving cannot continue while the FER flag is set to 1. In synchronous mode, serial transmitting is also disabled. Rev. 2.0, 06/04, page 473 of 980 For smart card interface (SMIF bit in SCMR set to 1): Indicates the status of the error signal sent back from the receiving side during transmission. Framing errors are not detected in smart card interface mode. Bit 4 ERS 0 Description Normal reception, no error signal* [Clearing conditions] The chip is reset or enters standby mode Read ERS when ERS = 1, then write 0 in ERS (Initial value) 1 An error signal has been sent from the receiving side indicating detection of a parity error [Setting condition] The error signal is low when sampled * Clearing the TE bit to 0 in SCR does not affect the ERS flag, which retains its previous value. Note: Bit 3--Parity Error (PER): Indicates that data reception ended abnormally due to a parity error in asynchronous mode. Bit 3 PER 0 Description Receiving is in progress or has ended normally* [Clearing conditions] The chip is reset or enters standby mode Read PER when PER = 1, then write 0 in PER 2 1 (Initial value) 1 A receive parity error occurred* [Setting condition] The number of 1s in receive data, including the parity bit, does not match the even or odd parity setting of O/E in SMR Notes: *1 Clearing the RE bit to 0 in SCR does not affect the PER flag, which retains its previous value. *2 When a parity error occurs the SCI transfers the receive data into RDR but does not set the RDRF flag. Serial receiving cannot continue while the PER flag is set to 1. In synchronous mode, serial transmitting is also disabled. Bit 2--Transmit End (TEND): The function of this bit differs for the normal serial communication interface and for the smart card interface. Its function is switched with the SMIF bit in SCMR. For serial communication interface (SMIF bit in SCMR cleared to 0): Indicates that when the last bit of a serial character was transmitted TDR did not contain valid transmit data, so transmission has ended. The TEND flag is a read-only bit and cannot be written. Rev. 2.0, 06/04, page 474 of 980 Bit 2 TEND 0 Description Transmission is in progress [Clearing conditions] Read TDRE when TDRE = 1, then write 0 in TDRE The DMAC writes data in TDR End of transmission (Initial value) [Setting conditions] The chip is reset or enters standby mode The TE bit in SCR is cleared to 0 TDRE is 1 when the last bit of a 1-byte serial transmit character is transmitted 1 For smart card interface (SMIF bit in SCMR set to 1): Indicates that when the last bit of a serial character was transmitted TDR did not contain valid transmit data, so transmission has ended. The TEND flag is a read-only bit and cannot be written. Bit 2 TEND 0 Description Transmission is in progress [Clearing conditions] Read TDRE when TDRE = 1, then write 0 in TDRE The DMAC writes data in TDR End of transmission (Initial value) [Setting conditions] The chip is reset or enters standby mode The TE bit is cleared to 0 in SCR and the FER/ERS bit is also cleared to 0 TDRE is 1 and FER/ERS is 0 (normal transmission) 2.5 etu (when GM = 0) or 1.0 etu (when GM = 1) after a 1-byte serial character is transmitted 1 Note: etu: Elementary time unit (time required to transmit one bit) Bit 1--Multiprocessor bit (MPB): Stores the value of the multiprocessor bit in the receive data when a multiprocessor format is used in asynchronous mode. MPB is a read-only bit, and cannot be written. Bit 1 MPB 0 1 Note: * Description Multiprocessor bit value in receive data is 0* Multiprocessor bit value in receive data is 1 If the RE bit in SCR is cleared to 0 when a multiprocessor format is selected, MPB retains its previous value. (Initial value) Rev. 2.0, 06/04, page 475 of 980 Bit 0--Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit added to transmit data when a multiprocessor format in selected for transmitting in asynchronous mode. The MPBT bit setting is ignored in synchronous mode, when a multiprocessor format is not selected, or when the SCI cannot transmit. Bit 1 MPBT 0 1 Description Multiprocessor bit value in transmit data is 0 Multiprocessor bit value in transmit data is 1 (Initial value) 13.2.8 Bit Rate Register (BRR) BRR is an 8-bit register that, together with the CKS1 and CKS0 bits in SMR that select the baud rate generator clock source, determines the serial communication bit rate. Bit 7 6 5 4 3 2 1 0 Initial value Read/Write 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W The CPU can always read and write BRR. BRR is initialized to H'FF by a reset and in standby mode. Each SCI channel has independent baud rate generator control, so different values can be set in the three channels. Table 13.3 shows examples of BRR settings in asynchronous mode. Table 13.4 shows examples of BRR settings in synchronous mode. Rev. 2.0, 06/04, page 476 of 980 Table 13.3 Examples of Bit Rates and BRR Settings in Asynchronous Mode (MHz) Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 10 nN Error (%) nN 12 Error (%) 12.288 nN Error (%) nN 2 230 2 168 2 84 1 168 1 84 0 168 0 84 0 41 0 20 0 12 0 10 13 Error (%) -0.08 0.16 -0.43 0.16 -0.43 0.16 -0.43 0.76 0.76 0.00 -3.82 nN 2 248 2 181 2 90 1 181 1 90 0 181 0 90 0 45 0 22 0 13 0 10 14 Error (%) -0.17 0.16 0.16 0.16 0.16 0.16 0.16 -0.93 -0.93 0.00 3.57 2 177 -0.25 2 129 0.16 2 64 1 64 0 64 0 32 0 15 09 07 0.16 0.16 0.16 -1.36 1.73 0.00 1.73 1 129 0.16 0 129 0.16 2 212 0.03 2 155 0.16 2 77 1 77 0 77 0 38 0 19 0 11 09 0.16 0.16 0.16 0.16 -2.34 0.00 -2.34 1 155 0.16 0 155 0.16 2 217 0.08 2 159 0.00 2 79 1 79 0 79 0 39 0 19 0 11 09 0.00 0.00 0.00 0.00 0.00 2.40 0.00 1 159 0.00 0 159 0.00 Rev. 2.0, 06/04, page 477 of 980 (MHz) Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 14.7456 nN 3 64 2 95 1 95 0 95 0 47 0 23 0 14 0 11 Error (%) 16 nN 3 70 Error (%) 18 nN 3 79 Error (%) 20 nN 3 88 3 64 2 129 2 64 1 129 1 64 0 129 0 64 0 32 0 19 0 15 Error (%) 25 nN 3 110 3 80 2 162 2 80 1 162 1 80 0 162 0 80 0 40 0 24 0 19 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 0.03 -0.12 -0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 0.00 1.73 -0.02 0.47 -0.15 0.47 -0.15 0.47 -0.15 0.47 -0.76 0.00 1.73 2 191 0.00 1 191 0.00 0 191 0.00 2 207 0.16 2 103 0.16 1 207 0.16 1 103 0.16 0 207 0.16 0 103 0.16 0 51 0 25 0 15 0 12 0.16 0.16 0.00 0.16 2 233 0.16 2 116 0.16 1 233 0.16 1 116 0.16 0 233 0.16 0 116 0.16 0 58 0 28 0 17 0 14 -0.69 1.02 0.00 -2.34 Rev. 2.0, 06/04, page 478 of 980 Table 13.4 Examples of Bit Rates and BRR Settings in Synchronous Mode Bit Rate (bit/s) 110 250 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M 2M 2.5M 4M n -- -- -- -- 1 1 0 0 0 0 0 0 -- -- 0 10 N -- -- -- -- 249 124 249 99 49 24 9 4 -- -- 0* n -- 3 3 2 2 1 1 0 0 -- 0 -- -- -- -- 13 N -- 202 101 202 80 162 80 129 64 -- 12 -- -- -- -- n -- 3 3 2 2 1 1 0 0 0 0 0 0 0 -- 0 16 N -- 249 124 249 99 199 99 159 79 39 15 7 3 1 -- 0* n -- -- 3 3 2 1 1 0 0 0 0 0 0 -- -- -- (MHz) 18 N -- -- 140 69 112 224 112 179 89 44 17 8 4 -- -- -- n -- -- 3 3 2 1 1 0 0 0 0 0 0 -- -- -- 20 N -- -- 155 77 124 249 124 199 99 49 19 9 4 -- -- -- n -- -- -- 3 2 2 1 0 0 0 0 -- -- -- -- -- 25 N -- -- -- 97 155 77 155 249 124 62 24 -- -- -- -- -- Note: Settings with an error of 1% or less are recommended. Legend Blank : No setting available --: Setting possible, but error occurs *: Continuous transmission/reception not possible Rev. 2.0, 06/04, page 479 of 980 The BRR setting is calculated as follows: Asynchronous mode: N= Synchronous mode: 64 x 22n-1 x B x 106 - 1 N= B: N: : n: 8 x 22n-1 x B x 106 - 1 Bit rate (bit/s) BRR setting for baud rate generator (0 N 255) System clock frequency (MHz) Baud rate generator clock source (n = 0, 1, 2, 3) (For the clock sources and values of n, see the following table.) SMR Settings n 0 1 2 3 Clock Source /4 /16 /64 CKS1 0 0 1 1 CKS0 0 1 0 1 The bit rate error in asynchronous mode is calculated as follows: x 106 (N + 1) x B x 64 x 22n-1 x 100 Error (%) = -1 Rev. 2.0, 06/04, page 480 of 980 Table 13.5 shows the maximum bit rates in asynchronous mode for various system clock frequencies. Table 13.6 and 13.7 shows the maximum bit rates with external clock input. Table 13.5 Maximum Bit Rates for Various Frequencies (Asynchronous Mode) Settings (MHz) 10 12 12.288 14 14.7456 16 17.2032 18 20 25 Maximum Bit Rate (bit/s) 312500 375000 384000 437500 460800 500000 537600 562500 625000 781250 n 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 Table 13.6 Maximum Bit Rates with External Clock Input (Asynchronous Mode) (MHz) 10 12 12.288 14 14.7456 16 17.2032 18 20 25 External Input Clock (MHz) 2.5000 3.0000 3.0720 3.5000 3.6864 4.0000 4.3008 4.5000 5.0000 6.2500 Maximum Bit Rate (bit/s) 156250 187500 192000 218750 230400 250000 268800 281250 312500 390625 Rev. 2.0, 06/04, page 481 of 980 Table 13.7 Maximum Bit Rates with External Clock Input (Synchronous Mode) (MHz) 10 12 14 16 18 20 25 External Input Clock (MHz) 1.6667 2.0000 2.3333 2.6667 3.0000 3.3333 4.1667 Maximum Bit Rate (bit/s) 1666666.7 2000000.0 2333333.3 2666666.7 3000000.0 3333333.3 4166666.7 Rev. 2.0, 06/04, page 482 of 980 13.3 13.3.1 Operation Overview The SCI can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and synchronous mode in which synchronization is achieved with clock pulses. A smart card interface is also supported as a serial communication function for an IC card interface. Selection of asynchronous or synchronous mode and the transmission format for the normal serial communication interface is made in SMR, as shown in table 13.8. The SCI clock source is selected by the C/A bit in SMR and the CKE1 and CKE0 bits in SCR, as shown in table 13.9. For details of the procedures for switching between LSB-first and MSB-first mode and inverting the data logic level, see section 14.2.1, Smart Card Mode Register (SCMR). For selection of the smart card interface format, see section 14.3.3, Data Format. Asynchronous Mode * Data length is selectable: 7 or 8 bits * Parity and multiprocessor bits are selectable, and so is the stop bit length (1 or 2 bits). These selections determine the communication format and character length. * In receiving, it is possible to detect framing errors, parity errors, overrun errors, and the break state. * An internal or external clock can be selected as the SCI clock source. When an internal clock is selected, the SCI operates using the on-chip baud rate generator, and can output a serial clock signal with a frequency matching the bit rate. When an external clock is selected, the external clock input must have a frequency 16 times the bit rate. (The on-chip baud rate generator is not used.) Synchronous Mode * The communication format has a fixed 8-bit data length. * In receiving, it is possible to detect overrun errors. * An internal or external clock can be selected as the SCI clock source. When an internal clock is selected, the SCI operates using the on-chip baud rate generator, and can output a serial clock signal to external devices. When an external clock is selected, the SCI operates on the input serial clock. The on-chip baud rate generator is not used. Rev. 2.0, 06/04, page 483 of 980 Smart Card Interface * One frame consists of 8-bit data and a parity bit. * In transmitting, a guard time of at least two elementary time units (2 etu) is provided between the end of the parity bit and the start of he next frame. (An elementary time unit is the time required to transmit one bit.) * In receiving, if a parity error is detected, a low error signal level is output for 1 etu, beginning 10.5 etu after the start bit. * In transmitting, if an error signal is received, the same data is automatically transmitted again after at least 2 etu. * Only asynchronous communication is supported. There is no synchronous communication function. For details of smart card interface operation, see section 14, Smart Card Interface. Table 13.8 SMR Settings and Serial Communication Formats SMR Settings SCI Communication Format Multiprocessor Bit Absent Bit 7 C/A A 0 Bit 6 CHR 0 Bit 2 MP 0 Bit 5 PE 0 1 Bit 3 STOP 0 1 0 1 0 1 0 1 0 1 0 1 -- Mode AsynChronous mode Data Length 8-bit data Parity Bit Absent Present Stop Bit Length 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 0 1 7-bit data Absent Present 0 1 1 -- 1 -- -- -- -- Asyn8-bit data chronous Mode (multi7-bit data processor format) Synchronous mode 8-bit data Present Absent -- -- Absent None Rev. 2.0, 06/04, page 484 of 980 Table 13.9 SMR and SCR Settings and SCI Clock Source Selection SMR Bit 7 C/A A 0 SCR Setting Bit 1 Bit 0 CKE1 CKE0 Mode 0 0 1 1 1 0 1 0 1 0 1 0 1 Synchronous mode Internal External Asynchronous mode SCI Transmit/Receive clock Clock Source SCK Pin Function Internal SCI does not use the SCK pin Outputs clock with frequency matching the bit rate External Inputs clock with frequency 16 times the bit rate Outputs the serial clock Inputs the serial clock 13.3.2 Operation in Asynchronous Mode In asynchronous mode, each transmitted or received character begins with a start bit and ends with one or two stop bits. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCI are independent, so full-duplex communication is possible. The transmitter and the receiver are both double-buffered, so data can be written and read while transmitting and receiving are in progress, enabling continuous transmitting and receiving. Figure 13.2 shows the general format of asynchronous serial communication. In asynchronous serial communication the communication line is normally held in the mark (high) state. The SCI monitors the line and starts serial communication when the line goes to the space (low) state, indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit (high or low), and one or two stop bits (high), in that order. When receiving in asynchronous mode, the SCI synchronizes at the falling edge of the start bit. The SCI samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate. Receive data is latched at the center of each bit. Rev. 2.0, 06/04, page 485 of 980 Idle (mark) state 1 (LSB) 0 D0 D1 D2 D3 D4 D5 D6 (MSB) D7 0/1 1 1 1 Serial data Start bit 1 bit Transmit or receive data 7 or 8 bits One unit of data (character or frame) Parity bit 1 bit, or none Stop bit(s) 1 or 2 bits Figure 13.2 Data Format in Asynchronous Communication (Example: 8-Bit Data with Parity and 2 Stop Bits) Communication Formats: Table 13.10 shows the 12 communication formats that can be selected in asynchronous mode. The format is selected by settings in SMR. Rev. 2.0, 06/04, page 486 of 980 Table 13.10 Serial Communication Formats (Asynchronous Mode) SMR Settings CHR 0 PE 0 MP 0 STOP 0 Serial Communication Format and Frame Length 1 S 2 3 4 5 6 7 8 9 10 STOP 11 12 8-bit data 0 0 0 1 S 8-bit data STOP STOP 0 1 0 0 S 8-bit data P STOP 0 1 0 1 S 8-bit data P STOP STOP 1 0 0 0 S 7-bit data STOP 1 0 0 1 S 7-bit data STOP STOP 1 1 0 0 S 7-bit data P STOP 1 1 0 1 S 7-bit data P STOP STOP 0 -- 1 0 S 8-bit data MPB STOP 0 -- 1 1 S 8-bit data MPB STOP STOP 1 -- 1 0 S 7-bit data MPB STOP 1 -- 1 1 S 7-bit data MPB STOP STOP Legend S: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit Rev. 2.0, 06/04, page 487 of 980 Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in SMR and bits CKE1 and CKE0 in SCR. For details of SCI clock source selection, see table 13.9. When an external clock is input at the SCK pin, it must have a frequency 16 times the desired bit rate. When the SCI is operated on an internal clock, it can output a clock signal at the SCK pin. The frequency of this output clock is equal to the bit rate. The phase is aligned as shown in figure 13.3 so that the rising edge of the clock occurs at the center of each transmit data bit. 0 D0 D1 D2 D3 D4 1frame D5 D6 D7 0/1 1 1 Figure 13.3 Phase Relationship between Output Clock and Serial Data (Asynchronous Mode) Transmitting and Receiving Data: * SCI Initialization (Asynchronous Mode): Before transmitting or receiving data, clear the TE and RE bits to 0 in SCR, then initialize the SCI as follows. When changing the communication mode or format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 sets the TDRE flag to 1 and initializes TSR. Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags, or RDR, which retain their previous contents. When an external clock is used the clock should not be stopped during initialization or subsequent operation, since operation will be unreliable in this case. Rev. 2.0, 06/04, page 488 of 980 Figure 13.4 shows a sample flowchart for initializing the SCI. Start of initialization Clear TE and RE bits to 0 in SCR Set CKE1 and CKE0 bits in SCR (leaving TE and RE bits cleared to 0) Select communication format in SMR Set value in BRR Wait No 1-bit interval elapsed? (4) Yes Set TE or RE bit to 1 in SCR Set the RIE, TIE, TEIE, and MPIE bits (4) (1) (1) Set the clock source in SCR. Clear the RIE, TIE, TEIE, MPIE, TE, and RE bits to 0. If clock output is selected in asynchronous mode, clock output starts immediately after the setting is made in SCR. Select the communication format in SMR. (2) (2) (3) (3) Write the value corresponding to the bit rate in BRR. This step is not necessary when an external clock is used. Wait for at least the interval required to transmit or receive one bit, then set the TE or RE bit to 1 in SCR. Set the RIE, TIE, TEIE, and MPIE bits as necessary. Setting the TE or RE bit enables the SCI to use the TxD or RxD pin. Figure 13.4 Sample Flowchart for SCI Initialization Rev. 2.0, 06/04, page 489 of 980 * Transmitting Serial Data (Asynchronous Mode): Figure 13.5 shows a sample flowchart for transmitting serial data and indicates the procedure to follow. (1) SCI initialization: the transmit data output function of the TxD pin is selected automatically. Transmission is possible after the TE bit is set to 1 and 1 is output for one frame. (2) SCI status check and transmit data write: read SSR and check that the TDRE flag is set to 1, then write transmit data in TDR and clear the TDRE flag to 0. (3) To continue transmitting serial data: after checking that the TDRE flag is 1, indicating that data can be written, write data in TDR, then clear the TDRE flag to 0. When the DMAC is activated by a transmit-data-empty interrupt request (TXI) to write data in TDR, the TDRE flag is checked and cleared automatically. (3) (4) To output a break signal at the end of serial transmission: set the DDR bit to 1 and clear the DR bit to 0, then clear the TE bit to 0 in SCR. Initialize Start transmitting (1) Read TDRE flag in SSR No (2) TDRE = 1 Yes Write transmit data in TDR and clear TDRE flag to 0 in SSR All data transmitted? Yes Read TEND flag in SSR No TEND = 1 Yes Output break signal? Yes Clear DR bit to 0 and set DDR bit to 1 No No (4) Clear TE bit to 0 in SCR Figure 13.5 Sample Flowchart for Transmitting Serial Data Rev. 2.0, 06/04, page 490 of 980 In transmitting serial data, the SCI operates as follows: * The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. * After loading the data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transmit-data-empty interrupt (TXI) at this time. Serial transmit data is transmitted in the following order from the TxD pin: Start bit: One 0 bit is output. Transmit data: 7 or 8 bits are output, LSB first. Parity bit or multiprocessor bit: One parity bit (even or odd parity),or one multiprocessor bit is output. Formats in which neither a parity bit nor a multiprocessor bit is output can also be selected. Stop bit(s): One or two 1 bits (stop bits) are output. Mark state: Output of 1 bits continues until the start bit of the next transmit data. * The SCI checks the TDRE flag when it outputs the stop bit. If the TDRE flag is 0, the SCI loads new data from TDR into TSR, outputs the stop bit, then begins serial transmission of the next frame. If the TDRE flag is 1, the SCI sets the TEND flag to 1 in SSR, outputs the stop bit, then continues output of 1 bits in the mark state. If the TEIE bit is set to 1 in SCR, a transmit-end interrupt (TEI) is requested at this time. Figure 13.6 shows an example of SCI transmit operation in asynchronous mode. Data Parity Stop Start bit bit bit Data Parity Stop bit bit 1 Start bit 1 0 D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 1 Idle state (mark state) TDRE TEND 1 frame TXI interrupt request TXI interrupt handler writes data in TDR and clears TDRE flag to 0 TXI interrupt request TEI interrupt request Figure 13.6 Example of SCI Transmit Operation in Asynchronous Mode (8-Bit Data with Parity and One Stop Bit) Rev. 2.0, 06/04, page 491 of 980 * Receiving Serial Data (Asynchronous Mode): Figure 13.7 shows a sample flowchart for receiving serial data and indicates the procedure to follow. Initialize Start receiving (1) (1) SCI initialization: the receive data input function of the RxD pin is selected automatically. Receive error handling and break detection: if a receive error occurs, read the ORER, PER, and FER flags in SSR to identify the error. After executing the necessary error handling, clear the ORER, PER, and FER flags all to 0. Receiving cannot resume if any of these flags remains set to 1. When a framing error occurs, the RxD pin can be read to detect the break state. (2)(3) Read ORER, PER, and FER flags in SSR (2) PERFEROPER = 1 Yes (3) No Error handling (continued on next page) Read RDRF flag in SSR No (4) (4) RDRF = 1 Yes SCI status check and receive data read: read SSR, check that the RDRF flag is set to 1, then read receive data from RDR and clear the RDRF flag to 0. Notification that the RDRF flag has changed from 0 to 1 can also be given by the RXI interrupt. To continue receiving serial data: check the RDRF flag, read RDR, and clear the RDRF flag to 0 before the stop bit of the current frame is received. When the DMAC is activated by a receive-data-full interrupt request (RXI) to read RDR, the RDRF flag is cleared automatically. Read receive data from RDR, and clear RDRF flag to 0 in SSR (5) No All data received? Yes Clear RE bit to 0 in SCR (5) Figure 13.7 Sample Flowchart for Receiving Serial Data (1) Rev. 2.0, 06/04, page 492 of 980 (3) Error handling No ORER = 1 Yes Overrun error handling No FER = 1 Yes Break? No Framing error handling Clear RE bit to 0 in SCR Yes No PER = 1 Yes Parity error handling Clear ORER, PER, and FER flags to 0 in SSR Figure 13.7 Sample Flowchart for Receiving Serial Data (2) Rev. 2.0, 06/04, page 493 of 980 In receiving, the SCI operates as follows: * The SCI monitors the communication line. When it detects a start bit (0 bit), the SCI synchronizes internally and starts receiving. * Receive data is stored in RSR in order from LSB to MSB. * The parity bit and stop bit are received. After receiving these bits, the SCI carries out the following checks: Parity check: The number of 1s in the receive data must match the even or odd parity setting of in the O/E bit in SMR. Stop bit check: The stop bit value must be 1. If there are two stop bits, only the first is checked. Status check: The RDRF flag must be 0, indicating that the receive data can be transferred from RSR into RDR. If these all checks pass, the RDRF flag is set to 1 and the received data is stored in RDR. If one of the checks fails (receive error*), the SCI operates as shown in table 13.11. Note: * When a receive error occurs, further receiving is disabled. In receiving, the RDRF flag is not set to 1. Be sure to clear the error flags to 0. * When the RDRF flag is set to 1, if the RIE bit is set to 1 in SCR, a receive-data-full interrupt (RXI) is requested. If the ORER, PER, or FER flag is set to 1 and the RIE bit in SCR is also set to 1, a receive-error interrupt (ERI) is requested. Table 13.11 Receive Error Conditions Receive Error Abbreviation Condition Overrun error ORER Framing error FER Parity error PER Data Transfer Receiving of next data ends while Receive data is not transferred RDRF flag is still set to 1 in SSR from RSR to RDR Stop bit is 0 Receive data is transferred from RSR to RDR Parity of received data differs from Receive data is transferred from even/odd parity setting in SMR RSR to RDR Rev. 2.0, 06/04, page 494 of 980 Figure 13.8 shows an example of SCI receive operation in asynchronous mode. Start bit Parity Stop bit bit Start bit Stop Parity Stop bit bit bit 1 Data Data 1 0 D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 1 Idle (mark) state RDRF FER RXI request 1 frame RXI interrupt handler reads data in RDR and clears RDRF flag to 0 Framing error, ERI request Figure 13.8 Example of SCI Receive Operation (8-Bit Data with Parity and One Stop Bit) 13.3.3 Multiprocessor Communication The multiprocessor communication function enables several processors to share a single serial communication line. The processors communicate in asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format). In multiprocessor communication, each receiving processor is addressed by an ID. A serial communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending cycles. The transmitting processor stars by sending the ID of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor sends transmit data with the multiprocessor bit cleared to 0. Receiving processors skip incoming data until they receive data with the multiprocessor bit set to 1. When they receive data with the multiprocessor bit set to 1, receiving processors compare the data with their IDs. Processors with IDs not matching the received data skip further incoming data until they again receive data with the multiprocessor bit set to 1. Multiple processors can send and receive data in this way. Figure 13.9 shows an example of communication among different processors using a multiprocessor format. Rev. 2.0, 06/04, page 495 of 980 Communication Formats: Four formats are available. Parity bit settings are ignored when a multiprocessor format is selected. For details see table 13.10. Clock: See the description of asynchronous mode. Transmitting processor Serial communication line Receiving processor A (ID=01) Receiving processor B (ID=02) Receiving processor C (ID=03) Receiving processor D (ID=04) Serial data H'01 (MPB=1) ID-sending cycle: receiving processor address H'AA (MPB=0) Data-sending cycle: data sent to receiving processor specified by ID Legend MPB : Multiprocessor bit Figure 13.9 Example of Communication among Processors using Multiprocessor Format (Sending Data H'AA to Receiving Processor A) Transmitting and Receiving Data: * Transmitting Multiprocessor Serial Data: Figure 13.10 shows a sample flowchart for transmitting multiprocessor serial data and indicates the procedure to follow. Rev. 2.0, 06/04, page 496 of 980 Initialize Start transmitting (1) (1) SCI initialization: the transmit data output function of the TxD pin is selected automatically. SCI status check and transmit data write: read SSR, check that the TDRE flag is 1, then write transmit data in TDR. Also set the MPBT flag to 0 or 1 in SSR. Finally, clear the TDRE flag to 0. To continue transmitting serial data: after checking that the TDRE flag is 1, indicating that data can be written, write data in TDR, then clear the TDRE flag to 0. When the DMAC is activated by a transmit-dataempty interrupt request (TXI) to write data in TDR, the TDRE flag is checked and cleared automatically. To output a break signal at the end of serial transmission: set the DDR bit to 1 and clear the DR bit to 0, then clear the TE bit to 0 in SCR. (2) Read TDRE flag in SSR (2) TDRE = 1 Yes Write transmit data in TDR and set MPBT bit in SSR Clear TDRE flag to 0 No (3) (4) No All data transmitted? Yes (3) Read TEND flag in SSR No TEND = 1 Yes Output break signal? Yes No (4) Clear DR bit to 0 and set DDR to 1 Clear TE bit to 0 in SCR Figure 13.10 Sample Flowchart for Transmitting Multiprocessor Serial Data Rev. 2.0, 06/04, page 497 of 980 In transmitting serial data, the SCI operates as follows: * The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. * After loading the data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transmit-data-empty interrupt (TXI) at this time. Serial transmit data is transmitted in the following order from the TxD pin: Start bit: One 0 bit is output. Transmit data: 7 or 8 bits are output, LSB first. Multiprocessor bit: One multiprocessor bit (MPBT value) is output. Stop bit(s): One or two 1 bits (stop bits) are output. Mark state: Output of 1 bits continues until the start bit of the next transmit data. * The SCI checks the TDRE flag when it outputs the stop bit. If the TDRE flag is 0, the SCI loads new data from TDR into TSR, outputs the stop bit, then begins serial transmission of the next frame. If the TDRE flag is 1, the SCI sets the TEND flag to 1 in SSR, outputs the stop bit, then continues output of 1 bits in the mark state. If the TEIE bit is set to 1 in SCR, a transmit-end interrupt (TEI) is requested at this time. Figure 13.11 shows an example of SCI transmit operation using a multiprocessor format. Multiprocessor Stop Start bit bit bit Multiprocessor Stop bit bit 1 Start bit Data Data 0 TDRE TEND D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 1 Idle (mark) state TXI interrupt TXI interrupt handler writes data in TDR and request clears TDRE flag to 0 1 frame TXI interrupt request TEI interrupt request Figure 13.11 Example of SCI Transmit Operation (8-Bit Data with Multiprocessor Bit and One Stop Bit) * Receiving Multiprocessor Serial Data: Figure 13.12 shows a sample flowchart for receiving multiprocessor serial data and indicates the procedure to follow. Rev. 2.0, 06/04, page 498 of 980 Initialize Start receiving (1) (1) SCI initialization: the receive data input function of the RxD pin is selected automatically. ID receive cycle: set the MPIE bit to 1 in SCR. SCI status check and ID check: read SSR, check that the RDRF flag is set to 1, then read data from RDR and compare it with the processor's own ID. If the ID does not match, set the MPIE bit to 1 again and clear the RDRF flag to 0. If the ID matches, clear the RDRF flag to 0. SCI status check and data receiving: read SSR, check that the RDRF flag is set to 1, then read data from RDR. Receive error handling and break detection: if a receive error occurs, read the ORER and FER flags in SSR to identify the error. After executing the necessary error handling, clear the ORER and FER flags both to 0. Receiving cannot resume while either the ORER or FER flag remains set to 1. When a framing error occurs, the RxD pin can be read to detect the break state. (2) Set MPIE bit to 1 in SCR Read ORER and FER flags in SSR (2) (3) FERORER = 1 No Read RDRF flag in SSR Yes (4) (3) (5) No RDRF = 1 Yes Read RDRF flag in SSR No Own ID? Yes Read ORER and FER flags in SSR FERORER = 1 No Read RDRF flag in SSR No (4) Yes RDRF = 1 Yes Read receive data from RDR No Finished receiving? Yes Clear RE bit to 0 in SCR (5) Error handling (continued on next page) Figure 13.12 Sample Flowchart for Receiving Multiprocessor Serial Data (1) Rev. 2.0, 06/04, page 499 of 980 (5) Error handling No ORER = 1 Yes Overrun error handling No FER = 1 Yes Break? No Clear RE bit to 0 in SCR Framing error handling Yes Clear ORER, PER, and FER flags to 0 in SSR Figure 13.12 Sample Flowchart for Receiving Multiprocessor Serial Data (2) Rev. 2.0, 06/04, page 500 of 980 Figure 13.13 shows an example of SCI receive operation using a multiprocessor format. Start bit Stop Start bit Stop 1 Data (ID1) MPB bit D7 1 Data (data1) MPB bit D7 0 1 0 D0 D1 1 0 D0 D1 1 Idle (mark) state MPIE RDRF RDR value MPB detection MPIE = 0 RXI interrupt request (multiprocessor interrupt) RXI interrupt handler reads RDR data and clears RDRF flag to 0 ID1 Not own ID, so MPIE bit is set to 1 again No RXI interrupt request, RDR not updated a. Own ID does not match data 1 Start bit Data (ID2) MPB D7 1 Stop bit Start bit Data (data1) MPB D7 0 Stop bit 1 0 D0 D1 1 0 D0 D1 1 Idle (mark) state MPIE RDRF RDR value ID1 ID2 Data2 MPB detection MPIE = 0 RXI interrupt request (multiprocessor interrupt) RXI interrupt handler reads RDR data and clears RDRF flag to 0 Own ID, so receiving MPIE bit is set to continues, with data 1 again received by RXI interrupt handler b. Own ID matches data Figure 13.13 Example of SCI Receive Operation (8-Bit Data with Multiprocessor Bit and One Stop Bit) 13.3.4 Synchronous Operation In synchronous mode, the SCI transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCI transmitter and receiver share the same clock but are otherwise independent, so fullduplex communication is possible. The transmitter and the receiver are also double-buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress. Rev. 2.0, 06/04, page 501 of 980 Figure 13.14 shows the general format in synchronous serial communication. One unit (character or frame) of transfer data * Serial clock LSB MSB * Serial data Don't care Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Don't care Note: * High except in continuous transmitting or receiving Figure 13.14 Data Format in Synchronous Communication In synchronous serial communication, each data bit is placed on the communication line from one falling edge of the serial clock to the next. Data is guaranteed valid at the rise of the serial clock. In each character, the serial data bits are transferred in order from LSB (first) to MSB (last). After output of the MSB, the communication line remains in the state of the MSB. In synchronous mode the SCI receives data by synchronizing with the rise of the serial clock. Communication Format: The data length is fixed at 8 bits. No parity bit or multiprocessor bit can be added. Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected by means of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. See table 13.6 for details of SCI clock source selection. When the SCI operates on an internal clock, it outputs the clock source at the SCK pin. Eight clock pulses are output per transmitted or received character. When the SCI is not transmitting or receiving, the clock signal remains in the high state. If receiving in single-character units is required, an external clock should be selected. Transmitting and Receiving Data: * SCI Initialization (Synchronous Mode): Before transmitting or receiving data, clear the TE and RE bits to 0 in SCR, then initialize the SCI as follows. When changing the communication mode or format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 sets the TDRE flag to 1 and initializes TSR. Note that clearing RE to 0, however, does not initialize the RDRF, PER, and ORE flags, or RDR, which retain their previous contents. Rev. 2.0, 06/04, page 502 of 980 Figure 13.15 shows a sample flowchart for initializing the SCI. (1) Set the clock source in SCR. Clear the RIE, TIE, TEIE, MPIE, TE, and RE bits to 0.* Select the communication format in SMR. Write the value corresponding to the bit rate in BRR. This step is not necessary when an external clock is used. Wait for at least the interval required to transmit or receive one bit, then set the TE or RE bit to 1 in SCR.* Set the RIE, TIE, TEIE, and MPIE bits as necessary. Setting the TE or RE bit enables the SCI to use the TxD or RxD pin. Start of initialization Clear TE and RE bits to 0 in SCR (2) (3) Set RIE, TIE, TEIE, MPIE, CKE1, and CKE0 bits in SCR (leaving TE and RE bits cleared to 0) Select communication format in SMR Set value in BRR Wait 1-bit interval elapsed? Yes Set TE or RE bit to 1 in SCR Set RIE, TIE, TEIE, and MPIE bits as necessary (1) (4) (2) (3) Note: * In simultaneous transmitting and receiving, the TE and RE bits should be cleared to 0 or set to 1 simultaneously. No (4) Figure 13.15 Sample Flowchart for SCI Initialization Rev. 2.0, 06/04, page 503 of 980 * Transmitting Serial Data (Synchronous Mode): Figure 13.16 shows a sample flowchart for transmitting serial data and indicates the procedure to follow. (1) SCI initialization: the transmit data output function of the TxD pin is selected automatically. SCI status check and transmit data write: read SSR, check that the TDRE flag is 1, then write transmit data in TDR and clear the TDRE flag to 0. To continue transmitting serial data: after checking that the TDRE flag is 1, indicating that data can be written, write data in TDR, then clear the TDRE flag to 0. When the DMAC is activated by a transmit-data-empty interrupt request (TXI) to write data in TDR, the TDRE flag is checked and cleared automatically. Initialize Start transmitting (1) (2) Read TDRE flag in SSR (2) TDRE = 1 Yes No (3) Write transmit data in TDR and clear TDRE flag to 0 in SSR All data transmitted? Yes Read TEND flag in SSR No (3) TEND = 1 Yes Clear TE bit to 0 in SCR No Figure 13.16 Sample Flowchart for Serial Transmitting Rev. 2.0, 06/04, page 504 of 980 In transmitting serial data, the SCI operates as follows. * The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. * After loading the data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transmit-data-empty interrupt (TXI) at this time. If clock output is selected, the SCI outputs eight serial clock pulses. If an external clock source is selected, the SCI outputs data in synchronization with the input clock. Data is output from the TxD pin n order from LSB (bit 0) to MSB (bit 7). * The SCI checks the TDRE flag when it outputs the MSB (bit 7). If the TDRE flag is 0, the SCI loads data from TDR into TSR and begins serial transmission of the next frame. If the TDRE flag is 1, the SCI sets the TEND flag to 1 in SSR, and after transmitting the MSB (bit 7), holds the TxD pin in the MSB state. If the TEIE bit is set to 1 in SCR, a transmit-end interrupt (TEI) is requested at this time * After the end of serial transmission, the SCK pin is held in a constant state. Figure 13.17 shows an example of SCI transmit operation. Transmit direction Serial clock Serial data TDRE TEND TXI interrupt request Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TXI interrupt handler TXI interrupt writes data in TDR request and clears TDRE flag to 0 1 frame TEI interrupt request Figure 13.17 Example of SCI Transmit Operation * Receiving Serial Data (Synchronous Mode): Figure 13.18 shows a sample flowchart for receiving serial data and indicates the procedure to follow. When switching from asynchronous to synchronous mode. make sure that the ORER, PER, and FER flags are cleared to 0. If the FER or PER flag is set to 1 the RDRF flag will not be set and both transmitting and receiving will be disabled. Rev. 2.0, 06/04, page 505 of 980 Initialize Start receiving (1) (1) SCI initialization: the receive data input function of the RxD pin is selected automatically. Read ORER flag in SSR (2) ORER = 1 No Yes (3) Error handling (continued on next page) (2)(3) Receive error handling: if a receive error occurs, read the ORER flag in SSR, then after executing the necessary error handling, clear the ORER flag to 0. Neither transmitting nor receiving can resume while the ORER flag remains set to 1. (4) SCI status check and receive data read: read SSR, check that the RDRF flag is set to 1, then read receive data from RDR and clear the RDRF flag to 0. Notification that the RDRF flag has changed from 0 to 1 can also be given by the RXI interrupt. To continue receiving serial data: check the RDRF flag, read RDR, and clear the RDRF flag to 0 before the MSB (bit 7) of the current frame is received. When the DMAC is activated by a receive-data-full interrupt request (RXI) to read RDR, the RDRF flag is cleared automatically. Read RDRF flag in SSR No (4) RDRF = 1 Yes Read receive data from RDR, and clear RDRF flag to 0 in SSR (5) No Finished receiving? Yes Clear RE bit to 0 in SCR (5) Figure 13.18 Sample Flowchart for Serial Receiving (1) Rev. 2.0, 06/04, page 506 of 980 (3) Error handling Overrun error handling Clear ORER flag to 0 in SSR Figure 13.18 Sample Flowchart for Serial Receiving (2) In receiving, the SCI operates as follows: * The SCI synchronizes with serial clock input or output and synchronizes internally. * Receive data is stored in RSR in order from LSB to MSB. After receiving the data, the SCI checks that the RDRF flag is 0, so that receive data can be transferred from RSR to RDR. If this check passes, the RDRF flag is set to 1 and the received data is stored in RDR. If the checks fails (receive error), the SCI operates as shown in table 13.11. When a receive error has been identified in the error check, subsequent transmit and receive operations are disabled. * When the RDRF flag is set to 1, if the RIE bit is set to 1 in SCR, a receive-data-full interrupt (RXI) is requested. If the ORER flag is set to 1 and the RIE bit in SCR is also set to 1, a receive-error interrupt (ERI) is requested. Rev. 2.0, 06/04, page 507 of 980 Figure 13.19 shows an example of SCI receive operation. Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDRF ORER RXI interrupt request RXI interrupt handler reads data in RDR and clears RDRF flag to 0 1 frame RXI interrupt request Overrun error, ERI interrupt request Figure 13.19 Example of SCI Receive Operation Rev. 2.0, 06/04, page 508 of 980 * Transmitting and Receiving Data Simultaneously (Synchronous Mode): Figure 13.20 shows a sample flowchart for transmitting and receiving serial data simultaneously and indicates the procedure to follow. (1) Initialize Start of transmitting and receiving (1) SCI initialization: the transmit data output function of the TxD pin and the read data input function of the RxD pin are selected, enabling simultaneous transmitting and receiving. SCI status check and transmit data write: read SSR, check that the TDRE flag is 1, then write transmit data in TDR and clear the TDRE flag to 0. Notification that the TDRE flag has changed from 0 to 1 can also be given by the TXI interrupt. Receive error handling: if a receive error occurs, read the ORER flag in SSR, then after executing the necessary error handling, clear the ORER flag to 0. Neither transmitting nor receiving can resume while the ORER flag remains set to 1. SCI status check and receive data read: read SSR, check that the RDRF flag is 1, then read receive data from RDR and clear the RDRF flag to 0. Notification that the RDRF flag has changed from 0 to 1 can also be given by the RXI interrupt. To continue transmitting and receiving serial data: check the RDRF flag, read RDR, and clear the RDRF flag to 0 before the MSB (bit 7) of the current frame is received. Also check that the TDRE flag is set to 1, indicating that data can be written, write data in TDR, then clear the TDRE flag to 0 before the MSB (bit 7) of the current frame is transmitted. When the DMAC is activated by a transmitdata-empty interrupt request (TXI) to write data in TDR, the TDRE flag is checked and cleared automatically. When the DMAC is activated by a receive-data-full interrupt request (RXI) to read RDR, the RDRF flag is cleared automatically. Read TDRE flag in SSR (2) (2) No TDRE = 1 Yes (3) Write transmit data in TDR and clear TDRE flag to 0 in SSR (4) Read ORER flag in SSR Yes (3) No Error handling (4) (5) ORER = 1 Read RDRF flag in SSR No RDRF = 1 Yes Read receive data from RDR, and clear RDRF flag to 0 in SSR No End of transmitting and receiving? Yes (5) Clear TE and RE bits to 0 in SCR Figure 13.20 Sample Flowchart for Simultaneous Serial Transmitting and Receiving Rev. 2.0, 06/04, page 509 of 980 13.4 SCI Interrupts The SCI has four interrupt request sources: the transmit-end interrupt (TEI), receive-error interrupt (ERI), receive-data-full interrupt (RXI), and transmit-data-empty interrupt (TXI). Table 13.12 lists the interrupt sources and indicates their priority. These interrupts can be enabled or disabled by the TIE, RIE, and TEIE bits in SCR. Each interrupt request is sent separately to the interrupt controller. A TXI interrupt is requested when the TDRE flag is set to 1 in SSR. A TEI interrupt is requested when the TEND flag is set to 1 in SSR. A TXI interrupt request can activate the DMAC to transfer data. Data transfer by the DMAC automatically clears the TDRE flag to 0. A TEI interrupt request cannot activate the DMAC. An RXI interrupt is requested when the RDRF flag is set to 1 in SSR. An ERI interrupt is requested when the ORER, PER, or FER flag is set to 1 in SSR. An RXI interrupt can activate the DMAC to transfer data. Data transfer by the DMAC automatically clears the RDRF flag to 0. An ERI interrupt request cannot activate the DMAC. The DMAC can be activated by interrupts from SCI channel 0. Table 13.12 SCI Interrupt Sources Interrupt Source ERI RXI TXI TEI Description Receive error (ORER, FER, or PER) Receive data register full (RDRF) Transmit data register empty (TDRE) Transmit end (TEND) Low Priority High 13.5 13.5.1 Usage Notes Notes on Use of SCI Note the following points when using the SCI. TDR Write and TDRE Flag: The TDRE flag in SSR is a status flag indicating the loading of transmit data from TDR to TSR. The SCI sets the TDRE flag to 1 when it transfers data from TDR to TSR. Data can be written into TDR regardless of the state of the TDRE flag. If new data is written in TDR when the TDRE flag is 0, the old data stored in TDR will be lost because this data has not yet been transferred to TSR. Before writing transmit data in TDR, be sure to check that the TDRE flag is set to 1. Rev. 2.0, 06/04, page 510 of 980 Simultaneous Multiple Receive Errors: Table 13.13 shows the state of the SSR status flags when multiple receive errors occur simultaneously. When an overrun error occurs the RSR contents are not transferred to RDR, so receive data is lost. Table 13.13 SSR Status Flags and Transfer of Receive Data SSR Status Flags RDRF 1 0 0 1 1 0 1 ORER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 x x x Receive Data Transfer RSR RDR x Receive Errors Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error Notes: : Receive data is transferred from RSR to RDR. x : Receive data is not transferred from RSR to RDR. Break Detection and Processing: Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state the input from the RxD pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set. In the break state the SCI receiver continues to operate, so if the FER flag is cleared to 0 it will be set to 1 again. Sending a Break Signal: The input/output condition and level of the TxD pin are determined by DR and DDR bits. This feature can be used to send a break signal. After the serial transmitter is initialized, the DR value substitutes for the mark state until the TE bit is set to 1 (the TxD pin function is not selected until the TE bit is set to 1). The DDR and DR bits should therefore be set to 1 beforehand. To send a break signal during serial transmission, clear the DR bit to 0 , then clear the TE bit to 0. When the TE bit is cleared to 0 the transmitter is initialized, regardless of its current state, so the TxD pin becomes an input/output outputting the value 0. Rev. 2.0, 06/04, page 511 of 980 Receive Error Flags and Transmitter Operation (Synchronous Mode Only): When a receive error flag (ORER, PER, or FER) is set to 1 the SCI will not start transmitting, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 when starting to transmit. Note that clearing the RE bit to 0 does not clear the receive error flags to 0. Receive Data Sampling Timing in Asynchronous Mode and Receive Margin: In asynchronous mode the SCI operates on a base clock with 16 times the bit rate frequency. In receiving, the SCI synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the eighth base clock pulse. See figure 13.21. 16 clocks 8 clocks 0 7 15 0 7 15 0 Internal base clock Receive data (RxD) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 13.21 Receive Data Sampling Timing in Asynchronous Mode The receive margin in asynchronous mode can therefore be expressed as shown in equation (1). M= (0.5 - 1 2N ) - (L - 0.5) F - D - 0.5 N (1 + F) x 100% . . . . . . . . (1) M: N: D: L: F: Receive margin (%) Ratio of clock frequency to bit rate (N = 16) Clock duty cycle (L = 0 to 1.0) Frame length (L = 9 to 12) Absolute deviation of clock frequency Rev. 2.0, 06/04, page 512 of 980 From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2). D = 0.5, F = 0 M = (0.5 - 1 2 x 16 ) x 100% . . . . . . . . (2) = 46.875% This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%. Restrictions on Use of DMAC: * When an external clock source is used for the serial clock, after the DMAC updates TDR, allow an inversion of at least five system clock () cycles before input of the serial clock to start transmitting. If the serial clock is input within four states of the TDR update, a malfunction may occur (see figure 13.22) . * To have the DMAC read RDR, be sure to select the corresponding SCI receive-data-full interrupt (RXI) as the activation source with bits DTS2 to DTS0 in DTCR. SCK t TDRE D0 D1 D2 D3 D4 D5 D6 D7 Note: In operation with an external clock source, be sure that t >4 states. Figure 13.22 Example of Synchronous Transmission Using DMAC Rev. 2.0, 06/04, page 513 of 980 Switching from SCK Pin Function to Port Pin Function: * Problem in Operation: When switching the SCK pin function to the output port function (highlevel output) by making the following settings while DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1 (synchronous mode), low-level output occurs for one half-cycle. 1. End of serial data transmission 2. TE bit = 0 3. C/A bit = 0 ... switchover to port output 4. Occurrence of low-level output (see figure 13.23) Half-cycle low-level output SCK/port 1. End of transmission Data TE C/) CKE1 CKE0 Bit 6 Bit 7 2. TE= 0 4. Low-level output 3. C/)= 0 Figure 13.23 Operation when Switching from SCK Pin Function to Port Pin Function Rev. 2.0, 06/04, page 514 of 980 * Sample Procedure for Avoiding Low-Level Output: As this sample procedure temporarily places the SCK pin in the input state, the SCK/port pin should be pulled up beforehand with an external circuit. With DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1, make the following settings in the order shown. 1. End of serial data transmission 2. TE bit = 0 3. CKE1 bit = 1 4. C/A bit = 0 ... switchover to port output 5. CKE1 bit = 0 High-level output TE SCK/port 1. End of transmission Data TE C/A 3. CKE1= 1 CKE1 CKE0 5. CKE1= 0 Bit 6 Bit 7 2. TE= 0 4. C/A= 0 Figure 13.24 Operation when Switching from SCK Pin Function to Port Pin Function (Example of Preventing Low-Level Output) Rev. 2.0, 06/04, page 515 of 980 Rev. 2.0, 06/04, page 516 of 980 Section 14 Smart Card Interface 14.1 Overview An IC card (smart card) interface conforming to the ISO/IEC 7816-3 (Identification Card) standard is supported as an extension of the serial communication interface (SCI) functions. Switchover between the normal serial communication interface and the smart card interface is controlled by a register setting. 14.1.1 Features Features of the smart card interface supported by the H8/3029 are listed below. * Asynchronous communication Data length: 8 bits Parity bit generation and checking Transmission of error signal (parity error) in receive mode Error signal detection and automatic data retransmission in transmit mode Direct convention and inverse convention both supported * Built-in baud rate generator allows any bit rate to be selected * Three interrupt sources There are three interrupt sources--transmit-data-empty, receive-data-full, and transmit/receive error--that can issue requests independently. The transmit-data-empty interrupt and receive-data-full interrupt can activate the DMA controller (DMAC) to execute data transfer. Rev. 2.0, 06/04, page 517 of 980 14.1.2 Block Diagram Figure 14.1 shows a block diagram of the smart card interface. Bus interface Module data bus Internal data bus RDR TDR RxD RSR TSR TxD Parity generation Parity check SCK Legend SCMR: RSR: RDR: TSR: TDR: SMR: SCR: SSR: BRR: SCMR SSR SCR SMR Transmission/ reception control BRR Baud rate generator /4 /16 /64 Clock External clock Smart card mode register Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register Serial status register Bit rate register TXI RXI ERI Figure 14.1 Block Diagram of Smart Card Interface 14.1.3 Pin Configuration Table 14.1 shows the smart card interface pins. Table 14.1 Smart Card Interface Pins Pin Name Serial clock pin Receive data pin Transmit data pin Abbreviation SCK RxD TxD I/O I/O Input Output Function Clock input/output Receive data input Transmit data output Rev. 2.0, 06/04, page 518 of 980 14.1.4 Register Configuration The smart card interface has the internal registers listed in table 14.2. The BRR, TDR, and RDR registers have their normal serial communication interface functions, as described in section 13, Serial Communication Interface. Table 14.2 Smart Card Interface Registers Channel 0 Address* H'FFFB0 H'FFFB1 H'FFFB2 H'FFFB3 H'FFFB4 H'FFFB5 H'FFFB6 1 H'FFFB8 H'FFFB9 H'FFFBA H'FFFBB H'FFFBC H'FFFBD H'FFFBE 2 H'FFFC0 H'FFFC1 H'FFFC2 H'FFFC3 H'FFFC4 H'FFFC5 H'FFFC6 1 Name Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Smart card mode register Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Smart card mode register Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Smart card mode register Abbreviation SMR BRR SCR TDR SSR RDR SCMR SMR BRR SCR TDR SSR RDR SCMR SMR BRR SCR TDR SSR RDR SCMR R/W R/W R/W R/W R/W R/(W)* R R/W R/W R/W R/W R/W R/(W)* R R/W R/W R/W R/W R/W R/(W)* R R/W 2 2 2 Initial Value H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 Notes: *1 Lower 20 bits of the address in advanced mode. *2 Only 0 can be written in bits 7 to 3, to clear the flags. Rev. 2.0, 06/04, page 519 of 980 14.2 Register Descriptions This section describes the new or modified registers and bit functions in the smart card interface. 14.2.1 Smart Card Mode Register (SCMR) SCMR is an 8-bit readable/writable register that selects smart card interface functions. Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 SDIR 0 R/W 2 SINV 0 R/W 1 -- 1 -- 0 SMIF 0 R/W Reserved bits Reserved bit Smart card interface mode select Enables or disables the smart card interface function Smart card data invert Inverts data logic levels Smart card data transfer direction Selects the serial/parallel conversion format SCMR is initialized to H'F2 by a reset and in standby mode. Bits 7 to 4--Reserved: Read-only bits, always read as 1. Bit 3--Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion 1 format.* Bit 3 SDIR 0 1 Description TDR contents are transmitted LSB-first Receive data is stored LSB-first in RDR TDR contents are transmitted MSB-first Receive data is stored MSB-first in RDR (Initial value) Rev. 2.0, 06/04, page 520 of 980 Bit 2--Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This function is used in combination with the SDIR bit to communicate with inverse-convention 2 cards.* The SINV bit does not affect the logic level of the parity bit. For parity settings, see section 14.3.4, Register Settings. Bit 2 SINV 0 1 Description Unmodified TDR contents are transmitted Receive data is stored unmodified in RDR Inverted TDR contents are transmitted Receive data is inverted before storage in RDR (Initial value) Bit 1--Reserved: Read-only bit, always read as 1. Bit 0--Smart Card Interface Mode Select (SMIF): Enables the smart card interface function. Bit 0 SMIF 0 1 Description Smart card interface function is disabled Smart card interface function is enabled (Initial value) Notes: *1 The function for switching between LSB-first and MSB-first mode can also be used with the normal serial communication interface. Note that when the communication format data length is set to 7 bits and MSB-first mode is selected for the serial data to be transferred, bit 0 of TDR is not transmitted, and only bits 7 to 1 of the received data are valid. *2 The data logic level inversion function can also be used with the normal serial communication interface. Note that, when inverting the serial data to be transferred, parity transmission and parity checking is based on the number of high-level periods at the serial data I/O pin, and not on the register value. 14.2.2 Serial Status Register (SSR) The function of SSR bit 4 is modified in smart card interface mode. This change also causes a modification to the setting conditions for bit 2 (TEND). Rev. 2.0, 06/04, page 521 of 980 Bit Initial value Read/Write 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 ERS 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W Transmit end Status flag indicating end of transmission Error signal status (ERS) Status flag indicating that an error signal has been received Note: * Only 0 can be written, to clear the flag. Bits 7 to 5: These bits operate as in normal serial communication. For details see section 13.2.7, Serial Status Register (SSR). Bit 4--Error Signal Status (ERS): In smart card interface mode, this flag indicates the status of the error signal sent from the receiving device to the transmitting device. The smart card interface does not detection framing errors. Bit 4 ERS 0 Description Indicates normal transmission, with no error signal returned [Clearing conditions] The chip is reset, or enters standby mode or module stop mode Software reads ERS while it is set to 1, then writes 0. 1 Indicates that the receiving device sent an error signal reporting a parity error [Setting condition] A low error signal was sampled. Note: Clearing the TE bit to 0 in SCR does not affect the ERS flag, which retains its previous value. (Initial value) Bits 3 to 0: These bits operate as in normal serial communication. For details see section 13.2.7, Serial Status Register (SSR). The setting conditions for transmit end (TEND), however, are modified as follows. Rev. 2.0, 06/04, page 522 of 980 Bit 2 TEND 0 Description Transmission is in progress [Clearing conditions] Software reads TDRE while it is set to 1, then writes 0 in the TDRE flag. The DMAC or DTC writes data in TDR. 1 End of transmission [Setting conditions] The chip is reset or enters standby mode. The TE bit and FER/ERS bit are both cleared to 0 in SCR. TDRE is 1 and ERS is 0 at a time 2.5 etu after the last bit of a 1-byte serial character is transmitted (normal transmission). (Initial value) Note: An etu (elementary time unit) is the time needed to transmit one bit. 14.2.3 Serial Mode Register (SMR) The function of SMR bit 7 is modified in smart card interface mode. This change also causes a modification to the function of bits 1 and 0 in the serial control register (SCR). Bit Initial value Read/Write 7 GM 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Bit 7--GSM Mode (GM): With the normal smart card interface, this bit is cleared to 0. Setting this bit to 1 selects GSM mode, an additional mode for controlling the timing for setting the TEND flag that indicates completion of transmission, and the type of clock output used. The details of the additional clock output control mode are specified by the CKE1 and CKE0 bits in the serial control register (SCR). Bit 7 GM 0 Description Normal smart card interface mode operation The TEND flag is set 12.5 etu after the beginning of the start bit. Clock output on/off control only. 1 GSM mode smart card interface mode operation The TEND flag is set 11.0 etu after the beginning of the start bit. Clock output on/off and fixed-high/fixed-low control. (Initial value) Rev. 2.0, 06/04, page 523 of 980 Bit 6: Only 0 should be written to this bit. Bits 5 to 2: These bits operate as in normal serial communication. For details see section 13.2.5, Serial Mode Register (SMR). Bits 1 and 0: Only 0 should be written to these bits. 14.2.4 Serial Control Register (SCR) The function of SCR bits 1 and 0 is modified in smart card interface mode Bit Initial value Read/Write 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W Bits 7 to 2: These bits operate as in normal serial communication. For details see section 13.2.6, Serial Control Register (SCR). Bits 1 and 0--Clock Enable 1 and 0 (CKE1, CKE0): These bits select the SCI clock source and enable or disable clock output from the SCK pin. In smart card interface mode, it is possible to specify a fixed high level or fixed low level for the clock output, in addition to the usual switching between enabling and disabling of the clock output. Bit 7 GM 0 1 1 Bit 1 CKE1 0 Bit 0 CKE0 0 1 0 1 0 1 Description Internal clock/SCK pin is I/O port Internal clock/SCK pin is clock output Internal clock/SCK pin is fixed at low output Internal clock/SCK pin is clock output Internal clock/SCK pin is fixed at high output Internal clock/SCK pin is clock output (Initial value) 14.3 14.3.1 Operation Overview The main features of the smart card interface are as follows. * One frame consists of 8-bit data plus a parity bit. Rev. 2.0, 06/04, page 524 of 980 * In transmission, a guard time of at least 2 etu (elementary time units: the time for transfer of one bit) is provided between the end of the parity bit and the start of the next frame. * If a parity error is detected during reception, a low error signal level is output for a1 etu period 10.5 etu after the start bit. * If an error signal is detected during transmission, the same data is transmitted automatically after the elapse of 2 etu or longer. * Only asynchronous communication is supported; there is no synchronous communication function. 14.3.2 Pin Connections Figure 14.2 shows a pin connection diagram for the smart card interface. In communication with a smart card, since both transmission and reception are carried out on a single data transmission line, the TxD pin and RxD pin should both be connected to this line. The data transmission line should be pulled up to VCC with a resistor. When the smart card uses the clock generated on the smart card interface, the SCK pin output is input to the CLK pin of the smart card. If the smart card uses an internal clock, this connection is unnecessary. The reset signal should be output from one of the H8/3029's generic ports. In addition to these pin connections, power and ground connections will normally also be necessary. VCC TxD RxD SCK H8/3029 chip Clock line Px (port) Reset line Data line I/O CLK RST Smart card Card-processing device Figure 14.2 Smart Card Interface Connection Diagram Note: A loop-back test can be performed by setting both RE and TE to 1 without connecting a smart card. Rev. 2.0, 06/04, page 525 of 980 14.3.3 Data Format Figure 14.3 shows the smart card interface data format. In reception in this mode, a parity check is carried out on each frame, and if an error is detected an error signal is sent back to the transmitting device to request retransmission of the data. In transmission, the error signal is sampled and the same data is retransmitted if the error signal is low. No parity error Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Output from transmitting device Parity error Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Output from transmitting device Output from receiving device Legend Ds: D0 to D7: Dp: DE: Start bit Data bits Parity bit Error signal Figure 14.3 Smart Card Interface Data Format The operating sequence is as follows. 1. When the data line is not in use it is in the high-impedance state, and is fixed high with a pullup resistor. 2. The transmitting device starts transfer of one frame of data. The data frame starts with a start bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp). 3. With the smart card interface, the data line then returns to the high-impedance state. The data line is pulled high with a pull-up resistor. 4. The receiving device carries out a parity check. If there is no parity error and the data is received normally, the receiving device waits for reception of the next data. If a parity error occurs, however, the receiving device outputs an error signal (DE, low-level) to request retransmission of the data. After outputting the error signal for the prescribed length of time, the receiving device places the signal line in the high-impedance state again. The signal line is pulled high again by a pull-up resistor. Rev. 2.0, 06/04, page 526 of 980 5. If the transmitting device does not receive an error signal, it proceeds to transmit the next data frame. If it receives an error signal, however, it returns to step 2 and transmits the same data again. 14.3.4 Register Settings Table 14.3 shows a bit map of the registers used in the smart card interface. Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described in this section. Table 14.3 Smart Card Interface Register Settings Bit Register Address* SMR BRR SCR TDR SSR RDR SCMR H'FFFB0 H'FFFB1 H'FFFB2 H'FFFB3 H'FFFB4 H'FFFB5 H'FFFB6 1 Bit 7 GM BRR7 TIE TDR7 TDRE RDR7 -- Bit 6 0 BRR6 RIE TDR6 RDRF RDR6 -- Bit 5 1 BRR5 TE TDR5 ORER RDR5 -- Bit 4 O/E BRR4 RE TDR4 ERS RDR4 -- Bit 3 1 BRR3 0 TDR3 PER RDR3 SDIR Bit 2 0 BRR2 0 TDR2 TEND RDR2 SINV Bit 1 CKS1 BRR1 CKE1* TDR1 0 RDR1 -- 2 Bit 0 CKS0 BRR0 CKE0 TDR0 0 RDR0 SMIF Notes: -- Unused bit. *1 Lower 20 bits of the address in advanced mode. *2 When GM is cleared to 0 in SMR, the CKE1 bit must also be cleared to 0. Serial Mode Register (SMR) Settings: Clear the GM bit to 0 when using the normal smart card interface mode, or set to 1 when using GSM mode. Clear the O/E bit to 0 if the smart card is of the direct convention type, or set to 1 if of the inverse convention type. Bits CKS1 and CKS0 select the clock source of the built-in baud rate generator. See section 14.3.5, Clock. Bit Rate Register (BRR) Settings: BRR is used to set the bit rate. See section 14.3.5, Clock, for the method of calculating the value to be set. Serial Control Register (SCR) Settings: The TIE, RIE, TE, and RE bits have their normal serial communication functions. See section 13, Serial Communication Interface, for details. The CKE1 and CKE0 bits specify clock output. To disable clock output, clear these bits to 00; to enable clock output, set these bits to 01. Clock output is not performed when the GM bit is set to 1 in SMR. Clock output can also be fixed low or high. Rev. 2.0, 06/04, page 527 of 980 Smart Card Mode Register (SCMR) Settings: Clear both the SDIR bit and SINV bit cleared to 0 if the smart card is of the direct convention type, and set both to 1 if of the inverse convention type. To use the smart card interface, set the SMIF bit to 1. The register settings and examples of starting character waveforms are shown below for two smart cards, one following the direct convention and one the inverse convention. 1. Direct Convention (SDIR = SINV = O/E = 0) (Z) A Ds Z D0 Z D1 A D2 Z D3 Z D4 Z D5 A D6 A D7 Z Dp (Z) State With the direct convention type, the logic 1 level corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order. In the example above, the first character data is H'3B. The parity bit is 1, following the even parity rule designated for smart cards. 2. Indirect Convention (SDIR = SINV = O/E = 1) (Z) A Ds Z D7 Z D6 A D5 A D4 A D3 A D2 A D1 A D0 Z Dp (Z) State With the indirect convention type, the logic 1 level corresponds to state A and the logic 0 level to state Z, and transfer is performed in MSB-first order. In the example above, the first character data is H'3F. The parity bit is 0, corresponding to state Z, following the even parity rule designated for smart cards. In the H8/3029, inversion specified by the SINV bit applies only to the data bits, D7 to D0. For parity bit inversion, the O/E bit in SMR must be set to odd parity mode. This applies to both transmission and reception. Rev. 2.0, 06/04, page 528 of 980 14.3.5 Clock Only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock for the smart card interface. The bit rate is set with the bit rate register (BRR) and the CKS1 and CKS0 bits in the serial mode register (SMR). The equation for calculating the bit rate is shown below. Table 14.5 shows some sample bit rates. If clock output is selected with CKE0 set to 1, a clock with a frequency of 372 times the bit rate is output from the SCK pin. B= 1488 x 22n-1 x (N + 1) x 106 where, N: BRR setting (0 N 255) B: Bit rate (bit/s) : Operating frequency (MHz) n: See table 14.4 Table 14.4 n-Values of CKS1 and CKS0 Settings n 0 1 2 3 1 CKS1 0 CKS0 0 1 0 1 Note: If the gear function is used to divide the clock frequency, use the divided frequency to calculate the bit rate. The equation above applies directly to 1/1 frequency division. Table 14.5 Bit Rates (bits/s) for Various BRR Settings (When n = 0) (MHz) N 0 1 2 10.00 13440.9 6720.4 4480.3 10.7136 14400.0 7200.0 4800.0 13.00 17473.1 8736.6 5824.4 14.2848 19200.0 9600.0 6400.0 16.00 21505.4 10752.7 7168.5 18.00 24193.5 12096.8 8064.5 20.00 26881.7 13440.9 8960.6 25.00 33602.2 16801.1 11200.7 Note: Bit rates are rounded off to one decimal place. Rev. 2.0, 06/04, page 529 of 980 The following equation calculates the bit rate register (BRR) setting from the operating frequency and bit rate. N is an integer from 0 to 255, specifying the value with the smaller error. N= 1488 x 22n-1 x B x 106 - 1 Table 14.6 BRR Settings for Typical Bit Rates (bits/s) (When n = 0) (MHz) 10.00 bit/s 9600 N Error 1 30 10.7136 N Error 1 25 13.00 N Error 1 8.99 14.2848 N Error 1 0.00 16.00 N Error 1 12.01 18.00 N Error 2 15.99 20.00 N Error 2 6.66 25.0 N Error 3 12.49 Table 14.7 Maximum Bit Rates for Various Frequencies (Smart Card Interface Mode) (MHz) 10.00 10.7136 13.00 14.2848 16.00 18.00 20.00 25.00 Maximum Bit Rate (bits/s) 13441 14400 17473 19200 21505 24194 26882 33602 N 0 0 0 0 0 0 0 0 n 0 0 0 0 0 0 0 0 The bit rate error is given by the following equation: Error (%) = 1488 x 22n-1 x B x (N + 1) x 106 - 1 x 100 Rev. 2.0, 06/04, page 530 of 980 14.3.6 Transmitting and Receiving Data Initialization: Before transmitting or receiving data, the smart card interface must be initialized as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. 1. Clear the TE and RE bits to 0 in the serial control register (SCR). 2. Clear error flags ERS, PER, and ORER to 0 in the serial status register (SSR). 3. Set the parity bit (O/E) and baud rate generator select bits (CKS1 and CKS0) in the serial mode register (SMR). Clear the C/A, CHR, and MP bits to 0, and set the STOP and PE bits to 1. 4. Set the SMIF, SDIR, and SINV bits in the smart card mode register (SCMR). When the SMIF bit is set to 1, the TxD pin and RxD pin are both switched from port to SCI pin functions and go to the high-impedance state. 5. Set a value corresponding to the desired bit rate in the bit rate register (BRR). 6. Set the CKE0 bit in SCR. Clear the TIE, RIE, TE, RE, MPIE, TEIE, and CKE1 bits to 0. If the CKE0 bit is set to 1, the clock is output from the SCK pin. 7. Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCR. Do not set the TE bit and RE bit at the same time, except for self-diagnosis. Transmitting Serial Data: As data transmission in smart card mode involves error signal sampling and retransmission processing, the processing procedure is different from that for the normal SCI. Figure 14.5 shows a sample transmission processing flowchart. 1. Perform smart card interface mode initialization as described in Initialization above. 2. Check that the ERS error flag is cleared to 0 in SSR. 3. Repeat steps 2 and 3 until it can be confirmed that the TEND flag is set to 1 in SSR. 4. Write the transmit data in TDR, clear the TDRE flag to 0, and perform the transmit operation. The TEND flag is cleared to 0. 5. To continue transmitting data, go back to step 2. 6. To end transmission, clear the TE bit to 0. The above processing may include interrupt handling DMA transfer. If transmission ends and the TEND flag is set to 1 while the TIE bit is set to 1 and interrupt requests are enabled, a transmit-data-empty interrupt (TXI) will be requested. If an error occurs in transmission and the ERS flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a transmit/receive-error interrupt (ERI) will be requested. The timing of TEND flag setting depends on the GM bit in SMR (see figure 14.4). Rev. 2.0, 06/04, page 531 of 980 If the TXI interrupt activates the DMAC, the number of bytes designated in the DMAC can be transmitted automatically, including automatic retransmission. For details, see Interrupt Operations and Data Transfer by DMAC in this section. Serial data Ds Dp DE Guard time (1) GM = 0 TEND 12.5 etu (2) GM = 1 TEND 11.0 etu Figure 14.4 Timing of TEND Flag Setting Rev. 2.0, 06/04, page 532 of 980 Start Initialization Start transmitting No ERS = 0? Yes Error handling No TEND = 1? Yes Write transmit data in TDR, and clear TDRE flag to 0 in SSR No All data transmitted? Yes No ERS = 0? Yes Error handling No TEND = 1? Yes Clear TE bit to 0 End Figure 14.5 Sample Transmission Processing Flowchart Rev. 2.0, 06/04, page 533 of 980 TDR 1. Data write 2. Transfer from TDR to TSR 3. Serial data output Data 1 Data 1 Data 1 TSR (shift register) Data 1 Data remains in TDR Data 1 I/O signal output In case of normal transmission: TEND flag is set In case of transmit error: ERS flag is set Steps 2 and 3 above are repeated until the TEND flag is set. Note: When the ERS flag is set, it should be cleared until transfer of the last bit (D7 in LSB-first transmission, D0 in MSB-first transmission) of the retransmit data to be transmitted next has been completed. Figure 14.6 Relation Between Transmit Operation and Internal Registers I/O data Ds Da Db Dc Dd De Df Dg Dh Dp DE Guard time TXI (TEND interrupt) 12.5 etu When GM = 0 11.0 etu When GM = 1 Figure 14.7 Timing of TEND Flag Setting Receiving Serial Data: Data reception in smart card mode uses the same processing procedure as for the normal SCI. Figure 14.8 shows a sample reception processing flowchart. 1. Perform smart card interface mode initialization as described in Initialization above. 2. Check that the ORER flag and PER flag are cleared to 0 in SSR. If either is set, perform the appropriate receive error handling, then clear both the ORER and the PER flag to 0. 3. Repeat steps 2 and 3 until it can be confirmed that the RDRF flag is set to 1. 4. Read the receive data from RDR. 5. To continue receiving data, clear the RDRF flag to 0 and go back to step 2. 6. To end reception, clear the RE bit to 0. Rev. 2.0, 06/04, page 534 of 980 Start Initialization Start receiving ORER = 0 and PER = 0? Yes No Error handling No RDRF = 1? Yes Read RDR and clear RDRF flag to 0 in SSR No All data received? Yes Clear RE bit to 0 Figure 14.8 Sample Reception Processing Flowchart The above procedure may include interrupt handling and DMA transfer. If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a receive-data-full interrupt (RXI) will be requested. If an error occurs in reception and either the ORER flag or the PER flag is set to 1, a transmit/receive-error interrupt (ERI) will be requested. If the RXI interrupt activates the DMAC, the number of bytes designated in the DMAC will be transferred, skipping receive data in which an error occurred. For details, see Interrupt Operations and Data Transfer by DMAC in this section. If a parity error occurs during reception and the PER flag is set to 1, the received data is transferred to RDR, so the erroneous data can be read. Rev. 2.0, 06/04, page 535 of 980 Switching Modes: When switching from receive mode to transmit mode, first confirm that the receive operation has been completed, then start from initialization, clearing RE to 0 and setting TE to 1. The RDRF, PER, or ORER flag can be used to check that the receive operation has been completed. When switching from transmit mode to receive mode, first confirm that the transmit operation has been completed, then start from initialization, clearing TE to 0 and setting RE to 1. The TEND flag can be used to check that the transmit operation has been completed. Fixing Clock Output: When the GM bit is set to 1 in SMR, clock output can be fixed by means of the CKE1 and CKE0 bits in SCR. The minimum clock pulse width can be set to the specified width in this case. Figure 14.9 shows the timing for fixing clock output. In this example, GM = 1, CKE1 = 0, and the CKE0 bit is controlled. Specified pulse width CKE1 value SCK Specified pulse width SCR write (CKE0 = 0) SCR write (CKE0 = 1) Figure 14.9 Timing for Fixing Cock Output Interrupt Operations: The smart card interface has three interrupt sources: transmit-data-empty (TXI), transmit/receive-error (ERI), and receive-data-full (RXI). The transmit-end interrupt request (TEI) is not available in smart card mode. A TXI interrupt is requested when the TEND flag is set to 1 in SSR. An RXI interrupt is requested when the RDRF flag is set to 1 in SSR. An ERI interrupt is requested when the ORER, PER, or ERS flag is set to 1 in SSR. These relationships are shown in table 14.8. Rev. 2.0, 06/04, page 536 of 980 Table 14.8 Smart Card Interface Mode Operating States and Interrupt Sources Operating State Transmit Mode Normal operation Error Receive Mode Normal operation Error Flag TEND ERS RDRF PER, ORER Enable Bit TIE RIE RIE RIE Interrupt Source TXI ERI RXI ERI DMAC Activation Available Not available Available Not available Data Transfer by DMAC: The DMAC can be used to transmit and receive data in smart card mode, as in normal SCI operations. In transmit mode, when the TEND flag is set to 1 in SSR, the TDRE flag is set simultaneously, generating a TXI interrupt. If the TXI request is designated beforehand as a DMAC activation source, the DMAC will be activated by the TXI request and will transfer the next transmit data. This data transfer by the DMAC automatically clears the TDRE and TEND flags to 0. In the event of an error, the SCI automatically retransmits the same data, keeping the TEND flag cleared to 0 so that the DMAC is not activated. The SCI and DMAC will therefore automatically transmit the designated number of bytes, including retransmission when an error occurs. When an error occurs, the ERS flag is not cleared automatically, so the RIE bit should be set to 1 to enable the error to generate an ERI request, and the ERI interrupt handler should clear ERS. When using the DMAC to transmit or receive, first set up and enable the DMAC, then make SCI settings. DMAC settings are described in section 7, DMA controller. In receive operations, an RXI interrupt is requested when the RDRF flag is set to 1 in SSR. If the RXI request is designated beforehand as a DMAC activation source, the DMAC will be activated by the RXI request and will transfer the received data. This data transfer by the DMAC automatically clears the RDRF flag to 0. When an error occurs, the RDRF flag is not set and an error flag is set instead. The DMAC is not activated. The ERI interrupt request is directed to the CPU. The ERI interrupt handler should clear the error flags. Rev. 2.0, 06/04, page 537 of 980 Examples of Operation in GSM Mode: When switching between smart card interface mode and software standby mode, use the following procedures to maintain the clock duty cycle. * Switching from smart card interface mode to software standby mode 1. Set the P94 data register (DR) and data direction register (DDR) to the values for the fixed output state in software standby mode. 2. Write 0 in the TE and RE bits in the serial control register (SCR) to stop transmit/receive operations. At the same time, set the CKE1 bit to the value for the fixed output state in software standby mode. 3. Write 0 in the CKE0 bit in SCR to stop the clock. 4. Wait for one serial clock cycle. During this period, the duty cycle is preserved and clock output is fixed at the specified level. 5. Write H'00 in the serial mode register (SMR) and smart card mode register (SCMR). 6. Make the transition to the software standby state. * Returning from software standby mode to smart card interface mode 1. Clear the software standby state. 2. Set the CKE1 bit in SCR to the value for the fixed output state at the start of software standby (the current P94 pin state). 3. Set smart card interface mode and output the clock. Clock signal generation is started with the normal duty cycle. Software standby Normal operation Normal operation (1) (2) (3) (4) (5) (6) (1) (2) (3) Figure 14.10 Procedure for Stopping and Restarting the Clock Use the following procedure to secure the clock duty cycle after powering on. 1. The initial state is port input and high impedance. Use pull-up or pull-down resistors to fix the potential. 2. Fix at the output specified by the CKE1 bit in SCR. 3. Set SMR and SCMR, and switch to smart card interface mode operation. 4. Set the CKE0 bit to 1 in SCR to start clock output. Rev. 2.0, 06/04, page 538 of 980 14.4 Usage Notes The following points should be noted when using the SCI as a smart card interface. Receive Data Sampling Timing and Receive Margin in Smart Card Interface Mode: In smart card interface mode, the SCI operates on a base clock with a frequency of 372 times the transfer rate. In reception, the SCI synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the 186th base clock pulse. The timing is shown in figure 14.11. 372 clocks 186 clocks 0 185 371 0 185 371 0 Internal base clock Receive data (RxD) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 14.11 Receive Data Sampling Timing in Smart Card Interface Mode Rev. 2.0, 06/04, page 539 of 980 The receive margin can therefore be expressed as follows. Receive margin in smart card interface mode: M = (0.5 - 1 2N ) - (L - 0.5) F - D - 0.5 N (1 + F) x 100% M: N: D: L: F: Receive margin (%) Ratio of clock frequency to bit rate (N = 372) Clock duty cycle (L = 0 to 1.0) Frame length (L =10) Absolute deviation of clock frequency From the above equation, if F = 0 and D = 0.5, the receive margin is as follows. When D = 0.5 and F = 0: M = (0.5 - 1/2 x 372) x 100% = 49.866% Retransmission: Retransmission is performed by the SCI in receive mode and transmit mode as described below. * Retransmission when SCI is in Receive Mode Figure 14.12 illustrates retransmission when the SCI is in receive mode. 1. If an error is found when the received parity bit is checked, the PER bit is automatically set to 1. If the RIE bit in SCR is set to the enable state, an ERI interrupt is requested. The PER bit should be cleared to 0 in SSR before the next parity bit sampling timing. 2. The RDRF bit in SSR is not set for the frame in which the error has occurred. 3. If no error is found when the received parity bit is checked, the PER bit is not set to 1 in SSR. 4. If no error is found when the received parity bit is checked, the receive operation is assumed to have been completed normally, and the RDRF bit is automatically set to 1 in SSR. If the RIE bit in SCR is set to the enable state, an RXI interrupt is requested. If RXI is enabled as a DMA transfer activation source, the RDR contents can be read automatically. When the DMAC reads the RDR data, the RDRF flag is automatically cleared to 0. 5. When a normal frame is received, the data pin is held in the high-impedance state at the error signal transmission timing. Rev. 2.0, 06/04, page 540 of 980 Frame n Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Retransmitted frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE) Frame n+1 Ds D0 D1 D2 D3 D4 RDRF [2] PER [1] [3] [4] Figure 14.12 Retransmission in SCI Receive Mode * Retransmission when SCI is in Transmit Mode Figure 14.13 illustrates retransmission when the SCI is in transmit mode. 6. If an error signal is sent back from the receiving device after transmission of one frame is completed, the ERS bit is set to 1 in SSR. If the RIE bit in SCR is set to the enable state, an ERI interrupt is requested. The ERS bit should be cleared to 0 in SSR before the next parity bit sampling timing. 7. The TEND bit in SSR is not set for the frame for which the error signal was received. 8. If an error signal is not sent back from the receiving device, the ERS flag is not set in SSR. 9. If an error signal is not sent back from the receiving device, transmission of one frame, including retransmission, is assumed to have been completed, and the TEND bit is set to 1 in SSR. If the TIE bit in SCR is set to the enable state, a TXI interrupt is requested. If TXI is enabled as a DMA transfer activation source, the next data can be written in TDR automatically. When the DMAC writes data in TDR, the TDRE bit is automatically cleared to 0. Frame n Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Retransmitted frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE) Frame n+1 Ds D0 D1 D2 D3 D4 TDRE Transfer from TDR to TSR TEND [7] ERS [6] [8] [9] Transfer from TDR to TSR Transfer from TDR to TSR Figure 14.13 Retransmission in SCI Transmit Mode Support of Block Transfer Mode: The smart card interface of this LSI supports an IC card (smart card) interface corresponding to T=0 (character transfer) in ISO/IEC 7816-3. Rev. 2.0, 06/04, page 541 of 980 Rev. 2.0, 06/04, page 542 of 980 Section 15 A/D Converter 15.1 Overview The H8/3029 includes a 10-bit successive-approximations A/D converter with a selection of up to eight analog input channels. When the A/D converter is not used, it can be halted independently to conserve power. For details see section 20.6, Module Standby Function. 15.1.1 Features A/D converter features are listed below. * 10-bit resolution * Eight input channels * Selectable analog conversion voltage range The analog voltage conversion range can be programmed by input of an analog reference voltage at the VREF pin. * High-speed conversion Conversion time: maximum 5.36 s per channel (with 25 MHz system clock) * Two conversion modes Single mode: A/D conversion of one channel Scan mode: continuous conversion on one to four channels * Four 16-bit data registers A/D conversion results are transferred for storage into data registers corresponding to the channels. * Sample-and-hold function * Three conversion start sources The A/D converter can be activated by software, an external trigger, or an 8-bit timer compare match. * A/D interrupt requested at end of conversion At the end of A/D conversion, an A/D end interrupt (ADI) can be requested. * DMA controller (DMAC) activation The DMAC can be activated at the end of A/D conversion. Rev. 2.0, 06/04, page 543 of 980 15.1.2 Block Diagram Figure 15.1 shows a block diagram of the A/D converter. Module data bus Bus interface ADDRC ADDRD ADCSR ADDRA ADDRB Internal data bus AVCC VREF AVSS 10-bit D/A Successiveapproximations register AN 0 AN 1 AN 2 AN 3 AN 4 AN 5 AN 6 AN 7 Analog multiplexer + - Comparator Control circuit Sample-andhold circuit /8 /4 ADCR ),64/ Compare match A0 ADTE 8-bit timer TCSR0 Legend ADCR: ADCSR: ADDRA: ADDRB: ADDRC: ADDRD: ADI interrupt signal A/D control register A/D control/status register A/D data register A A/D data register B A/D data register C A/D data register D Figure 15.1 A/D Converter Block Diagram Rev. 2.0, 06/04, page 544 of 980 15.1.3 Input Pins Table 15.1 summarizes the A/D converter's input pins. The eight analog input pins are divided into two groups: group 0 (AN0 to AN3), and group 1 (AN4 to AN7). AVCC and AVSS are the power supply for the analog circuits in the A/D converter. VREF is the A/D conversion reference voltage. Table 15.1 A/D Converter Pins Pin Name Analog power supply pin Analog ground pin Reference voltage pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 Abbreviation I/O AVCC AVSS VREF AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Input Input Input Input Input Input Input Input Input Input Input Input External trigger input for starting A/D conversion Group 1 analog inputs Function Analog power supply Analog ground and reference voltage Analog reference voltage Group 0 analog inputs A/D external trigger input pin ADTRG Rev. 2.0, 06/04, page 545 of 980 15.1.4 Register Configuration Table 15.2 summarizes the A/D converter's registers. Table 15.2 A/D Converter Registers Address* H'FFFE0 H'FFFE1 H'FFFE2 H'FFFE3 H'FFFE4 H'FFFE5 H'FFFE6 H'FFFE7 H'FFFE8 H'FFFE9 1 Name A/D data register A H A/D data register A L A/D data register B H A/D data register B L A/D data register C H A/D data register C L A/D data register D H A/D data register D L A/D control/status register A/D control register Abbreviation ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR R/W R R R R R R R R R/(W)* R/W 2 Initial Value H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'7E Notes: *1 Lower 20 bits of the address in advanced mode. *2 Only 0 can be written in bit 7, to clear the flag. Rev. 2.0, 06/04, page 546 of 980 15.2 15.2.1 Bit ADDRn Register Descriptions A/D Data Registers A to D (ADDRA to ADDRD) 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 -- 0 R AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 -- Initial value Read/Write (n = A to D) A/D conversion data 10-bit data giving an A/D conversion result Reserved bits The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the results of A/D conversion. An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data register corresponding to the selected channel. The upper 8 bits of the result are stored in the upper byte of the A/D data register. The lower 2 bits are stored in the lower byte. Bits 5 to 0 of an A/D data register are reserved bits that are always read as 0. Table 15.3 indicates the pairings of analog input channels and A/D data registers. The CPU can always read and write the A/D data registers. The upper byte can be read directly, but the lower byte is read through a temporary register (TEMP). For details see section 15.3, CPU Interface. The A/D data registers are initialized to H'0000 by a reset and in standby mode. Table 15.3 Analog Input Channels and A/D Data Registers Analog Input Channel Group 0 AN0 AN1 AN2 AN3 Group 1 AN4 AN5 AN6 AN7 A/D Data Register ADDRA ADDRB ADDRC ADDRD Rev. 2.0, 06/04, page 547 of 980 15.2.2 Bit A/D Control/Status Register (ADCSR) 7 ADF 0 R/(W) * 6 ADIE 0 R/W 5 ADST 0 R/W 4 SCAN 0 R/W 3 CKS 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W Initial value Read/Write Channel select 2 to 0 These bits select analog input channels Clock select Selects the A/D conversion time Scan mode Selects single mode or scan mode A/D start Starts or stops A/D conversion A/D interrupt enable Enables and disables A/D end interrupts A/D end flag Indicates end of A/D conversion Note: * Only 0 can be written, to clear the flag. ADCSR is an 8-bit readable/writable register that selects the mode and controls the A/D converter. ADCSR is initialized to H'00 by a reset and in standby mode. Rev. 2.0, 06/04, page 548 of 980 Bit 7--A/D End Flag (ADF): Indicates the end of A/D conversion. Bit 7 ADF 0 Description [Clearing condition] Read ADF when ADF =1, then write 0 in ADF. DMAC activated by ADI interrupt. [Setting conditions] Single mode: A/D conversion ends Scan mode: A/D conversion ends in all selected channels (Initial value) 1 Bit 6--A/D Interrupt Enable (ADIE): Enables or disables the interrupt (ADI) requested at the end of A/D conversion. Bit 6 ADIE 0 1 Description A/D end interrupt request (ADI) is disabled A/D end interrupt request (ADI) is enabled (Initial value) Bit 5--A/D Start (ADST): Starts or stops A/D conversion. The ADST bit remains set to 1 during A/D conversion. It can also be set to 1 by external trigger input at the ADTRG pin, or by an 8-bit timer compare match. Bit 5 ADST 0 1 Description A/D conversion is stopped (Initial value) Single mode: A/D conversion starts; ADST is automatically cleared to 0 when conversion ends. Scan mode: A/D conversion starts and continues, cycling among the selected channels, until ADST is cleared to 0 by software, by a reset, or by a transition to standby mode. Rev. 2.0, 06/04, page 549 of 980 Bit 4--Scan Mode (SCAN): Selects single mode or scan mode. For further information on operation in these modes, see section 15.4, Operation. Clear the ADST bit to 0 before switching the conversion mode. Bit 4 SCAN 0 1 Description Single mode Scan mode (Initial value) Bit 3--Clock Select (CKS): Selects the A/D conversion time. Clear the ADST bit to 0 before switching the conversion time. Bit 3 CKS 0 1 Description Conversion time = 134 states (maximum) Conversion time = 70 states (maximum) (Initial value) Bits 2 to 0--Channel Select 2 to 0 (CH2 to CH0): These bits and the SCAN bit select the analog input channels. Clear the ADST bit to 0 before changing the channel selection. Group Selection CH2 0 CH1 0 1 1 0 1 Channel Selection CH0 0 1 0 1 0 1 0 1 Single Mode AN0 (Initial value) AN1 AN2 AN3 AN4 AN5 AN6 AN7 Description Scan Mode AN0 AN0, AN1 AN0 to AN2 AN0 to AN3 AN4 AN4, AN5 AN4 to AN6 AN4 to AN7 Rev. 2.0, 06/04, page 550 of 980 15.2.3 Bit A/D Control Register (ADCR) 7 TRGE 0 R/W 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- Reserved bits Trigger enable Enables or disables starting of A/D conversion by an external trigger or 8-bit timer compare match 2 -- 1 R/W 1 -- 1 R/W 0 -- 0 R/W Initial value Read/Write ADCR is an 8-bit readable/writable register that enables or disables starting of A/D conversion by external trigger input or an 8-bit timer compare match signal. ADCR is initialized to H'7E by a reset and in standby mode. Bit 7--Trigger Enable (TRGE): Enables or disables starting of A/D conversion by an external trigger or 8-bit timer compare match. Bit 7 TRGE 0 1 Description Starting of A/D conversion by an external trigger or 8-bit timer compare match is disabled A/D conversion is started at the falling edge of the external trigger signal (ADTRG) or by an 8-bit timer compare match (Initial value) External trigger pin and 8-bit timer selection are performed by the 8-bit timer. For details, see section 10, 8-Bit Timers. Bits 6 to 3--Reserved: These bits cannot be modified and are always read as 1. Bit 2, 1--Reserved: These bits can be read or written, but must not be set to 0. Bit 0--Reserved: This bit can be read or written, but must not be set to 1. Rev. 2.0, 06/04, page 551 of 980 15.3 CPU Interface ADDRA to ADDRD are 16-bit registers, but they are connected to the CPU by an 8-bit data bus. Therefore, although the upper byte can be be accessed directly by the CPU, the lower byte is read through an 8-bit temporary register (TEMP). An A/D data register is read as follows. When the upper byte is read, the upper-byte value is transferred directly to the CPU and the lower-byte value is transferred into TEMP. Next, when the lower byte is read, the TEMP contents are transferred to the CPU. When reading an A/D data register, always read the upper byte before the lower byte. It is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. Figure 15.2 shows the data flow for access to an A/D data register. Upper-byte read CPU (H'AA) Module data bus Bus interface TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) (n = A to D) Lower-byte read CPU (H'40) Module data bus Bus interface TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) (n = A to D) Figure 15.2 A/D Data Register Access Operation (Reading H'AA40) Rev. 2.0, 06/04, page 552 of 980 15.4 Operation The A/D converter operates by successive approximations with 10-bit resolution. It has two operating modes: single mode and scan mode. 15.4.1 Single Mode (SCAN = 0) Single mode should be selected when only one A/D conversion on one channel is required. A/D conversion starts when the ADST bit is set to 1 by software, or by external trigger input. The ADST bit remains set to 1 during A/D conversion and is automatically cleared to 0 when conversion ends. When conversion ends the ADF bit is set to 1. If the ADIE bit is also set to 1, an ADI interrupt is requested at this time. To clear the ADF flag to 0, first read ADCSR, then write 0 in ADF. When the mode or analog input channel must be switched during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be set at the same time as the mode or channel is changed. Typical operations when channel 1 (AN1) is selected in single mode are described next. Figure 15.3 shows a timing diagram for this example. 1. Single mode is selected (SCAN = 0), input channel AN1 is selected (CH2 = CH1 = 0, CH0 = 1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1). 2. When A/D conversion is completed, the result is transferred into ADDRB. At the same time the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle. 3. Since ADF = 1 and ADIE = 1, an ADI interrupt is requested. 4. The A/D interrupt handling routine starts. 5. The routine reads ADCSR, then writes 0 in the ADF flag. 6. The routine reads and processes the conversion result (ADDRB). 7. Execution of the A/D interrupt handling routine ends. After that, if the ADST bit is set to 1, A/D conversion starts again and steps 2 to 7 are repeated. Rev. 2.0, 06/04, page 553 of 980 Set * ADIE A/D conversion starts Clear * Set * Set * ADST Clear * Rev. 2.0, 06/04, page 554 of 980 Idle Idle A/D conversion (1) ADF State of channel 0 (AN 0) Idle State of channel 1 (AN 1) Idle A/D conversion (2) Idle State of channel 2 (AN 2) Idle State of channel 3 (AN 3) ADDRA Read conversion result A/D conversion result (1) Read conversion result A/D conversion result (2) ADDRB ADDRC ADDRD Figure 15.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) Note: * Vertical arrows ( ) indicate instructions executed by software. 15.4.2 Scan Mode (SCAN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by software or external trigger input, A/D conversion starts on the first channel in the group (AN0 when CH2 = 0, AN4 when CH2 = 1). When two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (AN1 or AN5) starts immediately. A/D conversion continues cyclically on the selected channels until the ADST bit is cleared to 0. The conversion results are transferred for storage into the A/D data registers corresponding to the channels. When the mode or analog input channel selection must be changed during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1. A/D conversion will start again from the first channel in the group. The ADST bit can be set at the same time as the mode or channel selection is changed. Typical operations when three channels in group 0 (AN0 to AN2) are selected in scan mode are described next. Figure 15.4 shows a timing diagram for this example. 1. Scan mode is selected (SCAN = 1), scan group 0 is selected (CH2 = 0), analog input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1). 2. When A/D conversion of the first channel (AN0) is completed, the result is transferred into ADDRA. Next, conversion of the second channel (AN1) starts automatically. 3. Conversion proceeds in the same way through the third channel (AN2). 4. When conversion of all selected channels (AN0 to AN2) is completed, the ADF flag is set to 1 and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1, an ADI interrupt is requested at this time. 5. Steps 2 to 4 are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion starts again from the first channel (AN0). Rev. 2.0, 06/04, page 555 of 980 Continuous A/D conversion Set *1 Clear*1 ADST Clear*1 A/D conversion time Idle A/D conversion (1) ADF Idle A/D conversion (4) Idle Rev. 2.0, 06/04, page 556 of 980 Idle A/D conversion (2) Idle A/D conversion (5)*2 Idle Idle A/D conversion (3) Idle Idle Transfer A/D conversion result (1) A/D conversion result (4) A/D conversion result (2) A/D conversion result (3) State of channel 0 (AN 0) State of channel 1 (AN 1) State of channel 2 (AN 2) State of channel 3 (AN 3) ADDRA ADDRB ADDRC Figure 15.4 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2 Selected) ADDRD Notes: *1 Vertical arrows ( ) indicate instructions executed by software. *2 Data currently being converted is ignored. 15.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 15.5 shows the A/D conversion timing. Table 15.4 indicates the A/D conversion time. As indicated in figure 15.5, the A/D conversion time includes tD and the input sampling time. The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 15.4. In scan mode, the values given in table 15.4 apply to the first conversion. In the second and subsequent conversions the conversion time is fixed at 128 states when CKS = 0 or 66 states when CKS = 1. (1) Address bus (2) Write signal Input sampling timing ADF tD t SPL t CONV Legend (1): ADCSR write cycle (2): ADCSR address tD : A/D conversion start delay time t SPL : Input sampling time t CONV : A/D conversion time Figure 15.5 A/D Conversion Timing Rev. 2.0, 06/04, page 557 of 980 Table 15.4 A/D Conversion Time (Single Mode) CKS = 0 Symbol Synchronization delay Input sampling time A/D conversion time tD tSPL tCONV Min 6 -- 131 Typ -- 31 -- Max 9 -- 134 Min 4 -- 69 CKS = 1 Typ -- 15 -- Max 5 -- 70 Note: Values in the table are numbers of states. 15.4.4 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGE bit is set to 1 in ADCR and the 8-bit timer's ADTE bit is cleared to 0, external trigger input is enabled at the ADTRG pin. A high-tolow transition at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan modes, are the same as if the ADST bit had been set to 1 by software. Figure 15.6 shows the timing. ADTRG Internal trigger signal ADST A/D conversion Figure 15.6 External Trigger Input Timing Rev. 2.0, 06/04, page 558 of 980 15.5 Interrupts The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt request can be enabled or disabled by the ADIE bit in ADCSR. The ADI interrupt request can be designated as a DMAC activation source. In this case, an interrupt request is not sent to the CPU. 15.6 Usage Notes When using the A/D converter, note the following points: 1. Analog Input Voltage Range: During A/D conversion, the voltages input to the analog input pins should be in the range AVSS ANn VREF. 2. Relationships of AVCC and AVSS to VCC and VSS: AVCC, AVSS, VCC, and VSS should be related as follows: AVSS = VSS. AVCC and AVSS must not be left open, even if the A/D converter is not used. 3. VREF Programming Range: The reference voltage input at the VREF pin should be in the range VREF AVCC. 4. Note on Board Design: In board layout, separate the digital circuits from the analog circuits as much as possible. Particularly avoid layouts in which the signal lines of digital circuits cross or closely approach the signal lines of analog circuits. Induction and other effects may cause the analog circuits to operate incorrectly, or may adversely affect the accuracy of A/D conversion. The analog input signals (AN0 to AN7), analog reference voltage (VREF), and analog supply voltage (AVCC) must be separated from digital circuits by the analog ground (AVSS). The analog ground (AVSS) should be connected to a stable digital ground (VSS) at one point on the board. 5. Note on Noise: To prevent damage from surges and other abnormal voltages at the analog input pins (AN0 to AN7) and analog reference voltage pin (VREF), connect a protection circuit like the one in figure 15.7 between AVCC and AVSS. The bypass capacitors connected to AVCC and VREF and the filter capacitors connected to AN0 to AN7 must be connected to AVSS. If filter capacitors like the ones in figure 15.7 are connected, the voltage values input to the analog input pins (AN0 to AN7) will be smoothed, which may give rise to error. Error can also occur if A/D conversion is frequently performed in scan mode so that the current that charges and discharges the capacitor in the sample-and-hold circuit of the A/D converter becomes greater than that input to the analog input pins via input impedance Rin. The circuit constants should therefore be selected carefully. Rev. 2.0, 06/04, page 559 of 980 AV CC VREF Rin*2 *1 *1 0.1 F AV SS 100 AN0 to AN7 Notes: *1 10 F 0.01 F *2 Rin: input impedance Figure 15.7 Example of Analog Input Protection Circuit Table 15.5 Analog Input Pin Ratings Item Analog input capacitance Allowable signal-source impedance Note: * min -- -- max 20 10* Unit pF k When conversion time = 134 states, VCC = 3.0 V to 3.6 V, and 13 MHz. For details see section 21, Electrical Characteristics. 10 k AN0 to AN7 To A/D converter 20 pF Figure 15.8 Analog Input Pin Equivalent Circuit Note: Numeric values are approximate, except in table 15.5 Rev. 2.0, 06/04, page 560 of 980 6. A/D Conversion Accuracy Definitions: A/D conversion accuracy in the H8/3029 is defined as follows: * * Resolution: ...................Digital output code length of A/D converter Offset error:..................Deviation from ideal A/D conversion characteristic of analog input voltage required to raise digital output from minimum voltage value 0000000000 to 0000000001 (figure 15.10) Full-scale error:............Deviation from ideal A/D conversion characteristic of analog input voltage required to raise digital output from 1111111110 to 1111111111 (figure 15.10) Quantization error: .......Intrinsic error of the A/D converter; 1/2 LSB (figure 15.9) Nonlinearity error: .......Deviation from ideal A/D conversion characteristic in range from zero volts to full scale, exclusive of offset error, full-scale error, and quantization error. Absolute accuracy:.......Deviation of digital value from analog input value, including offset error, full-scale error, quantization error, and nonlinearity error. Digital output * * * * 111 110 101 100 011 010 001 000 Ideal A/D conversion characteristic Quantization error 1/8 2/8 3/8 4/8 5/8 6/8 7/8 FS Analog input voltage Figure 15.9 A/D Converter Accuracy Definitions (1) Rev. 2.0, 06/04, page 561 of 980 Digital output Full-scale error Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Offset error Analog input voltage Figure 15.10 A/D Converter Accuracy Definitions (2) 7. Allowable Signal-Source Impedance: The analog inputs of the H8/3029 are designed to assure accurate conversion of input signals with a signal-source impedance not exceeding 10 k. The reason for this rating is that it enables the input capacitor in the sample-and-hold circuit in the A/D converter to charge within the sampling time. If the sensor output impedance exceeds 10 k, charging may be inadequate and the accuracy of A/D conversion cannot be guaranteed. If a large external capacitor is provided in single mode, then the internal 10-k input resistance becomes the only significant load on the input. In this case the impedance of the signal source is not a problem. A large external capacitor, however, acts as a low-pass filter. This may make it impossible to track analog signals with high dv/dt (e.g. a variation of 5 mV/s) (figure 15.11). To convert high-speed analog signals or to use scan mode, insert a low-impedance buffer. 8. Effect on Absolute Accuracy: Attaching an external capacitor creates a coupling with ground, so if there is noise on the ground line, it may degrade absolute accuracy. The capacitor must be connected to an electrically stable ground, such as AVSS. If a filter circuit is used, be careful of interference with digital signals on the same board, and make sure the circuit does not act as an antenna. Rev. 2.0, 06/04, page 562 of 980 H8/3029 Sensor output impedance Sensor input Up to 10 k Cin = 15 pF Equivalent circuit of A/D converter 10 k Low-pass filter C Up to 0.1 F 20 pF Figure 15.11 Analog Input Circuit (Example) Rev. 2.0, 06/04, page 563 of 980 Rev. 2.0, 06/04, page 564 of 980 Section 16 D/A Converter 16.1 Overview The H8/3029 includes a D/A converter with two channels. 16.1.1 Features D/A converter features are listed below. * Eight-bit resolution * Two output channels * Conversion time: maximum 10 s (with 20-pF capacitive load) * Output voltage: 0 V to VREF * D/A outputs can be sustained in software standby mode 16.1.2 Block Diagram Figure 16.1 shows a block diagram of the D/A converter. Module data bus VREF DA 0 DA 1 AVSS 8-bit D/A Legend DACR: D/A control register DADR0: D/A data register 0 DADR1: D/A data register 1 DASTCR: D/A standby control register Control circuit Figure 16.1 D/A Converter Block Diagram Rev. 2.0, 06/04, page 565 of 980 DASTCR AVCC DADR0 DADR1 DACR Bus interface Internal data bus 16.1.3 Input/Output Pins Table 16.1 summarizes the D/A converter's input and output pins. Table 16.1 D/A Converter Pins Pin Name Analog power supply pin Analog ground pin Analog output pin 0 Analog output pin 1 Abbreviation I/O AVCC AVSS DA0 DA1 Input Input Output Output Input Function Analog power supply and reference voltage Analog ground and reference voltage Analog output, channel 0 Analog output, channel 1 Analog reference voltage Reference voltage input pin VREF 16.1.4 Register Configuration Table 16.2 summarizes the D/A converter's registers. Table 16.2 D/A Converter Registers Address* H'FFF9C H'FFF9D H'FFF9E H'EE01A Note: * Name D/A data register 0 D/A data register 1 D/A control register D/A standby control register Abbreviation DADR0 DADR1 DACR DASTCR R/W R/W R/W R/W R/W Initial Value H'00 H'00 H'1F H'FE Lower 20 bits of the address in advanced mode. Rev. 2.0, 06/04, page 566 of 980 16.2 16.2.1 Bit Register Descriptions D/A Data Registers 0 and 1 (DADR0/1) 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Initial value Read/Write The D/A data registers (DADR0 and DADR1) are 8-bit readable/writable registers that store the data to be converted. When analog output is enabled, the D/A data register values are constantly converted and output at the analog output pins. The D/A data registers are initialized to H'00 by a reset and in standby mode. When the DASTE bit is set to 1 in the D/A standby control register (DASTCR), the D/A registers are not initialized in software standby mode. 16.2.2 Bit Initial value Read/Write D/A Control Register (DACR) 7 DAOE1 0 R/W 6 DAOE0 0 R/W 5 DAE 0 R/W 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- D/A enable Controls D/A conversion D/A output enable 0 Controls D/A conversion and analog output D/A output enable 1 Controls D/A conversion and analog output DACR is an 8-bit readable/writable register that controls the operation of the D/A converter. DACR is initialized to H'1F by a reset and in standby mode. When the DASTE bit is set to 1 in DASTCR, the DACR is not initialized in software standby mode. Rev. 2.0, 06/04, page 567 of 980 Bit 7--D/A Output Enable 1 (DAOE1): Controls D/A conversion and analog output. Bit 7 DAOE1 0 1 Description DA1 analog output is disabled Channel-1 D/A conversion and DA1 analog output are enabled Bit 6--D/A Output Enable 0 (DAOE0): Controls D/A conversion and analog output. Bit 6 DAOE0 0 1 Description DA0 analog output is disabled Channel-0 D/A conversion and DA0 analog output are enabled Bit 5--D/A Enable (DAE): Controls D/A conversion, together with bits DAOE0 and DAOE1. When the DAE bit is cleared to 0, analog conversion is controlled independently in channels 0 and 1. When the DAE bit is set to 1, analog conversion is controlled together in channels 0 and 1. Output of the conversion results is always controlled independently by DAOE0 and DAOE1. Bit 7 Bit 6 Bit 5 DAOE1 DAOE0 DAE 0 0 1 -- 0 1 1 0 0 1 1 -- Description D/A conversion is disabled in channels 0 and 1 D/A conversion is enabled in channel 0 D/A conversion is disabled in channel 1 D/A conversion is enabled in channels 0 and 1 D/A conversion is disabled in channel 0 D/A conversion is enabled in channel 1 D/A conversion is enabled in channels 0 and 1 D/A conversion is enabled in channels 0 and 1 When the DAE bit is set to 1, even if bits DAOE0 and DAOE1 in DACR and the ADST bit in ADCSR are cleared to 0, the same current is drawn from the analog power supply as during A/D and D/A conversion. Bits 4 to 0--Reserved: These bits cannot be modified and are always read as 1. Rev. 2.0, 06/04, page 568 of 980 16.2.3 D/A Standby Control Register (DASTCR) DASTCR is an 8-bit readable/writable register that enables or disables D/A output in software standby mode. Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- Reserved bits D/A standby enable Enables or disables D/A output in software standby mode 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 DASTE 0 R/W DASTCR is initialized to H'FE by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 1--Reserved: These bits cannot be modified and are always read as 1. Bit 0--D/A Standby Enable (DASTE): Enables or disables D/A output in software standby mode. Bit 0 DASTE 0 1* Note: * Description D/A output is disabled in software standby mode D/A output is enabled in software standby mode The D/A accuracy is not guaranteed in software standby mode. (Initial value) Rev. 2.0, 06/04, page 569 of 980 16.3 Operation The D/A converter has two built-in D/A conversion circuits that can perform conversion independently. D/A conversion is performed constantly while enabled in DACR. If the DADR0 or DADR1 value is modified, conversion of the new data begins immediately. The conversion results are output when bits DAOE0 and DAOE1 are set to 1. An example of D/A conversion on channel 0 is given next. Timing is indicated in figure 16.2. 1. Data to be converted is written in DADR0. 2. Bit DAOE0 is set to 1 in DACR. D/A conversion starts and DA0 becomes an output pin. The converted result is output after the conversion time. The output value is DADR contents x VREF 256 Output of this conversion result continues until the value in DADR0 is modified or the DAOE0 bit is cleared to 0. 3. If the DADR0 value is modified, conversion starts immediately, and the result is output after the conversion time. 4. When the DAOE0 bit is cleared to 0, DA0 becomes an input pin. Rev. 2.0, 06/04, page 570 of 980 DADR0 write cycle DACR write cycle DADR0 write cycle DACR write cycle Address DADR0 DAOE0 DA 0 Conversion data 1 Conversion data 2 High-impedance state t DCONV Legend t DCONV : D/A conversion time Conversion result 1 t DCONV Conversion result 2 Figure 16.2 Example of D/A Converter Operation 16.4 D/A Output Control In the H8/3029, D/A converter output can be enabled or disabled in software standby mode. When the DASTE bit is set to 1 in DASTCR, D/A converter output is enabled in software standby mode. The D/A converter registers retain the values they held prior to the transition to software standby mode. When D/A output is enabled in software standby mode, the reference supply current is the same as during normal operation. Rev. 2.0, 06/04, page 571 of 980 Rev. 2.0, 06/04, page 572 of 980 Section 17 RAM 17.1 Overview The H8/3029 has 16 kbytes RAM. The RAM is connected to the CPU by a 16-bit data bus. The CPU accesses both byte data and word data in two states, making the RAM useful for rapid data transfer. The on-chip RAM of the H8/3029 is assigned to addresses H'FBF20 to H'FFF1F in modes 1, 2, and 7, and to addresses H'FFBF20 to H'FFFF1F in modes 3, 4, and 5. The RAM enable bit (RAME) in the system control register (SYSCR) can enable or disable the on-chip RAM. 17.1.1 Block Diagram Figure 17.1 shows a block diagram of the on-chip RAM. On-chip data bus (upper 8 bits) On-chip data bus (lower 8 bits) Bus interface SYSCR H'FBF20* H'FBF22* H'FBF21* H'FBF23* On-chip RAM H'FFF1E* Even addresses Legend SYSCR: System control register Note: * Lower 20 bits of the address in mode 7. H'FFF1F* Odd addresses Figure 17.1 RAM Block Diagram Rev. 2.0, 06/04, page 573 of 980 17.1.2 Register Configuration The on-chip RAM is controlled by SYSCR. Table 17.1 gives the address and initial value of SYSCR. Table 17.1 System Control Register Address* H'EE012 Note: * Name System control register Abbreviation SYSCR R/W R/W Initial Value H'09 Lower 20 bits of the address in advanced mode. 17.2 Bit System Control Register (SYSCR) 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 UE 1 R/W 2 NMIEG 0 R/W 1 SSOE 0 R/W 0 RAME 1 R/W Initial value Read/Write RAM enable bit Enables or disables on-chip RAM Software standby output port enable NMI edge select User bit enable Standby timer select 2 to 0 Software standby One function of SYSCR is to enable or disable access to the on-chip RAM. The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details about the other bits, see section 3.3, System Control Register (SYSCR). Bit 0--RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized at the rising edge of the input at the RES pin. It is not initialized in software standby mode. Bit 0 RAME 0 1 Description On-chip RAM is disabled On-chip RAM is enabled (Initial value) Rev. 2.0, 06/04, page 574 of 980 17.3 Operation When the RAME bit is set to 1, the on-chip RAM is enabled. Accesses to addresses H'FBF20 to H'FFF1F in modes 1, 2, and 7, and to addresses H'FFBF20 to H'FFFF1F in the H8/3029 in modes 3, 4, and 5, are directed to the on-chip RAM. In modes 1 to 5 (expanded modes), when the RAME bit is cleared to 0, the off-chip address space is accessed. In mode 7 (single-chip mode), when the RAME bit is cleared to 0, the on-chip RAM is not accessed: read access always results in H'FF data, and write access is ignored. Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written and read by word access. It can also be written and read by byte access. Byte data is accessed in two states using the upper 8 bits of the data bus. Word data starting at an even address is accessed in two states using all 16 bits of the data bus. Rev. 2.0, 06/04, page 575 of 980 Rev. 2.0, 06/04, page 576 of 980 Section 18 ROM 18.1 Features This LSI has an on-chip 512-kbyte flash memory. The flash memory has the following features. * Two flash-memory MATs according to LSI initiation mode The on-chip flash memory has two memory spaces in the same address space (hereafter referred to as memory MATs). The mode setting in the initiation determines which memory MAT is initiated first. The MAT can be switched by using the bank-switching method after initiation. The user memory MAT is initiated at a power-on reset in user mode: 512 kbytes The user boot memory MAT is initiated at a power-on reset in user boot mode:10 kbytes * Three on-board programming modes and one off-board programming mode On-board programming modes Boot mode: This mode is a program mode that uses an on-chip SCI interface. The user MAT and user boot MAT can be programmed. This mode can automatically adjust the bit rate between host and this LSI. User program mode: The user MAT can be programmed by using the optional interface. User boot mode: The user boot program of the optional interface can be made and the user MAT can be programmed. Off-board programming mode PROM mode: This mode uses the PROM programmer. The user MAT and user boot MAT can be programmed. * Programming/erasing interface by the download of on-chip program This LSI has a dedicated programming/erasing program. After downloading this program to the on-chip RAM, programming/erasing can be performed by setting the argument parameter. User branch* The program processing is performed in 128-byte units. It consists the program pulse application, verify read, and several other steps. Erasing is performed in one divided-block units and consists of several steps. The user processing routine can be executed between the steps, this setting for which is called the user branch addition. Note: * Not available in the H8/3029. Rev. 2.0, 06/04, page 577 of 980 * Emulation function of flash memory by using the on-chip RAM As flash memory is overlapped with part of the on-chip RAM, the flash memory programming can be emulated in real time. * Protection modes There are two protection modes: software protection by the register setting and hardware protection by the FWE pin. The protection state for flash memory programming/erasing can be set. When abnormalities, such as runaway of programming/erasing are detected, these modes enter the error protection state and the programming/erasing processing is suspended. * Programming/erasing time The flash memory programming time is 3 ms (typ) in 128-byte simultaneous programming and 25 s per byte. The erasing time is 1000 ms (typ) per 64 kbyte block. * Number of programming The number of flash memory programming can be up to minimum 100 times. Rev. 2.0, 06/04, page 578 of 980 18.2 18.2.1 Overview Block Diagram Internal address bus Internal data bus (16 bits) FCCS FPCS Module bus FECS FKEY FMATS FTDAR RAMCR FVACR FVADR Flash memory Control unit Memory MAT unit User MAT: 512 kbytes User boot MAT: 10 kbytes FWE pin Mode pin Operating mode Legend FCCS: FPCS: FECS: FKEY: FMATS: FTDAR: RAMCR: FVACR: FVADR: Flash code control and status register Flash program code select register Flash erase code select register Flash key code register Flash MAT select register Flash transfer destination address register RAM control register Flash vector address control register Flash vector address data register Figure 18. 1 Block Diagram of Flash Memory Rev. 2.0, 06/04, page 579 of 980 18.2.2 Operating Mode When each mode pin and the FWE pin are set in the reset state and reset start is performed, the microcomputer enters each operating mode as shown in figure 18.2. For the setting of each mode pin and the FWE pin, see table 18.1. * Flash memory cannot be read, programmed, or erased in ROM invalid mode. * Flash memory can be read in user mode, but cannot be programmed or erased. * Flash memory can be read, programmed, or erased on the board only in user program mode, user boot mode, and boot mode. * Flash memory can be read, programmed, or erased by means of the PROM programmer in PROM mode. ROM invalid mode 4-5=0 ROM invalid mode setting 4-5=0 Reset state PROM mode setting PROM mode Us mo er p de rog se ram ttin g 5= 5 4U =0 d mo es in ett g 0 Bo 4ot mo de 5=0 ttin g ot g bo tin er set Us de mo 45= r se 4- se 0 FWE=0 User mode User program mode FWE=1 User boot mode Boot mode RAM emulation is enabled On-board programming mode Figure 18.2 Mode Transition of Flash Memory Rev. 2.0, 06/04, page 580 of 980 Table 18.1 Location of FWE and MD Pins and Operating Modes Mode On-chip ROM invalid mode* 1 0 0/1 0/1 0 0/1 0 0 1 On-chip ROM valid mode* 1 0 1 0/1 1 0/1 User program mode 1 1 1 0/1 1 0/1 User boot mode 1 1 1 0/1 0 0 Pin RES FWE MD0 MD1 MD2 NMI Note: * Reset state 0 0/1 0/1 0/1 0/1 0/1 Boot mode 1 1 1 0/1 0 1 PROM mode 1 1 0 0 0 0/1 Modes 1 to 4 are on-chip ROM invalid modes. Modes 5 and 7 are on-chip ROM valid modes. For details, see section 3, MCU Operating Modes. 18.2.3 Mode Comparison The comparison table of programming and erasing related items about boot mode, user program mode, user boot mode, and PROM mode is shown in table 18.2. Rev. 2.0, 06/04, page 581 of 980 Table 18.2 Comparison of Programming Modes Boot mode Programming/ Erasing Environment Programming/ Erasing Enable MAT All Erasure Block Division Erasure Program Data Transfer User Branch Function RAM Emulation Reset Initiation MAT Transition to User Mode On-board programming User MAT User boot MAT (Automatic) * 1 User program mode On-board programming User MAT User boot mode On-board programming User MAT PROM mode Off-board programming User MAT User boot MAT (Automatic) x From optional device via RAM From optional device via RAM Via programmer From host via SCI x x Embedded program storage MAT Mode setting change and reset x x x x x 2 User MAT User boot MAT* -- FWE setting change Mode setting change and reset -- Notes: *1 All-erasure is performed. After that, the specified block can be erased. *2 Initiation starts from the embedded program storage MAT. After checking the flashmemory related registers, initiation starts from the reset vector of the user MAT. * The user boot MAT can be programmed or erased only in boot mode and PROM mode. * The user MAT and user boot MAT are erased in boot mode. Then, the user MAT and user boot MAT can be programmed by means of the command method. However, the contents of the MAT cannot be read until this state. Only user boot MAT is programmed and the user MAT is programmed in user boot mode or only user MAT is programmed because user boot mode is not used. * The boot operation of the optional interface can be performed by the mode pin setting different from user program mode in user boot mode. Rev. 2.0, 06/04, page 582 of 980 18.2.4 Flash MAT Configuration This LSI's flash memory is configured by the 512-kbyte user MAT and 10-kbyte user boot MAT. The start address is allocated to the same address in the user MAT and user boot MAT. Therefore, when the program execution or data access is performed between two MATs, the MAT must be switched by using FMATS. The user MAT or user boot MAT can be read in all modes if it is in ROM valid mode. However, the user boot MAT can be programmed only in boot mode and PROM mode. 10 kbytes 512 kbytes Address H'07FFFF Figure 18.3 Flash Memory Configuration The user MAT and user boot MAT have different memory sizes. Do not access a user boot MAT that is 10 kbytes or more. When a user boot MAT exceeding 10 kbytes is read from, an undefined value is read. 18.2.5 Block Division The user MAT is divided into 64 kbytes (seven blocks), 32 kbytes (one block), and 4 kbytes (eight blocks) as shown in figure 18.4. The user MAT can be erased in this divided-block units and the erase-block number of EB0 to EB15 is specified when erasing. The RAM emulation can be performed in the eight blocks of 4 kbytes. Rev. 2.0, 06/04, page 583 of 980 Erase block EB0 to * EB7 32 kbytes 64 kbytes 512 kbytes EB8 EB9 EB10 EB11 EB12 EB13 EB14 EB15 64 kbytes 64 kbytes 64 kbytes 64 kbytes 64 kbytes Address H'07FFFF 64 kbytes Note: *The RAM emulation can be performed in the eight blocks of 4 kbytes. Figure 18.4 Block Division of User MAT 18.2.6 Programming/Erasing Interface Programming/erasing is executed by downloading the on-chip program to the on-chip RAM and specifying the program address/data and erase block by using the interface register/parameter. The procedure program is made by the user in user program mode and user boot mode. The overview of the procedure is as follows. For details, see section 18.5.2, User Program Mode. Rev. 2.0, 06/04, page 584 of 980 Start user procedure program for programming/erasing Select on-chip program to be downloaded and set download destination Download on-chip program by setting FKEY and the SCO bits Initialization execution (download program execution) Programming (in 128-byte units) or erasing (in one-block units) (download program execution) No Programming/erasing completed? Yes End user procedure program Figure 18.5 Overview of User Procedure Program 1. Selection of on-chip program to be downloaded and setting of download destination This LSI has programming/erasing programs and they can be downloaded to the on-chip RAM. The on-chip program to be downloaded is selected by setting the corresponding bits in the programming/erasing interface register. The download destination can be specified by FTDAR. 2. Download of on-chip program The on-chip program is automatically downloaded by setting the SCO bit in the flash key code register (FKEY) and the flash code control and status register (FCCS), which are programming/ erasing interface registers. The user MAT is replaced to the embedded program storage area when downloading. Since the flash memory cannot be read when programming/erasing, the procedure program, which is working from download to completion of programming/erasing, must be executed in a space other than the flash memory to be programmed/erased (for example, on-chip RAM). Since the result of download is returned to the programming/erasing interface parameters, whether the normal download is executed or not can be confirmed. Rev. 2.0, 06/04, page 585 of 980 3. Initialization of programming/erasing The operating frequency and user branch are set before execution of programming/erasing. The user branch destination must be area other than the flash memory area or the area where the onchip program is downloaded. These settings are performed by using the programming/erasing interface parameters. 4. Programming/erasing execution To program or erase, the FWE pin must be set to 1 and user program mode must be entered. The program data/programming destination address is specified in 128-byte units when programming. The block to be erased is specified in erase-block units when erasing. These specifications are set by using the programming/erasing interface parameters and the onchip program is initiated. The on-chip program is executed by using the JSR or BSR instruction to perform the subroutine call of the specified address in the on-chip RAM. The execution result is returned to the programming/erasing interface parameters. The area to be programmed must be erased in advance when programming flash memory. All interrupts are prohibited during programming and erasing. Interrupts must not occur in the user system. 5. When programming/erasing is executed consecutively When the processing is not ended by the 128-byte programming or one-block erasure, the program address/data and erase-block number must be updated and consecutive programming/erasing is required. Since the downloaded on-chip program is left in the on-chip RAM after the processing, download and initialization are not required when the same processing is executed consecutively. Rev. 2.0, 06/04, page 586 of 980 18.3 Pin Configuration Flash memory is controlled by the pin as shown in table 18.3. Table 18.3 Pin Configuration Pin Name Reset Flash programming enable Mode 2 Mode 1 Mode 0 Non-maskable interrupt Transmit data Receive data Abbreviation RES FWE MD2 MD1 MD0 NMI TxD1 RxD1 Input/Output Input Input Input Input Input Input Output Input Function Reset Hardware protection when programming flash memory Sets operating mode of this LSI Sets operating mode of this LSI Sets operating mode of this LSI Sets operating mode of this LSI Serial transmit data output (used in boot mode) Serial receive data input (used in boot mode) Note: For the pin configuration in PROM mode, see section 18.9, PROM Mode. Rev. 2.0, 06/04, page 587 of 980 18.4 18.4.1 Register Configuration Registers The registers/parameters which control flash memory when the on-chip flash memory is valid are shown in table 18.4. There are several operating modes for accessing flash memory, for example, read mode/program mode. There are two memory MATs: user MAT and user boot MAT. The dedicated registers/parameters are allocated for each operating mode and MAT selection. The correspondence of operating modes and registers/parameters for use is shown in table 18.5. Rev. 2.0, 06/04, page 588 of 980 Table 18.4 (1) Name Register Configuration Abbreviation FCCS FPCS FECS FKEY FMATS FTDAR RAMCR FVACR FVADRR FVADRE FVADRH FVADRL R/W R, W* R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 1 Initial Value H'00* 2 H'80* H'00 H'00 H'00 H'00* 3 H'AA* H'00 H'F0 H'00 H'00 H'00 H'00 H'00 3 2 Address H'EE0B0 H'EE0B1 H'EE0B2 H'EE0B4 H'EE0B5 H'EE0B6 H'EE077 H'EE0B7 H'EE0B8 H'EE0B9 H'EE0BA H'EE0BB Access Size 8 8 8 8 8 8 8 8 8 8 8 8 Flash code control status register Flash program code select register Flash erase code select register Flash key code register Flash MAT select register Flash transfer destination address register RAM control register Flash vector address code control register Flash vector address data register R Flash vector address data register E Flash vector address data register H Flash vector address data register L Notes: *1 The bits except the SCO bit are read-only bits. The SCO bit is a programming-only bit. (The value which can be read is always 0.) *2 The initial value is H'00 when the FWE pin goes low. The initial value is H'80 when the FWE pin goes high. *3 The initial value at initiation in user mode or user program mode is H'00. The initial value at initiation in user boot mode is H'AA. Rev. 2.0, 06/04, page 589 of 980 Table 18.4 (2) Name Parameter Configuration Abbreviation DPFR FPFR FMPAR FMPDR FEBS FPEFEQ FUBRA R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Address On-chip RAM* R0L of CPU ER1 of CPU ER0 of CPU ER0 of CPU ER0 of CPU ER1 of CPU Access Size 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 Download pass/fail result Flash pass/fail result Flash multipurpose address area Flash multipurpose data destination area Flash erase block select Flash program and erase frequency control Flash user branch address set parameter Note: * One byte of the start address in the on-chip RAM area specified by FTDAR is valid. Rev. 2.0, 06/04, page 590 of 980 Table 18.5 Register/Parameter and Target Mode Download Programming/ erasing interface registers FCCS FPCS PECS FKEY FMATS FTDAR Programming/ erasing interface parameter DPFR FPFR FPEFEQ FUBRA FMPAR FMPDR FEBS RAM emulation RAMCR -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialization -- -- -- -- -- -- -- * -- -- 1 Programming -- -- -- Erasure -- -- -- * -- -- 1 Read -- -- -- -- * -- -- -- -- -- -- -- -- -- 2 RAM Emulation -- -- -- -- -- -- -- -- -- -- -- -- -- Notes: *1 The setting is required when programming or erasing user MAT in user boot mode. *2 The setting may be required according to the combination of initiation mode and read target MAT. 18.4.2 Programming/Erasing Interface Register The programming/erasing interface registers are as described below. They are all 8-bit registers that can be accessed in byte. Except for the FLER bit in FCCS, these registers are initialized at a power-on reset, in hardware standby mode, or in software standby mode. The FLER bit is not initialized in software standby mode. (1) Flash Code Control and Status Register (FCCS) FCCS is configured by bits which request the monitor of the FWE pin state and error occurrence during programming or erasing flash memory and the download of on-chip program. Bit : Initial value : R/W : 7 FWE 1/0 R 6 -- 0 R 5 -- 0 R 4 FLER 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 SCO 0 (R)W Bit 7--Flash Programming Enable (FWE): Monitors level which is input to the FWE pin that performs hardware protection of the flash memory programming or erasing. The initial value is 0 or 1 according to the FWE pin state. Rev. 2.0, 06/04, page 591 of 980 Bit 7 FWE 0 1 Description When the FWE pin goes low (in hardware protection state) When the FWE pin goes high Bits 6 and 5--Reserved: These bits are always read as 0. The write value should always be 0. Bit 4--Flash Memory Error (FLER): Indicates an error occurs during programming and erasing flash memory. When FLER is set to 1, flash memory enters the error protection state. This bit is initialized at a power-on reset or in hardware standby mode. When FLER is set to 1, high voltage is applied to the internal flash memory. To reduce the damage to flash memory, the reset must be released after the reset period of 100 s which is longer than normal. Bit 4 FLER 0 Description Flash memory operates normally (Initial value) Programming/erasing protection for flash memory (error protection) is invalid. [Clearing condition] At a power-on reset or in hardware standby mode Indicates an error occurs during programming/erasing flash memory. Programming/erasing protection for flash memory (error protection) is valid. [Setting condition] See section 18.6.3, Error Protection. 1 Bits 3 to 1--Reserved: These bits are always read as 0. The write value should always be 0. Bit 0--Source Program Copy Operation (SCO): Requests the on-chip programming/erasing program to be downloaded to the on-chip RAM. When this bit is set to 1, the on-chip program which is selected by FPCS/FECS is automatically downloaded in the on-chip RAM area specified by FTDAR. In order to set this bit to 1, RAM emulation state must be canceled, H'A5 must be written to FKEY, and this operation must be in the on-chip RAM. Four NOP instructions must be executed immediately after setting this bit to 1. Since this bit is cleared to 0 when download is completed, this bit cannot be read as 1. All interrupts are prohibited during programming and erasing. Interrupts must not occur in the user system. Rev. 2.0, 06/04, page 592 of 980 Bit 0 SCO 0 Description Download of the on-chip programming/erasing program to the on-chip RAM is not executed (Initial value) [Clear condition] When download is completed Request that the on-chip programming/erasing program is downloaded to the onchip RAM is occurred [Clear conditions] When all of the following conditions are satisfied and 1 is written to this bit * * * FKEY is written to H'A5 During execution in the on-chip RAM Not in RAM emulation mode (RAMS in RAMCR = 0) 1 (2) Flash Program Code Select Register (FPCS) FPCS selects the on-chip programming program to be downloaded. Bit : Initial value : R/W : 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 PPVS 0 R/W Bits 7 to 1--Reserved: These bits are always read as 0. The write value should always be 0. Bit 0--Program Pulse Verify (PPVS): Selects the programming program. Bit 0 PPVS 0 1 Description On-chip programming program is not selected [Clear condition] When transfer is completed On-chip programming program is selected (Initial value) Rev. 2.0, 06/04, page 593 of 980 (3) Flash Erase Code Select Register (FECS) FECS selects download of the on-chip erasing program. Bit : Initial value : R/W : 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 EPVB 0 R/W Bits 7 to 1--Reserved: These bits are always read as 0. The write value should always be 0. Bit 0--Erase Pulse Verify Block (EPVB): Selects the erasing program. Bit 0 EPVB 0 1 Description On-chip erasing program is not selected [Clear condition] When transfer is completed On-chip erasing program is selected (Initial value) (4) Flash Key Code Register (FKEY) FKEY is a register for software protection that enables download of on-chip program and programming/erasing of flash memory. Before setting the SCO bit to 1 in order to download onchip program or executing the downloaded programming/erasing program, these processing cannot be executed if the key code is not written. Bit : Initial value : R/W : 7 K7 0 R/W 6 K6 0 R/W 5 K5 0 R/W 4 K4 0 R/W 3 K3 0 R/W 2 K2 0 R/W 1 K1 0 R/W 0 K0 0 R/W Bits 7 to 0--Key Code (K7 to K0): Only when H'A5 is written, writing to the SCO bit is valid. When the value other than H'A5 is written to FKEY, 1 cannot be written to the SCO bit. Therefore downloading to the on-chip RAM cannot be executed. Only when H'5A is written, programming/erasing can be executed. Even if the on-chip programming/erasing program is executed, flash memory cannot be programmed or erased when the value other than H'5A is written to FKEY. Rev. 2.0, 06/04, page 594 of 980 Bits 7 to 0 K7 to K0 H'A5 H'5A H'00 Description Writing to the SCO bit is enabled (The SCO bit cannot be set by the value other than H'A5.) Programming/erasing is enabled (The value other than H'5A is in software protection state.) Initial value (5) Flash MAT Select Register (FMATS) FMATS specifies whether user MAT or user boot MAT is selected. Bit : Initial value : Initial value : R/W : 7 MS7 0 1 R/W 6 MS6 0 0 R/W 5 MS5 0 1 R/W 4 MS4 0 0 R/W 3 MS3 0 1 R/W 2 MS2 0 0 R/W 1 MS1 0 1 R/W 0 MS0 0 0 R/W (When not in user boot mode) (When in user boot mode) Bits 7 to 0--MAT Select (MS7 to MS0): These bits are in user-MAT selection state when the value other than H'AA is written and in user-boot-MAT selection state when H'AA is written. The MAT is switched by writing the value in FMATS. When the MAT is switched, follow section 18.8, Switching between User MAT and User Boot MAT. (The user boot MAT cannot be programmed in user programming mode if user boot MAT is selected by FMATS. The user boot MAT must be programmed in boot mode or in PROM mode.) Bits 7 to 0 MS7 to MS0 H'AA Description The user boot MAT is selected (in user-MAT selection state when the value of these bits are other than H'AA) Initial value when these bits are initiated in user boot mode. H'00 Initial value when these bits are initiated in a mode except for user boot mode (in user-MAT selection state) [Programmable condition] ] These bits are in the process of being executed in the on-chip RAM. Rev. 2.0, 06/04, page 595 of 980 (6) Flash Transfer Destination Address Register (FTDAR) FTDAR specifies the on-chip RAM address to which the on-chip program is downloaded. Make settings for FTDAR before writing 1 to the SCO bit in FCCS. The initial value is H'00 which points to the start address (H'FFEF20) in on-chip RAM. Bit : Initial value : R/W : 7 TDER 0 R/W 6 TDA6 0 R/W 5 TDA5 0 R/W 4 TDA4 0 R/W 3 TDA3 0 R/W 2 TDA2 0 R/W 1 TDA1 0 R/W 0 TDA0 0 R/W Bit 7--Transfer Destination Address Setting Error (TDER): This bit is set to 1 when there is an error in the download start address set by bits 6 to 0 (TDA6 to TDA0). Whether the address setting is erroneous or not is judged by checking whether the setting of TDA6 to TDA0 is between the range of H'00 and H'03 after setting the SCO bit in FCCS to 1 and performing download. Before setting the SCO bit to 1 be sure to set the FTDAR value between H'00 to H'03 as well as clearing this bit to 0. Bit 7 TDER 0 1 Description(Return Value after Download) Setting of TDA6 to TDA0 is normal (Initial value) Setting of TDER and TDA6 to TDA0 is H'04 to H'FF and download has been aborted Bits 6 to 0--Transfer Destination Address (TDA6 to TDA0): These bits specify the download start address. A value from H'00 to H'03 can be set to specify the download start address in onchip RAM in 4-kbyte units. A value from H'04 to H'7F cannot be set. If such a value is set, the TDER bit (bit 7) in this register is set to 1 to prevent download from being executed. Bits 6 to 0 TDA6 to TDA0 H'00 H'01 H'02 H'03 H'04 to H'FF Description Download start address is set to H'FFEF20 Download start address is set to H'FFDF20 Download start address is set to H'FFCF20 Download start address is set to H'FFBF20 Setting prohibited. If this value is set, the TDER bit (bit 7) is set to 1 to abort the download processing. (Initial value) Rev. 2.0, 06/04, page 596 of 980 18.4.3 Programming/Erasing Interface Parameter The programming/erasing interface parameter specifies the operating frequency, user branch destination address, storage place for program data, programming destination address, and erase block and exchanges the processing result for the downloaded on-chip program. This parameter uses the general registers of the CPU (ER0 and ER1) or the on-chip RAM area. The initial value is undefined at a power-on reset or in hardware standby mode. When download, initialization, or on-chip program is executed, registers of the CPU except for R0L are stored. The return value of the processing result is written in R0L. Since the stack area is used for storing the registers except for R0L, the stack area must be saved at the processing start. (A maximum size of a stack area to be used is 128 bytes.) The programming/erasing interface parameter is used in the following four items. (1) Download control (2) Initialization before programming or erasing (3) Programming (4) Erasing These items use different parameters. The correspondence table is shown in table 18.6. Here the FPFR parameter returns the results of initialization processing, programming processing, or erasing processing, but the meaning of the bits differs depending on the type of processing. For details, refer to the FPFR descriptions for the individual processes. Rev. 2.0, 06/04, page 597 of 980 Table 18.6 Usable Parameters and Target Modes Name of Parameter Download pass/fail result Flash pass/fail result Flash programming/ erasing frequency control Flash user branch address set parameter Flash multipurpose address area Flash multipurpose data destination area Flash erase block select Note: * Abbreviation DPFR Download Initialization -- Programming -- Erasure -- R/W R/ W R/ W -- -- R/ W Initial Value Undefined Allocation Onchip RAM* R0L of CPU ER0 of CPU FPFR FPEFEQ -- -- Undefined Undefined FUBRA -- -- -- R/ W R/ W R/ W Undefined ER1 of CPU ER1 of CPU ER0 of CPU FMPAR -- -- -- Undefined FMPDR -- -- -- Undefined FEBS -- -- -- R/ W Undefined ER0 of CPU One byte of start address of download destination specified by FTDAR (1) Download Control The on-chip program is automatically downloaded by setting the SCO bit to 1. The on-chip RAM area to be downloaded is the area as much as 4 kbytes starting from the start address specified by FTDAR. For the address map of the on-chip RAM, see figure 18.10. The download control is set by using the programming/erasing interface register. The return value is given by the DPFR parameter. (a) Download pass/fail result parameter (DPFR: one byte of start address of on-chip RAM specified by FTDAR) This parameter indicates the return value of the download result. The value of this parameter can be used to determine if downloading is executed or not. Since the confirmation whether the SCO bit is set to 1 is difficult, the certain determination must be performed by setting one byte of the start address of the on-chip RAM area specified by FTDAR to a value other than the return value of download (for example, H'FF) before the download start (before setting the SCO bit to 1). Refer to item 18.5.2 (e) for information on the method for checking the download result. Rev. 2.0, 06/04, page 598 of 980 Bit : 7 0 6 0 5 0 4 0 3 0 2 SS 1 FK 0 SF Bits 7 to 3--Unused: Return 0. Bit 2--Source Select Error Detect (SS): The on-chip program which can be downloaded can be specified only one type. When more than two types of the program are selected, the program is not selected, or the program is selected without mapping, error is occurred. Bit 2 SS 0 1 Description Download program can be selected normally Download error is occurred (Multi-selection or program which is not mapped is selected) Bit 1--Flash Key Register Error Detect (FK): Returns the check result whether the value of FKEY is set to H'A5. Bit 1 FK 0 1 Description FKEY setting is normal (FKEY = H'A5) Setting value of FKEY becomes error (FKEY = value other than H'A5) Bit 0--Success/Fail (SF): Returns the result whether download is ended normally or not. The judgement result whether program that is downloaded to the on-chip RAM is read back and then transferred to the on-chip RAM is returned. Bit 0 SF 0 1 Description Downloading on-chip program is ended normally (no error) Downloading on-chip program is ended abnormally (error occurs) (2) Programming/Erasing Initialization The on-chip programming/erasing program to be downloaded includes the initialization program. The specified period pulse must be applied when programming or erasing. The specified pulse width is made by the method in which wait loop is configured by the CPU instruction. The operating frequency of the CPU must be set. The initial program is set as a parameter of the programming/erasing program which has downloaded these settings. Rev. 2.0, 06/04, page 599 of 980 (a) Flash programming/erasing frequency parameter (FPEFEQ: general register ER0 of CPU) This parameter sets the operating frequency of the CPU. For the range of the operating frequency of this LSI, see section 21.4.1, Clock Timing. Bit : Bit : 31 0 23 0 15 F15 7 F7 30 0 22 0 14 F14 6 F6 29 0 21 0 13 F13 5 F5 28 0 20 0 12 F12 4 F4 27 0 19 0 11 F11 3 F3 26 0 18 0 10 F10 2 F2 25 0 17 0 9 F9 1 F1 24 0 16 0 8 F8 0 F0 Bit : Bit : Bits 31 to 16--Unused: Only 0 may be written to these bits. Bits 15 to 0--Frequency Set (F15 to F0): Set the operating frequency of the CPU. The setting value must be calculated as the following methods. 1. The operating frequency which is shown in MHz units must be rounded in a number to three decimal places and be shown in a number of two decimal places. 2. The centuplicated value is converted to the binary digit and is written to the FPEFEQ parameter (general register R0). For example, when the operating frequency of the CPU is 25.000 MHz, the value is as follows. * The number to three decimal places of 25.000 is rounded and the value is thus 25.00. * The formula that 25.00 x 100 = 2500 is converted to the binary digit and b'0000,1001,1100,0100 (H'09C4) is set to R0. Rev. 2.0, 06/04, page 600 of 980 (b) Flash user branch address setting parameter (FUBRA: general register ER1 of CPU) This parameter sets the user branch destination address. The user program which has been set can be executed in specified processing units when programming and erasing. Bit : Bit : Bit : Bit : 31 UA31 23 UA23 15 UA15 7 UA7 30 UA30 22 UA22 14 UA14 6 UA6 29 UA29 21 UA21 13 UA13 5 UA5 28 UA28 20 UA20 12 UA12 4 UA4 27 UA27 19 UA19 11 UA11 3 UA3 26 UA26 18 UA18 10 UA10 2 UA2 25 UA25 17 UA17 9 UA9 1 UA1 24 UA24 16 UA16 8 UA8 0 UA0 Bits 31 to 0--User Branch Destination Address (UA31 to UA0): Not available in the H8/3029, address 0 (H'00000000) must be set. The user branch destination must be the area other than the RAM area in which on-chip program has been transferred or the external bus space. Note that the CPU must not branch to an area without the execution code and get out of control. The on-chip program download area and stack area must not be overwritten. If CPU runaway occurs or the download area or stack area is overwritten, the value of flash memory cannot be guaranteed. The download of on-chip program, initialization, initiation of the programming/erasing program must not be executed in the processing of the user branch destination. Programming or erasing cannot be guaranteed when returning from the user branch destination. The program data which has already been prepared must not be programmed. Moreover, the programming/erasing interface register must not be programmed or RAM emulation mode must not be entered in the processing of the user branch destination. After the processing of the user branch is ended, the programming/erasing program must be returned by using the RTS instruction. (c) Flash pass/fail parameter (FPFR: general register R0L of CPU) An explanation of FPFR as the return value indicating the initialization result is provided here. Bit : 7 0 6 0 5 0 4 0 3 0 2 BR 1 FQ 0 SF Bits 7 to 3--Unused: Return 0. Rev. 2.0, 06/04, page 601 of 980 Bit 2--User Branch Error Detect (BR): Returns the check result whether the specified user branch destination address is in the area other than the storage area of the programming/erasing program which has been downloaded . Bit 2 BR 0 1 Description User branch address setting is normal User branch address setting is abnormal Bit 1--Frequency Error Detect (FQ): Returns the check result whether the specified operating frequency of the CPU is in the range of the supported operating frequency. Bit 1 FQ 0 1 Description Setting of operating frequency is normal Setting of operating frequency is abnormal Bit 0--Success/Fail (SF): Indicates whether initialization is completed normally. Bit 0 SF 0 1 Description Initialization is ended normally (no error) Initialization is ended abnormally (error occurs) (3) Programming Execution When flash memory is programmed, the programming destination address on the user MAT must be passed to the programming program in which the program data is downloaded. 1. The start address of the programming destination on the user MAT is set in general register ER1 of the CPU. This parameter is called FMPAR (flash multipurpose address area parameter). Since the program data is always in 128-byte units, the lower eight bits (MOA7 to MOA0) must be H'00 or H'80 as the boundary of the programming start address on the user MAT. 2. The program data for the user MAT must be prepared in the consecutive area. The program data must be in the consecutive space which can be accessed by using the MOV.B instruction of the CPU and is not the flash memory space. When data to be programmed does not satisfy 128 bytes, the 128-byte program data must be prepared by embedding the dummy code (H'FF). The start address of the area in which the prepared program data is stored must be set in general register ER0. This parameter is called FMPDR (flash multipurpose data destination area parameter). Rev. 2.0, 06/04, page 602 of 980 For details on the programming procedure, see section 18.5.2, User Program Mode. (a) Flash multipurpose address area parameter (FMPAR: general register ER1 of CPU) This parameter indicates the start address of the programming destination on the user MAT. When an address in an area other than the flash memory space is set, an error occurs. The start address of the programming destination must be at the 128-byte boundary. If this boundary condition is not satisfied, an error occurs. The error occurrence is indicated by the WA bit (bit 1) in FPFR. FMPAR Bit : Bit : Bit : Bit : 31 MOA31 23 MOA23 15 MOA15 7 MOA7 30 MOA30 22 MOA22 14 MOA14 6 MOA6 29 MOA29 21 MOA21 13 MOA13 5 MOA5 28 MOA28 20 MOA20 12 MOA12 4 MOA4 27 MOA27 19 MOA19 11 MOA11 3 MOA3 26 MOA26 18 MOA18 10 MOA10 2 MOA2 25 MOA25 17 MOA17 9 MOA9 1 MOA1 24 MOA24 16 MOA16 8 MOA8 0 MOA0 Bits 31 to 0--MOA31 to MOA0: Store the start address of the programming destination on the user MAT. The consecutive 128-byte programming is executed starting from the specified start address of the user MAT. Therefore, the specified programming start address becomes a 128-byte boundary and MOA6 to MOA0 are always 0. Rev. 2.0, 06/04, page 603 of 980 (b) Flash multipurpose data destination parameter (FMPDR: general register ER0 of CPU): This parameter indicates the start address in the area which stores the data to be programmed in the user MAT. When the storage destination of the program data is in flash memory, an error occurs. The error occurrence is indicated by the WD bit (bit 2) in FPFR. FMPDR Bit : Bit : Bit : Bit : 31 MOD31 23 MOD23 15 MOD15 7 MOD7 30 MOD30 22 MOD22 14 MOD14 6 MOD6 29 MOD29 21 MOD21 13 MOD13 5 MOD5 28 MOD28 20 MOD20 12 MOD12 4 MOD4 27 MOD27 19 MOD19 11 MOD11 3 MOD3 26 MOD26 18 MOD18 10 MOD10 2 MOD2 25 MOD25 17 MOD17 9 MOD9 1 MOD1 24 MOD24 16 MOD16 8 MOD8 0 MOD0 Bits 31 to 0--MOD31 to MOD0: Store the start address of the area which stores the program data for the user MAT. The consecutive 128-byte data is programmed to the user MAT starting from the specified start address. (c) Flash pass/fail parameter (FPFR: general register R0L of CPU) An explanation of FPFR as the return value indicating the programming result is provided here. Bit : 7 0 6 MD 5 EE 4 FK 3 0 2 WD 1 WA 0 SF Bit 7--Unused: Returns 0. Bit 6--Programming Mode Related Setting Error Detect (MD): Returns the check result of whether the signal input to the FWE pin is high and whether the error protection state is entered. When a low-level signal is input to the FWE pin or the error protection state is entered, 1 is written to this bit. The input level to the FWE pin and the error protection state can be confirmed with the FWE bit (bit 7) and the FLER bit (bit 4) in FCCS, respectively. For conditions to enter the error protection state, see section 18.6.3, Error Protection. Bit 6 MD 0 1 Description FWE and FLER settings are normal (FWE = 1, FLER = 0) FWE = 0 or FLER = 1, and programming cannot be performed Rev. 2.0, 06/04, page 604 of 980 Bit 5-Programming Execution Error Detect (EE): 1 is returned to this bit when the specified data could not be written because the user MAT was not erased or when flash-memory related register settings are partially changed on returning from the user branch processing. If this bit is set to 1, there is a high possibility that the user MAT is partially rewritten. In this case, after removing the error factor, erase the user MAT. If FMATS is set to H'AA and the user boot MAT is selected, an error occurs when programming is performed. In this case, both the user MAT and user boot MAT are not rewritten. Programming of the user boot MAT should be performed in the boot mode or PROM mode. Bit 5 EE 0 1 Description Programming has ended normally Programming has ended abnormally (programming result is not guaranteed) Bit 4--Flash Key Register Error Detect (FK): Returns the check result of the value of FKEY before the start of the programming processing. Bit 4 FK 0 1 Description FKEY setting is normal (FKEY = H'5A) FKEY setting is error (FKEY = value other than H'5A) Bit 3--Unused: Returns 0. Bit 2--Write Data Address Detect (WD): When flash memory area is specified as the start address of the storage destination of the program data, an error occurs. Bit 2 WD 0 1 Description Setting of write data address is normal Setting of write data address is abnormal Bit 1--Write Address Error Detect (WA): When the following area is specified as the start address of the programming destination, an error occurs. 1. If the start address is outside the flash memory area 2. If the specified address is not a 128-byte boundary (A6 to A0 are not 0) Rev. 2.0, 06/04, page 605 of 980 Bit 1 WA 0 1 Description Setting of programming destination address is normal Setting of programming destination address is abnormal Bit 0--Success/Fail (SF): Indicates whether the program processing is ended normally or not. Bit 0 SF 0 1 Description Programming is ended normally (no error) Programming is ended abnormally (error occurs) (4) Erasure Execution When flash memory is erased, the erase-block number on the user MAT must be passed to the erasing program which is downloaded. This is set to the FEBS parameter (general register ER0). One block is specified from the block number 0 to 15. For details on the erasing processing procedure, see section 18.5.2, User Program Mode. (a) Flash erase block select parameter (FEBS: general register ER0 of CPU) This parameter specifies the erase-block number. The several block numbers cannot be specified. Bit : Bit : 31 0 23 0 15 0 7 EBS7 30 0 22 0 14 0 6 EBS6 29 0 21 0 13 0 5 EBS5 28 0 20 0 12 0 4 EBS4 27 0 19 0 11 0 3 EBS3 26 0 18 0 10 0 2 EBS2 25 0 17 0 9 0 1 EBS1 24 0 16 0 8 0 0 EBS0 Bit : Bit : Bits 31 to 8--Unused: Only 0 may be written to these bits. Bits 7 to 0--Erase Block (EB7 to EB0): Set the erase-block number in the range from 0 to 15. 0 corresponds to the EB0 block and 15 corresponds to the EB15 block. An error occurs when the number other than 0 to 15 is set. Rev. 2.0, 06/04, page 606 of 980 (b) Flash pass/fail parameter (FPFR: general register R0L of CPU) An explanation of FPFR as the return value indicating the erase result is provided here. Bit : 7 0 6 MD 5 EE 4 FK 3 EB 2 0 1 0 0 SF Bit 7--Unused: Returns 0. Bit 6--Erasure Mode Related Setting Error Detect (MD): Returns the check result of whether the signal input to the FWE pin is high and whether the error protection state is entered. When a low-level signal is input to the FWE pin or the error protection state is entered, 1 is written to this bit. The input level to the FWE pin and the error protection state can be confirmed with the FWE bit (bit 7) and the FLER bit (bit 4) in FCCS, respectively. For conditions to enter the error protection state, see section 18.6.3, Error Protection. Bit 6 MD 0 1 Description FWE and FLER settings are normal (FWE = 1, FLER = 0) FWE = 0 or FLER = 1, and erasure cannot be performed Bit 5--Erasure Execution Error Detect (EE): 1 is returned to this bit when the user MAT could not be erased or when flash-memory related register settings are partially changed on returning from the user branch processing. If this bit is set to 1, there is a high possibility that the user MAT is partially erased. In this case, after removing the error factor, erase the user MAT. If FMATS is set to H'AA and the user boot MAT is selected, an error occurs when erasure is performed. In this case, both the user MAT and user boot MAT are not erased. Erasing of the user boot MAT should be performed in the boot mode or PROM mode. Bit 5 EE 0 1 Description Erasure has ended normally Erasure has ended abnormally (erasure result is not guaranteed) Bit 4--Flash Key Register Error Detect (FK): Returns the check result of FKEY value before start of the erasing processing. Rev. 2.0, 06/04, page 607 of 980 Bit 4 FK 0 1 Description FKEY setting is normal (FKEY = H'5A) FKEY setting is error (FKEY = value other than H'5A) Bit 3--Erase Block Select Error Detect (EB): Returns the check result whether the specified erase-block number is in the block range of the user MAT. Bit 3 EB 0 1 Description Setting of erase-block number is normal Setting of erase-block number is abnormal Bits 2 to 1--Unused: Return 0. Bit 0--Success/Fail (SF): Indicates whether the erasing processing is ended normally or not. Bit 0 SF 0 1 Description Erasure is ended normally (no error) Erasure is ended abnormally (error occurs) 18.4.4 RAM Control Register (RAMCR) When the realtime programming of the user MAT is emulated, RAMCR sets the area of the user MAT which is overlapped with a part of the on-chip RAM. RAMCR is initialized to H'F0 at a power-on reset or in hardware standby mode and is not initialized in software standby mode. The RAMCR setting must be executed in user mode or in user program mode. For the division method of the user-MAT area, see table 18.7. In order to operate the emulation function certainly, the target MAT of the RAM emulation must not be accessed immediately after RAMCR is programmed. If it is accessed, the normal access is not guaranteed. Bit : Initial value : R/W : 7 -- 1 R 6 -- 1 R 5 -- 1 R 4 -- 1 R 3 RAMS 0 R/W 2 RAM2 0 R/W 1 RAM1 0 R/W 0 RAM0 0 R/W Bits 7 to 4--Reserved: These bits are always read as 1. The write value should always be 1. Rev. 2.0, 06/04, page 608 of 980 Bit 3--RAM Select (RAMS): Sets whether the user MAT is emulated or not. When RAMS = 1, all blocks of the user MAT are in the programming/erasing protection state. Bit 3 RAMS 0 1 Description Emulation is not selected Programming/erasing protection of all user-MAT blocks is invalid Emulation is selected Programming/erasing protection of all user-MAT blocks is valid (Initial value) Bits 2 to 0--User MAT Area Select: These bits are used with bit 3 and select the user-MAT area to be overlapped with the on-chip RAM (see table 18.7). Table 18.7 Division of User MAT Area RAM Area H'FFE000 to H'FFEFFF H'000000 to H'000FFF H'001000 to H'001FFF H'002000 to H'002FFF H'003000 to H'003FFF H'004000 to H'004FFF H'005000 to H'005FFF H'006000 to H'006FFF H'007000 to H'007FFF Note: * Don't care. Block Name RAM area (4 kbytes) EB0 (4kbytes) EB1 (4kbytes) EB2 (4kbytes) EB3 (4kbytes) EB4 (4kbytes) EB5 (4kbytes) EB6 (4kbytes) EB7 (4kbytes) RAMS 0 1 1 1 1 1 1 1 1 RAM2 * 0 0 0 0 1 1 1 1 RAM1 * 0 0 1 1 0 0 1 1 RAM0 * 0 1 0 1 0 1 0 1 18.4.5 Flash Vector Address Control Register (FVACR) FVACR modifies the space which reads the vector table data of the NMI interrupts. Normally the vector table data is read from the address spaces from H'00001C to H'00004F. However, the vector table can be read from the internal I/O register (FVADRR to FVADRL) by the FVACR setting. FVACR is initialized to H'00 at a power-on reset or in hardware standby mode. All interrupts including NMI must be prohibited in the programming/erasing processing or during downloading on-chip program. When if it is not possible to avoid using the NMI interrupt due to system requirements, such as during system error processing, FVACR and FVADRR to FVADRL must be set and the interrupt exception processing routine must be set in the on-chip RAM. Rev. 2.0, 06/04, page 609 of 980 Bit : Initial value : R/W : 7 FVCHGE 0 R/W 6 -- 0 R/W 5 -- 0 R/W 4 -- 0 R/W 3 2 1 0 FVSEL3 FVSEL2 FVSEL1 FVSEL0 0 R/W 0 R/W 0 R/W 0 R/W Bit 7--Vector Switch Function Valid (FVCHGE): Selects whether the function for modifying the space which reads the vector table data is valid or invalid. When FVCHGE = 1, the vector table data can be read from the internal I/O registers (FVADRR to FVADRL). Bit 7 FVCHGE 0 1 Description Function for modifying the space which reads the vector table data is invalid (Initial value) Function for modifying the space which reads the vector table data is valid Bits 6 to 4--Reserved: These bits are always read as 0. The write value should always be 0. Bits 3 to 0--Interrupt Source Select (FVSEL3 to FVSEL0): The vector table of the NMI interrupt processing can be in the internal I/O registers (FVADRR to FVADRL) by setting this bit. Interrupt Source Bits Bit 3 FVSEL3 0 0 0 0 1 1 1 1 Bit 2 FVSEL2 0 0 0 1 0 0 0 1 Bit 1 FVSEL1 0 0 1 -- 0 0 1 -- Bit 0 FVSEL0 0 1 -- -- 0 1 -- -- Vector table data is in internal I/O register (FVADRR to FVADRL) Setting prohibited Function Vector table data is in area 0 (H'00001C to H'00004F) Setting prohibited (Initial value) Rev. 2.0, 06/04, page 610 of 980 18.4.6 Flash Vector Address Data Register (FVADR) When the function for switching the space which reads the vector table data by using FVACR is valid, FVADR stores the vector data. FVADR is configured by the four 8-bit registers (FVADRR, FVADRE, FVADRH, and FVADRL). FVADR is initialized to H'00000000 at a power-on reset or in hardware standby mode. Bit : Initial value : R/W : 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00000000000000000000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W FVADRR FVADRE FVADRH FVADRL Vector address is set Rev. 2.0, 06/04, page 611 of 980 18.5 On-Board Programming Mode When the pin is set in on-board programming mode and the reset start is executed, the on-board programming state that can program/erase the on-chip flash memory is entered. On-board programming mode has three operating modes: user programming mode, user boot mode, and boot mode. For details on the pin setting for entering each mode, see table 18.1. For details on the state transition of each mode for flash memory, see figure 18.2. 18.5.1 Boot Mode Boot mode executes programming/erasing user MAT and user boot MAT by means of the control command and program data transmitted from the host using the on-chip SCI. The tool for transmitting the control command and program data must be prepared in the host. The SCI communication mode is set to asynchronous mode. When reset start is executed after this LSI's pin is set in boot mode, the boot program in the microcomputer is initiated. After the SCI bit rate is automatically adjusted, the communication with the host is executed by means of the control command method. The system configuration diagram in boot mode is shown in figure 18.6. For details on the pin setting in boot mode, see table 18.1. The NMI and other interrupts are ignored in boot mode. Make sure the NMI and other interrupts do not occur in the user system. This LSI Control command, analysis execution software (on-chip) Flash memory Host Boot Control command, program data programming tool and program data Reply response RxD1 On-chip SCI1 TxD1 On-chip RAM Figure 18.6 System Configuration in Boot Mode SCI Interface Setting by Host: When boot mode is initiated, this LSI measures the low period of asynchronous SCI-communication data (H'00), which is transmitted consecutively by the host. The SCI transmit/receive format is set to 8-bit data, 1 stop bit, and no parity. This LSI calculates the bit rate of transmission by the host by means of the measured low period and transmits the bit Rev. 2.0, 06/04, page 612 of 980 adjustment end sign (1 byte of H'00) to the host. The host must confirm that this bit adjustment end sign (H'00) has been received normally and transmits 1 byte of H'55 to this LSI. When reception is not executed normally, boot mode is initiated again (reset) and the operation described above must be executed. The bit rate between the host and this LSI is not matched by the bit rate of transmission by the host and system clock frequency of this LSI. To operate the SCI normally, the transfer bit rate of the host must be set to 9,600 bps or 19,200 bps. The system clock frequency which can automatically adjust the transfer bit rate of the host and the bit rate of this LSI is shown in table 18.8. Boot mode must be initiated in the range of this system clock. Start bit D0 D1 D2 D3 D4 D5 D6 D7 Stop bit Measure low period (9 bits) (data is H'00) High period of at least 1 bit Figure 18.7 Automatic Adjustment Operation of SCI Bit Rate Table 18.8 System Clock Frequency that Can Automatically Adjust Bit Rate of This LSI Bit rate of host 9,600 bps 19,200 bps System clock frequency which can automatically adjust bit rate of this LSI 10 to 25 MHz 16 to 25 MHz State Transition: The overview of the state transition after boot mode is initiated is shown in figure 18.8. For details on boot mode, refer to section 18.10.1, Serial Communications Interface Specification for Boot Mode. 1. Bit rate adjustment After boot mode is initiated, the bit rate of the SCI interface is adjusted with that of the host. 2. Waiting for inquiry set command For inquiries about user-MAT size and configuration, MAT start address, and support state, the required information is transmitted to the host. 3. Automatic erasure of all user MAT and user boot MAT After inquiries have finished, all user MAT and user boot MAT are automatically erased. Rev. 2.0, 06/04, page 613 of 980 4. Waiting for programming/erasing command * When the program preparation notice is received, the state for waiting program data is entered. The programming start address and program data must be transmitted following the programming command. When programming is finished, the programming start address must be set to H'FFFFFFFF and transmitted. Then the state for waiting program data is returned to the state of programming/erasing command wait. * When the erasure preparation notice is received, the state for waiting erase-block data is entered. The erase-block number must be transmitted following the erasing command. When the erasure is finished, the erase-block number must be set to H'FF and transmitted. Then the state for waiting erase-block data is returned to the state for waiting programming/erasing command. The erasure must be executed when reset start is not executed and the specified block is programmed after programming is executed in boot mode. When programming can be executed by only one operation, all blocks are erased before the state for waiting programming/erasing/other command is entered. The erasing operation is not required. * There are many commands other than programming/erasing. Examples are sum check, blank check (erasure check), and memory read of the user MAT/user boot MAT and acquisition of current status information. Note that memory read of the user MAT/user boot MAT can only read the program data after all user MAT/user boot MAT has automatically been erased. Rev. 2.0, 06/04, page 614 of 980 (Bit rate adjustment) H'00 to H'00 reception Boot mode initiation (reset by boot mode) H'00 transmission (adjustment completed) Bit rate adjustment H'55 rece ption 1 2 Wait for inquiry setting command Inquiry command reception Inquiry command response Processing of inquiry setting command 3 All user MAT and user boot MAT erasure Read/check command reception Command response 4 Wait for programming/erasing command Processing of read/check command (Erasure command reception) (Erasure end) (Program end) (Program command reception) (Program data transmission) (Erase-block specification) Wait for erase-block data Wait for program data Figure 18.8 Overview of Boot Mode State Transition 18.5.2 User Program Mode The user MAT can be programmed/erased in user program mode. (The user boot MAT cannot be programmed/erased.) Programming/erasing is executed by downloading the program in the microcomputer. The overview flow is shown in figure 18.9. High voltage is applied to internal flash memory during the programming/erasing processing. Therefore, transition to reset or hardware standby must not be executed. Doing so may cause Rev. 2.0, 06/04, page 615 of 980 damage or destroy flash memory. If reset is executed accidentally, reset must be released after the reset input period, which is longer than normal 100 s. For information on the programming procedure refer to "Programming Procedure in User Program Mode", and for information on the erasing procedure refer to "Erasing Procedure in User Program Mode", below. For the overview of a processing that repeats erasing and programming by downloading the programming program and the erasing program in separate on-chip ROM areas using FTDAR, see "Erasing and Programming Procedure in User Program Mode" which appears later in this section. Programming/erasing start When programming, program data is prepared 1. RAM emulation mode must be canceled in advance. Download cannot be executed in emulation mode. 2. When the program data is made by means of emulation, use the FTDAR register to change the download destination. Note that the download area and the emulation area will overlap if FTDAR is in its initial status (H'00) or set to H'01. 3. Inputting the FWE pin to high level sets the FWE bit to 1. 4. Programming/erasing is executed only in the on-chip RAM. However, if program data is in a consecutive area and can be accessed by the MOV.B instruction of the CPU like SRAM/ROM, the program data can be in an external space. 5. After programming/erasing is finished, the FWE pin must be input to low and protected. FWE=1 ? Yes No Programming/erasing procedure program is transferred to the on-chip RAM and executed Programming/erasing end Figure 18.9 Programming/Erasing Overview Flow On-chip RAM Address Map when Programming/Erasing is Executed: Parts of the procedure program that are made by the user, like download request, programming/erasing procedure, and judgement of the result, must be executed in the on-chip RAM. The on-chip program that is to be downloaded is all in the on-chip RAM. Note that area in the on-chip RAM must be controlled so that these parts do not overlap. Figure 18.10 shows the program area to be downloaded. Rev. 2.0, 06/04, page 616 of 980 RAM emulation area or area that can be used by user Address RAMTOP(H'FFBF20) Area to be downloaded (Size : 2 kbytes) Unusable area in programming/erasing processing period DPFR (Return value: 1 byte) System use area (15 bytes) Programming/erasing entry Initialization process entry FTDAR setting FTDAR setting+16 FTDAR setting+32 Initialization + programming program or Initialization + erasing program FTDAR setting+2048 Area that can be used by user RAMEND(H'FFFF1F) Figure 18.10 RAM Map when Programming/Erasing is Executed Programming Procedure in User Program Mode: The procedures for download, initialization, and programming are shown in figure 18.11. Rev. 2.0, 06/04, page 617 of 980 Start programming procedure program Select on-chip program to be downloaded and set download destination by FTDAR Set FKEY to H'A5 1 (a) (b) (c) (d) (e) No Disable interrupts and bus master operation other than CPU Set FKEY to H'5A (i) (j) (k) (l) (m) No Download Clear FKEY to 0 Programming Set SCO to 1 and execute download Set parameter to ER0 and ER1 (FMPAR and FMPDR) Programming JSR FTDAR setting+16 DFPR=0? Yes FPFR=0? Yes No Required data programming is completed? Download error processing Set the FPEFEQ and FUBRA parameters (f) (g) (h) No Clear FKEY and programming error processing Initialization Initialization JSR FTDAR setting+32 (n) (o) Yes Clear FKEY to 0 End programming procedure program FPFR=0? Yes Initialization error processing 1 Figure 18.11 Programming Procedure The details of the programming procedure are described below. The procedure program must be executed in an area other than the flash memory to be programmed. Especially the part where the SCO bit in FCCS is set to 1 for downloading must be executed in the on-chip RAM. The area that can be executed in the steps of the user procedure program (on-chip RAM, user MAT, and external space) is shown in section 18.10.3, Procedure Program and Storable Area for Programming Data. The following description assumes the area to be programmed on the user MAT is erased and program data is prepared in the consecutive area. When erasing is not executed, erasing is executed before writing. 128-byte programming is performed in one program processing. When more than 128-byte programming is performed, programming destination address/program data parameter is updated in 128-byte units and programming is repeated. When less than 128-byte programming is performed, data must total 128 bytes by adding the invalid data. If the invalid data to be added is H'FF, the program processing period can be shorted. Rev. 2.0, 06/04, page 618 of 980 (a) Select the on-chip program to be downloaded and the download destination. When the PPVS bit of FPCS is set to 1, the programming program is selected. Several programming/erasing programs cannot be selected at one time. If several programs are set, download is not performed and a download error is returned to the source select error detect (SS) bit in the DPFR parameter. Specify the start address of the download destination by FTDAR. (b) Program H'A5 in FKEY If H'A5 is not written to FKEY for protection, 1 cannot be written to the SCO bit for download request. (c) 1 is written to the SCO bit of FCCS and then download is executed. To write 1 to the SCO bit, the following conditions must be satisfied. * RAM emulation mode is canceled. * H'A5 is written to FKEY. * The SCO bit writing is executed in the on-chip RAM. When the SCO bit is set to 1, download is started automatically. When the SCO bit is returned to the user procedure program, the SCO is cleared to 0. Therefore, the SCO bit cannot be confirmed to be 1 in the user procedure program. The download result can be confirmed only by the return value of the DPFR parameter. Before the SCO bit is set to 1, incorrect judgement must be prevented by setting the DPFR parameter, that is one byte of the start address of the on-chip RAM area specified by FTDAR, to a value other than the return value (H'FF). When download is executed, particular interrupt processing, which is accompanied by the bank switch as described below, is performed as an internal microcomputer processing. Four NOP instructions are executed immediately after the instructions that set the SCO bit to 1. * The user-MAT space is switched to the on-chip program storage area. * After the selection condition of the download program and the address set in FTDAR are checked, the transfer processing is executed starting from the on-chip RAM address specified by FTDAR. * The SCO bits in FPCS, FECS, and FCCS are cleared to 0. * The return value is set to the DPFR parameter. * After the on-chip program storage area is returned to the user-MAT space, the user procedure program is returned. The notes on download are as follows. In the download processing, the values are stored in general registers than CPU. Rev. 2.0, 06/04, page 619 of 980 No interrupts are accepted during download processing. However, interrupt requests other than NMI requests are held, so when processing returns to the user procedure program and interrupts are generated. NMI requests are discarded if the FVACR register value is H'00. However, if H'80 has been written to the FVACR register, they are held and the NMI interrupts are generated when processing returns to the user procedure program. The sources of the interrupt requests from the on-chip module and at the falling edge of the IRQ are held during downloading. The refresh can be put in the DRAM. When the level-detection interrupt requests are to be held, interrupts must be put until the download is ended. When hardware standby mode is entered during download processing, the normal download cannot be guaranteed in the on-chip RAM. Therefore, download must be executed again. Since a stack area of a maximum 128 bytes is used, the area must be saved before setting the SCO bit to 1. If flash memory is accessed by the DMAC or BREQ during downloading, the operation cannot be guaranteed. Therefore, access by the DMAC or BREQ must not be executed. (d) FKEY is cleared to H'00 for protection. (e) The value of the DPFR parameter must be checked and the download result must be confirmed. A recommended procedure for confirming the download result is shown below. * Check the value of the DPFR parameter (one byte of start address of the download destination specified by FTDAR). If the value is H'00, download has been performed normally. If the value is not H'00, the source that caused download to fail can be investigated by the description below. * If the value of the DPFR parameter is the same as before downloading (e.g. H'FF), the address setting of the download destination in FTDAR may be abnormal. In this case, confirm the setting of the TDER bit (bit 7) in FTDAR. * If the value of the DPFR parameter is different from before downloading, check the SS bit (bit 2) and the FK bit (bit 1) in the DPFR parameter to ensure that the download program selection and FKEY register setting were normal, respectively. (f) The operating frequency and user branch destination are set to the FPEFEQ and FUBRA parameters for initialization. * The current frequency of the CPU clock is set to the FPEFEQ parameter (general register: ER0). Rev. 2.0, 06/04, page 620 of 980 For the settable range of the FPEFEQ parameter, see section 21.4.1, Clock Timing. When the frequency is set out of this range, an error is returned to the FPFR parameter of the initialization program and initialization is not performed. For details on the frequency setting, see the description in 18.4.3(2) (a) Flash programming/erasing frequency parameter (FPEFEQ: general register ER0 of CPU). * The start address in the user branch destination is set to the FUBRA parameter (general register: ER1). Not available in the H8/3029, 0 must be set to FUBRA. When the user branch is executed, the branch destination is executed in a user MAT other than the one that is to be programmed. The area of the on-chip program that is downloaded cannot be set. The program processing must be returned from the user branch processing by the RTS instruction. See the description in 18.4.3 (2) (b) Flash user branch address setting parameter (FUBRA: general register ER1 of CPU). (g) Initialization When a programming program is downloaded, the initialization program is also downloaded to the on-chip RAM. There is an entry point of the initialization program in the area from (download start address set by FTDAR) + 32 bytes. The subroutine is called and initialization is executed by using the following steps. MOV.L JSR NOP #DLTOP+32,ER2 @ER2 ; Set entry address to ER2 ; Call initialization routine * The general registers other than R0L are saved in the initialization program. * R0L is a return value of the FPFR parameter. * Since the stack area is used in the initialization program, a stack area of a maximum 128 bytes must be saved in RAM. * Interrupts can be accepted during the execution of the initialization program. The program storage area and stack area in the on-chip RAM and register values must not be destroyed. (h) The return value in the initialization program, FPFR (general register R0L) is judged. (i) All interrupts and the use of a bus master other than the CPU are prohibited. The specified voltage is applied for the specified time when programming or erasing. If interrupts occur or the bus mastership is moved to other than the CPU during this time, more than the specified voltage will be applied and flash memory may be damaged. Therefore, interrupts and movement of bus mastership to DMAC or BREQ and DRAM refresh other than the CPU are prohibited. Rev. 2.0, 06/04, page 621 of 980 The interrupt processing prohibition is set up by setting the bit 7 (I) in the condition code register (CCR) of the CPU to b'1. Then interrupts other than NMI are held and are not executed. The NMI interrupts must not occur in the user system. The interrupts that are held must be processed in executed after all program processing. When the bus mastership is moved to DMAC or BREQ or DRAM refresh except for the CPU, the error protection state is entered. Therefore, reservation of bus mastership by DMAC or BREQ is prohibited. (j) FKEY must be set to H'5A and the user MAT must be prepared for programming. (k) The parameter which is required for programming is set. The start address of the programming destination of the user MAT (FMPAR) is set to general register ER1. The start address of the program data storage area (FMPDR) is set to general register ER0. * Example of the FMPAR setting FMPAR specifies the programming destination address. When an address other than one in the user MAT area is specified, even if the programming program is executed, programming is not executed and an error is returned to the return value parameter FPFR. Since the unit is 128 bytes, the lower eight bits (A7 to A0) must be in the 128byte boundary of H'00 or H'80. * Example of the FMPDR setting When the storage destination of the program data is flash memory, even if the program execution routine is executed, programming is not executed and an error is returned to the FPFR parameter. In this case, the program data must be transferred to the on-chip RAM and then programming must be executed. (l) Programming There is an entry point of the programming program in the area from (download start address set by FTDAR) + 16 bytes of on-chip RAM. The subroutine is called and programming is executed by using the following steps. MOV.L JSR NOP #DLTOP+16,ER2 @ER2 ; Set entry address to ER2 ; Call programming routine * The general registers other than R0L are saved in the programming program. * R0 is a return value of the FPFR parameter. Rev. 2.0, 06/04, page 622 of 980 * Since the stack area is used in the programming program, a stack area of a maximum 128 bytes must be reserved in RAM (m) The return value in the programming program, FPFR (general register R0L) is judged. (n) Determine whether programming of the necessary data has finished. If more than 128 bytes of data are to be programmed, specify FMPAR and FMPDR in 128byte units, and repeat steps (l) to (m). Increment the programming destination address by 128 bytes and update the programming data pointer correctly. If an address which has already been programmed is written to again, not only will a programming error occur, but also flash memory will be damaged. (o) After programming finishes, clear FKEY and specify software protection. If this LSI is restarted by a power-on reset immediately after user MAT programming has finished, secure a reset period (period of RES = 0) that is at least as long as normal 100 s. Erasing Procedure in User Program Mode: The procedures for download, initialization, and erasing are shown in figure 18.12. Start erasing procedure program Select on-chip program to be downloaded and set download destination by FTDAR Set FKEY to H'A5 1 Disable interrupts and bus master operation other than CPU Set FKEY to H'5A (a) Download Set SCO to 1 and execute download Clear FKEY to 0 DPFR = 0? Set FEBS parameter Erasing JSR FTDAR setting+16 (b) (c) (d) No Erasing No Download error processing FPFR=0 ? Yes No Required block erasing is completed? Yes Clear FKEY and erasing error processing Set the FPEFEQ and FUBRA parameters Initialization (e) (f) Initialization JSR FTDAR setting+32 Yes Clear FKEY to 0 FPFR=0 ? No Yes Initialization error processing End erasing procedure program 1 Figure 18.12 Erasing Procedure Rev. 2.0, 06/04, page 623 of 980 The details of the erasing procedure are described below. The procedure program must be executed in an area other than the user MAT to be erased. Especially the part where the SCO bit in FCCS is set to 1 for downloading must be executed in on-chip RAM. The area that can be executed in the steps of the user procedure program (on-chip RAM, user MAT, and external space) is shown in section 18.10.3, Procedure Program and Storable Area for Programming Data. For the downloaded on-chip program area, refer to the RAM map for programming/erasing in figure 18.10, RAM Map when Programming/Erasing is Executed. A single divided block is erased by one erasing processing. For block divisions, refer to figure 18.4, Block Division of User MAT. To erase two or more blocks, update the erase block number and perform the erasing processing for each block. (a) Select the on-chip program to be downloaded Set the EPVB bit in FECS to 1. Several programming/erasing programs cannot be selected at one time. If several programs are set, download is not performed and a download error is returned to the source select error detect (SS) bit in the DPFR parameter. The procedures to be carried out after setting FKEY, e.g. download and initialization, are the same as those in the programming procedure. For details, refer to Programming Procedure in User Program Mode in section 18.5.2. (b) Set the FEBS parameter necessary for erasure Set the erase block number of the user MAT in the flash erase block select parameter FEBS (general register ER0). If a value other than an erase block number of the user MAT is set, no block is erased even though the erasing program is executed, and an error is returned to the return value parameter FPFR. (c) Erasure Similar to as in programming, there is an entry point of the erasing program in the area from (download start address set by FTDAR) + 16 bytes of on-chip RAM. The subroutine is called and erasing is executed by using the following steps. MOV.L JSR NOP #DLTOP+16,ER2 @ER2 ; Set entry address to ER2 ; Call erasing routine * The general registers other than R0L are saved in the erasing program. * R0 is a return value of the FPFR parameter. * Since the stack area is used in the erasing program, a stack area of a maximum 128 bytes must be reserved in RAM Rev. 2.0, 06/04, page 624 of 980 (d) The return value in the erasing program, FPFR (general register R0L) is judged. (e) Determine whether erasure of the necessary blocks has finished. If more than one block is to be erased, update the FEBS parameter and repeat steps (b) and (c). Blocks that have already been erased can be erased again. (f) After erasure finishes, clear FKEY and specify software protection. If this LSI is restarted by a power-on reset immediately after user MAT erasure has finished, secure a reset period (period of RES = 0) that is at least as long as normal 100 s. (4) Erasing and Programming Procedure in User Program Mode By changing the on-chip RAM address of the download destination in FTDAR, the erasing program and programming program can be downloaded to separate on-chip RAM areas. Figure 18.13 shows an example of repetitively executing RAM emulation, erasing, and programming. 1 Start procedure program Set FTDAR to H'02 (Specify H'FFCF20 as download destination) Enter RAM emulation mode and tune data in on-chip RAM Emulation/Erasing/Programming Erasing program download Cancel RAM emulation mode Download erasing program Initialize erasing program Erase relevant block (execute erasing program) Set FMPDR to H'FFE000 to program relevant block (execute programming program) Confirm operation Programming program download Set FTDAR to H'03 (Specify H'FFBF20 as download destination) Download programming program Initialize programming program End ? Yes No 1 End procedure program Figure 18.13 Sample Procedure of Repeating RAM Emulation, Erasing, and Programming (Overview) Rev. 2.0, 06/04, page 625 of 980 In the above example, the erasing program and programming program are downloaded to areas excluding the 4 kbytes (H'FFE000 to H'FFEFFF) from the start of on-chip ROM. Download and initialization are performed only once at the beginning. In this kind of operation, note the following: * Be careful not to damage on-chip RAM with overlapped settings. In addition to the RAM emulation area, erasing program area, and programming program area, areas for the user procedure programs, work area, and stack area are reserved in on-chip RAM. Do not make settings that will overwrite data in these areas. * Be sure to initialize both the erasing program and programming program. Initialization by setting the FPEFEQ and FUBRA parameters must be performed for both the erasing program and the programming program. Initialization must be executed for both entry addresses: (download start address for erasing program) + 32 bytes (H'FFCF40 in this example) and (download start address for programming program) + 32 bytes (H'FFBF40 in this example). 18.5.3 User Boot Mode This LSI has user boot mode which is initiated with different mode pin settings than those in user program mode or boot mode. User boot mode is a user-arbitrary boot mode, unlike boot mode that uses the on-chip SCI. Only the user MAT can be programmed/erased in user boot mode. Programming/erasing of the user boot MAT is only enabled in boot mode or programmer mode. User Boot Mode Initiation: For the mode pin settings to start up user boot mode, see table 18.1. When the reset start is executed in user boot mode, the built-in check routine runs. The user MAT and user boot MAT states are checked by this check routine. While the check routine is running, NMI and all other interrupts cannot be accepted. Next, processing starts from the execution start address of the reset vector in the user boot MAT. At this point, H'AA is set to the flash MAT select register FMATS because the execution MAT is the user boot MAT. To enable NMI interrupts in a user boot MAT program, after the reset ends (RES = 1) and 400 s passes, set NMI to 1. User MAT Programming in User Boot Mode: For programming the user MAT in user boot mode, additional processings made by setting FMATS are required: switching from user-bootMAT selection state to user-MAT selection state, and switching back to user-boot-MAT selection state after programming completes. Rev. 2.0, 06/04, page 626 of 980 Figure 18.14 shows the procedure for programming the user MAT in user boot mode. Start programming procedure program 1 MAT switchover Select on-chip program to be downloaded and set download destination by FTDAR Set FKEY to H'A5 Set FMATS to value other than H'AA to select user MAT User-boot-MAT selection state Download Set FKEY to H'5A User-MAT selection state Set SCO to 1 and execute download Clear FKEY to 0 DPFR=0 ? Yes Set parameter to ER0 and ER1 (FMPAR and FMPDR) No Programming Programming JSR FTDAR setting+16 FPFR=0 ? Download error processing Initialization Set the FPEFEQ and FUBRA parameters Initialization JSR FTDAR setting+32 FPFR=0 ? No Yes Clear FKEY and programming error processing* No Required data programming is completed? Yes No Clear FKEY to 0 Yes Initialization error processing Disable interrupts and bus master operation other than CPU Set FMATS to H'AA to select user boot MAT End programming procedure program MAT switchover 1 User-boot-MAT selection state Note: * The MAT must be switched by FMATS to perform the programming error processing in the user boot MAT. Figure 18.14 Procedure for Programming User MAT in User Boot Mode The difference between the programming procedures in user program mode and user boot mode is whether the MAT is switched or not as shown in figure 18.14. In user boot mode, the user boot MAT can be seen in the flash memory space with the user MAT hidden in the background. The user MAT and user boot MAT are switched only while the user MAT is being programmed. Because the user boot MAT is hidden while the user MAT is being programmed, the procedure program must be located in an area other than flash memory. After programming finishes, switch the MATs again to return to the first state. MAT switchover is enabled by writing a specific value to FMATS. However note that while the MATs are being switched, the LSI is in an unstable state, e.g. access to a MAT is not allowed until MAT switching is completely finished, and if an interrupt occurs, from which MAT the interrupt vector is read from is undetermined. Perform MAT switching in accordance with the description in section 18.8, Switching between User MAT and User Boot MAT. Rev. 2.0, 06/04, page 627 of 980 Except for MAT switching, the programming procedure is the same as that in user program mode. The area that can be executed in the steps of the user procedure program (on-chip RAM, user MAT, and external space) is shown in section 18.10.3, Procedure Program and Storable Area for Programming Data. User MAT Erasing in User Boot Mode: For erasing the user MAT in user boot mode, additional processings made by setting FMATS are required: switching from user-boot-MAT selection state to user-MAT selection state, and switching back to user-boot-MAT selection state after erasing completes. Figure 18.15 shows the procedure for erasing the user MAT in user boot mode. Start erasing procedure program Select on-chip program to be downloaded 1 MAT switchover Set FMATS to value other than H'AA to select user MAT User-boot-MAT selection state Set FKEY to H'A5 and set download destination by FTDAR Download Set FKEY to H'5A User-MAT selection state Set SCO to 1 and execute download Clear FKEY to 0 DPFR=0 ? Yes Set FEBS parameter Programming JSR FTDAR setting+16 FPFR=0 ? No Download error processing Erasing Initialization Set the FPEFEQ and FUBRA parameters Initialization JSR FTDAR setting+32 FPFR=0 ? No No Yes Clear FKEY and erasing error processing Required block erasing is completed? Yes No Clear FKEY to 0 Yes Initialization error processing Disable interrupts and bus master operation other than CPU Set FMATS to H'AA to select user boot MAT End erasing procedure program MAT switchover 1 User-boot-MAT selection state Note: The MAT must be switched by FMATS to perform the erasing error processing in the user boot MAT. Figure 18.15 Procedure for Erasing User MAT in User Boot Mode The difference between the erasing procedures in user program mode and user boot mode depends on whether the MAT is switched or not as shown in figure 18.15. Rev. 2.0, 06/04, page 628 of 980 MAT switching is enabled by writing a specific value to FMATS. However note that while the MATs are being switched, the LSI is in an unstable state, e.g. access to a MAT is not allowed until MAT switching is completed finished, and if an interrupt occurs, from which MAT the interrupt vector is read from is undetermined. Perform MAT switching in accordance with the description in section 18.8, Switching between User MAT and User Boot MAT. Except for MAT switching, the erasing procedure is the same as that in user program mode. The area that can be executed in the steps of the user procedure program (on-chip RAM, user MAT, and external space) is shown in section 18.10.3, Procedure Program and Storable Area for Programming Data. Rev. 2.0, 06/04, page 629 of 980 18.6 Protection There are two kinds of flash memory program/erase protection: hardware and software protection. 18.6.1 Hardware Protection Programming and erasing of flash memory is forcibly disabled or suspended by hardware protection. In this state, the downloading of an on-chip program and initialization of the flash memory are possible. However, an activated program for programming or erasure cannot program or erase locations in a user MAT, and the error in programming/erasing is reported in the parameter FPFR. Rev. 2.0, 06/04, page 630 of 980 Table 18.9 Hardware Protection Function to be Protected Item FWE-pin protection Description * The input of a low-level signal on the FWE pin clears the FWE bit of FCCS and the device enters a program/erase-protected state. A power-on reset (including a power-on reset by the WDT) and entry to standby mode reinitialize the program/erase interface register and the device enters a program/erase-protected state. Resetting by means of the RES pin after power is initially supplied will not make the device enter the reset state unless the RES pin is held low until oscillation has stabilized. In the case of a reset during operation, hold the RES pin low for the RES pulse width that is specified in the section on AC characteristics section. If the device is reset during programming or erasure, data values in the flash memory are not guaranteed. In this case, after keeping the RES pin low for at least 100 s, execute erasure and then execute programming again. Download -- Program/Erase Reset/standby protection * * 18.6.2 Software Protection Software protection is set up in any of three ways: by disabling the downloading of on-chip programs for programming and erasing, by means of a key code, and by the RAM-emulation register. Rev. 2.0, 06/04, page 631 of 980 Table 18.10 Software Protection Function to be Protected Item Protection by the SCO bit Description * Clearing the SCO bit in the FCCS register makes the device enter a program/erase-protected state, and this disables the downloading of the programming/erasing programs. Downloading and programming/erasing are disabled unless the required key code is written in the FKEY register. Different key codes are used for downloading and for programming/erasing. Setting the RAMS bit in the RAM emulation register (RAMER) makes the device enter a program/eraseprotected state. Download Program/Erase Protection by the FKEY register * Emulation protection * 18.6.3 Error Protection Error protection is a mechanism for aborting programming or erasure when an error occurs, in the form of the microcomputer entering runaway during programming/erasing of the flash memory or operations that are not according to the established procedures for programming/erasing. Aborting programming or erasure in such cases prevents damage to the flash memory due to excessive programming or erasing. If the microcomputer malfunctions during programming/erasing of the flash memory, the FLER bit in the FCCS register is set to 1 and the device enters the error-protection state, and this aborts the programming or erasure. The FLER bit is set in the following conditions: (1) When an interrupt, such as NMI, has occurred during programming/erasing (2) When the relevant block area of flash memory is read during programming/erasing (including a vector read or an instruction fetch) (3) When a SLEEP instruction (including software standby mode) is executed during programming/erasing (4) When a bus master other than the CPU, such as DMAC or BREQ, has obtained the bus right during programming/erasing Rev. 2.0, 06/04, page 632 of 980 Error protection is cancelled only by a power-on reset or by hardware-standby mode. Note that the reset should only be released after providing a reset input over a period longer than the normal 100 s period. Since high voltages are applied during programming/erasing of the flash memory, some voltage may remain after the error-protection state has been entered. For this reason, it is necessary to reduce the risk of damage to the flash memory by extending the reset period so that the charge is released. The state-transition diagram in figure 18.16 shows transitions to and from the error-protection state. Program mode Erase mode Read disabled Programming/erasing enabled FLER=0 4-5 = 0 or 56*; = 0 Err occ (S urren oft wa ce re sta or =0 4-5 6*;=0 5 nd by ) Reset or standby (Hardware protection) Read disabled Programming/erasing disabled FLER=0 or Error occurrence 4-5=0 or 56*;=0 Program/erase interface register is in its initial state. Error protection mode Read enabled Programming/erasing disabled FLER=1 Software-standby mode Error-protection mode (Software standby) Read disabled Cancel programming/erasing disabled software-standby mode FLER=1 Program/erase interface register is in its initial state. Figure 18.16 Transitions to and from the Error-Protection State Rev. 2.0, 06/04, page 633 of 980 18.7 Flash Memory Emulation in RAM To provide real-time emulation in RAM of data that is to be written to the flash memory, a part of the RAM can be overlaid on an area of flash memory (user MAT) that has been specified by the RAM control register (RAMCR). After the RAMCR setting is made, the RAM is accessible in both the user MAT area and as the RAM area that has been overlaid on the user MAT area. Such emulation is possible in both user mode and user-program mode. Figures 18.17 and 18.18 show an example of the emulation of realtime programming of the user MAT area. Start of emulation program Set RAMCR Write the data for tuning to the overlaid RAM area Execute application program No Tuning OK? Yes Cancel RAMCR setting Program the user MAT with the emulated block End of emulation program Figure 18.17 Emulation of Flash Memory in RAM Rev. 2.0, 06/04, page 634 of 980 This area is accessible as both a RAM area and as a flash memory area. H'00000 H'01000 H'02000 H'03000 H'04000 H'05000 H'06000 H'07000 H'08000 EB0 EB1 EB2 EB3 EB4 EB5 EB6 EB7 H'FFE000 H'FFEFFF H'FFBF20 Flash memory (user MAT) On-chip RAM EB8 to EB15 H'7FFFF H'FFFF1F Figure 18.18 Example of a RAM-Overlap Operation Figure 18.18 shows an example of an overlap on block area EB0 of the flash memory. Emulation is possible for a single area selected from among the eight areas, from EB0 to EB7, of user MAT bank 0. The area is selected by the setting of the RAM2 to RAM0 bits in the RAMCR register. (1) To overlap a part of the RAM on area EB0, to allow realtime programming of the data for this area, set the RAMCR register's RAMS bit to 1, and each of the RAM2 to RAM0 bits to 0. (2) Realtime programming is carried out using the overlaid area of RAM. In programming or erasing the user MAT, it is necessary to run a program that implements a series of procedural steps, including the downloading of a on-chip program. In this process, set the download area with FTDAR so that the overlaid RAM area and the area where the on-chip program is to be downloaded do not overlap. The initial setting (H'00) of FTDAR or a setting of H'01 causes part of the tuned data area to overlap with part of the download area. When using the initial setting of FTDAR, the data that is to be programmed must be saved beforehand in an area that is not used by the system. Figure 18.19 shows an example of programming of the data, after emulation has been completed, to the EB0 area in the user MAT. Rev. 2.0, 06/04, page 635 of 980 H'00000 H'01000 H'02000 H'03000 H'04000 H'05000 H'06000 H'07000 H'08000 EB0 EB1 EB2 EB3 EB4 EB5 EB6 EB7 (1) Cancel the emulation mode. (2) Transfer the user-created program/ erase-procedure program. (3) Download the on-chip programming/erasing programs, avoiding the tuning H'FFCF20 Download area Flash memory (user MAT) EB8 to EB15 Area for the programming-procedure program Copy of the tuned data H'FFD720 H'FFE000 H'FFEFFF On-chip RAM H'7FFFF H'FFFF1F Figure 18.19 Programming of the Data After Tuning (1) After the data to be programmed has fixed values, clear the RAMS bit to 0 to cancel the overlap of RAM. (2) Transfer the user programming/erasing procedure program to RAM. (3) Run the programming/erasing procedure program in RAM and download the on-chip programming/erasing program. Specify the download start address with FTDAR so that the tuned data area does not overlap with the download area. (4) When the EB0 area of the user MAT has not been erased, the programming program will be downloaded after erasure. Set the parameters FMPAR and FMPDR so that the tuned data is designated, and execute programming. Note: Setting the RAMS bit to 1 puts all the blocks in the flash MAT into a program/eraseprotected state regardless of the values of the RAM2 to RAM0 bits (emulation protection). In this state, downloading of the on-chip programs is also disabled, so clear the RAMS bit before actual programming or erasure. Rev. 2.0, 06/04, page 636 of 980 18.8 Switching between User MAT and User Boot MAT It is possible to alternate between the user MAT and user boot MAT. However, the following procedure is required because these MATs are allocated to address 0. (Switching to the user boot MAT disables programming and erasing. Programming of the user boot MAT should take place in boot mode or PROM mode.) (1) MAT switching by the FMATS register should always be executed from the on-chip RAM. (2) To ensure that the MAT that has been switched to is accessible, execute 4 NOP instructions in the on-chip RAM immediately before or after writing to the FMATS register of the on-chip RAM (this prevents access to the flash memory during MAT switching). (3) If an interrupt has occurred during switching, there is no guarantee of which memory MAT is being accessed. Always mask the maskable interrupts before switching between MATs. In addition, configure the system so that NMI interrupts do not occur during MAT switching. (4) After the MATs have been switched, take care because the interrupt vector table will also have been switched. If interrupt processing is to be the same before and after MAT switching, transfer the interrupt-processing routines to the on-chip RAM, and use the settings of the FVACR and FVADR registers to place the interrupt-vector table in the on-chip RAM . (5) Memory sizes of the user MAT and user boot MAT are different. When accessing the user boot MAT, do not access addresses above the top of its 10-kbyte memory space. If access goes beyond the 10-kbyte space, the values read are undefined. Procedure for switching to the user boot MAT Procedure for switching to the user MAT Procedure for switching to the user boot MAT (1) Mask interrupts (2) Write H'AA to the FMATS register. (3) Execute 4 NOP instructions before accessing the user boot MAT. Procedure for switching to the user MAT (1) Mask interrupts (2) Write a value other than H'AA to the FMATS register. (3) Execute 4 NOP instructions before or after accessing the user MAT. Figure 18.20 Switching between the User MAT and User Boot MAT Rev. 2.0, 06/04, page 637 of 980 18.8.1 Usage Notes 1. Download time of on-chip program The programming program that includes the initialization routine and the erasing program that includes the initialization routine are each 2 kbytes or less. Accordingly, when the CPU clock frequency is 25 MHz, the download for each program takes approximately 164s at maximum. 2. Write to flash-memory related registers by DMAC While an instruction in on-chip RAM is being executed, the DMAC can write to the SCO bit in FCCS that is used for a download request or FMATS that is used for MAT switching. Make sure that these registers are not accidentally written to, otherwise an on-chip program may be downloaded and damage RAM or a MAT switchover may occur and the CPU get out of control. Do not use DMAC to program FLASH related registers. 3. Compatibility with programming/erasing program of conventional F-ZTAT H8 microcomputer A programming/erasing program for flash memory used in the conventional F-ZTAT H8 microcomputer which does not support download of the on-chip program by a SCO transfer request cannot run in this LSI. Be sure to download the on-chip program to execute programming/erasing of flash memory in this LSI. 4. Monitoring runaway by WDT Unlike the conventional F-ZTAT H8 microcomputer, no countermeasures are available for a runaway by WDT during programming/erasing by the downloaded on-chip program. Prepare countermeasures (e.g. use of the user branch routine and periodic timer interrupts) for WDT while taking the programming/erasing time into consideration as required. Rev. 2.0, 06/04, page 638 of 980 18.9 PROM Mode Along with its on-board programming mode, this LSI also has a PROM mode as a further mode for the writing and erasing of programs and data. In the PROM mode, a general-purpose PROM programmer can freely be used to write programs to the on-chip ROM. Program/erase is possible on the user MAT and user boot MAT. The PROM programmer must support Renesas microcomputers with 512-kbyte flash memory units as a device type. A status-polling system is adopted for operation in automatic program, automatic erase, and status-read modes. In the status-read mode, details of the system's internal signals are output after execution of automatic programming or automatic erasure. In the PROM mode, provide a 12MHz input-clock signal. Table 18.11 PROM Mode Pin Pins Mode pin: P82, P81, P80 Setting 1, 0, 0 18.9.1 Pin Arrangement of the Socket Adapter Attach the socket adapter to the LSI in the way shown in figure 18.22. This allows conversion to 40 pins. Figure 18.21 shows the memory mapping of the on-chip ROM, and figure 18.22 shows the arrangement of the socket adapter's pins. Address in MCU mode H'000000 Address in PROM mode H'00000 Address in MCU mode H'000000 Address in PROM mode H'00000 On-chip ROM space (user boot MAT) 10kB H'0027FF H'027FF On-chip ROM space (user MAT) 512kB H'07FFFF H'7FFFF Figure 18.21 Mapping of On-Chip Flash Memory Rev. 2.0, 06/04, page 639 of 980 H8/3029 Pin No. 36 37 38 39 40 41 42 43 45 64 47 48 49 50 51 58 69 70 55 27 28 29 30 31 32 33 34 52 46 90 10 76,77,62,71,89,35,68 73,74,75,87,88,86,11,22,44,57,65,92,14 Pin Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 D0 D1 D2 D3 D4 D5 D6 D7 CE OE WE FWE VCC VSS RES XTAL EXTAL VCL N.C.(OPEN) Socket Adapter (40-Pin Conversion) HN27C4096HG (40 pins) Pin No. 21 22 23 24 25 26 27 28 29 31 32 33 34 35 36 37 38 39 10 19 18 17 16 15 14 13 12 2 20 3 4 1,40 Pin Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 CE OE WE FWE VCC VSS NC A20 A19 63 67 66 1 Power-on reset circuit Oscillator circuit Capacitor 11,30 5,6,7 8 9 Other Legend FWE I/O7 to 0 A18 to 0 CE OE WE : Flash-write enable : Data I/O : Address input : Chip enable : Output enable : Write enable Figure 18.22 Pin Arrangement of the Socket Adapter Rev. 2.0, 06/04, page 640 of 980 18.9.2 PROM Mode Operation Table 18.12 shows the settings for the operating modes of PROM mode, and table 18.13 lists the commands used in PROM mode. The following sections provide detailed information on each mode. * Memory-read mode: This mode supports reading, in units of bytes, from the user MAT or user boot MAT. * Auto-program mode: This mode supports the simultaneous programming of the user MAT and user boot MAT in 128-byte units. Status polling is used to confirm the end of automatic programming. * Auto-erase mode: This mode only supports the automatic erasing of the entire user MAT or user boot MAT. Status polling is used to confirm the end of automatic erasing. * Status-read mode: Status polling is used with automatic programming and automatic erasure. Normal completion can be detected by reading the signal on the I/O6 pin. In status-read mode, error information is output when an error has occurred. Table 18.12 Settings for Each Operating Mode of PROM Mode Pin Name Mode Read Output disable Command write Chip disable FWE H or L H or L H or L H or L CE L L L H OE L H H X WE H H L X I/O7 to 0 Data output Hi-Z Data input Hi-Z A18 to 0 Ain X *Ain X Notes: 1. The chip-disable mode is not a standby state; internally, it is an operational state. 2. To write commands when making a transition to the auto-program or auto-erase mode, input a high-level signal on the FWE pin. * Ain indicates that there is also an address input in auto-program mode. Rev. 2.0, 06/04, page 641 of 980 Table 18.13 Commands in PROM Mode Memory MAT to be Accessed User MAT User boot MAT Auto-program mode 129 User MAT User boot MAT Auto-erase mode 2 User MAT User boot MAT Status-read mode 2 Common to both MATs Mode write write write write write write write Number Command Memory-read mode of Cycles 1+n 1 Cycle Address X X X X X X X Data H'00 H'05 H'40 H'45 H'20 H'25 H'71 write write write Mode read st 2 Cycle Address RA Data Dout nd WA Din X H'20 H'25 X H'71 Notes: 1. In auto-program mode, 129 cycles are required in command writing because of the simultaneous 128-byte write. 2. In memory read mode, the number of cycles varies with the number of address writing cycles (n). 18.9.3 Memory-Read Mode (1) On completion of an automatic program, automatic erase, or status read, the LSI enters a command waiting state. So, to read the contents of memory after these operations, issue the command to change the mode to the memory-read mode before reading from the memory. (2) In memory-read mode, the writing of commands is possible in the same way as in the command-write state. (3) After entering memory-read mode, continuous reading is possible. (4) After power has first been supplied, the LSI enters the memory-read mode. For the AC characteristics in memory read mode, see section 18.10.2, AC Characteristics and Timing in Writer Mode. Rev. 2.0, 06/04, page 642 of 980 18.9.4 Auto-Program Mode (1) In auto-program mode, programming is in 128-byte units. That is, 128 bytes of data are transferred in succession. (2) Even in the programming of less than 128 bytes, 128 bytes of data must be transferred. H'FF should be written to those addresses that are unnecessarily written to. (3) Set the low seven bits of the address to be transferred to low level. Inputting an invalid address will result in a programming error, although processing will proceed to the memoryprogramming operation. (4) The memory address is transferred in the 2 cycle. Do not transfer addresses in the 3 or later cycles. (5) Do not issue commands while programming is in progress. (6) When programming, execute automatic programming once for each 128-byte block of addresses. Programming the block at an address where programming has already been performed is not possible. (7) To confirm the end of automatic programming, check the signal on the I/O6 pin. Confirmation in the status-read mode is also possible (status polling of the I/O7 pin is used to check the end status of automatic programming). (8) Status-polling information on the I/O6 and I/O7 pins is retained until the next command is written. As long as no command is written, the information is made readable by setting CE and OE for enabling. For the AC characteristics in auto-program mode, see section 18.10.2, AC Characteristics and Timing in Writer Mode. 18.9.5 Auto-Erase Mode nd rd (1) Auto-erase mode only supports erasing of the entire memory. (2) Do not perform command writing during auto erasing is in progress. (3) To confirm the end of automatic erasing, check the signal on the I/O6 pin. Confirmation in the status-read mode is also possible (status polling of the I/O7 pin is used to check the end status of automatic erasure). (4) Status polling information on the I/O6 and I/O7 pins is retained until the next command writing. As long as no command is written, the information is made readable by setting CE and OE for enabling. For the AC characteristics in auto-erase mode, see section 18.10.2, AC Characteristics and Timing in Writer Mode. Rev. 2.0, 06/04, page 643 of 980 18.9.6 Status-Read Mode (1) Status-read mode is used to determine the type of an abnormal termination. Use this mode when automatic programming or automatic erasure ends abnormally. (2) The return code is retained until writing of a command that selects a mode other than statusread mode. Table 18.14 lists the return codes of status-read mode. For the AC characteristics in status-read mode, see section 18.10.2, AC Characteristics and Timing in Writer Mode. Table 18.14 Return Codes of Status-Read Mode Pin Name I/O7 Attribute I/O6 I/O5 Programming error I/O4 I/O3 I/O2 -- I/O1 I/O0 Normal end Command indicator error Erase error -- Programming Invalid address or erase error count exceeded 0 0 Initial value 0 Indication Normal end: 0 Abnormal end: 1 0 0 0 0 0 -- -- Erase Command Programming error: 1 error:1 error: 1 Otherwise: 0 Otherwise: 0 Otherwise: 0 Invalid Count exceeded: 1 address Otherwise: 0 error: 1 Otherwise: 0 Note: I/O2 and I/O3 are undefined pins. 18.9.7 Status Polling (1) The I/O7 status-polling output is a flag that indicates the operating status in auto-program or auto-erase mode. (2) The I/O6 status-polling output is a flag that indicates normal/abnormal end of auto-program or auto-erase mode. Table 18.15 Truth Table of Status-Polling Output Pin Name I/O7 I/O6 I/O0 to 5 In Progress 0 0 0 Abnormal End 1 0 0 -- 0 1 0 Normal End 1 1 0 Rev. 2.0, 06/04, page 644 of 980 18.9.8 Time Taken in Transition to PROM Mode Until oscillation has stabilized and while PROM mode is being set up, the LSI is unable to accept commands. After the PROM-mode setup time has elapsed, the LSI enters memory-read mode. See section 18.10.2, AC Characteristics and Timing in Writer Mode. 18.9.9 Notes on Using PROM Mode (1) When programming addresses which have previously been programmed, apply auto-erasing before auto-programming (figure 18.24). (2) When using PROM mode to program a chip that has been programmed/erased in an on-board programming mode, auto-erasing before auto-programming is recommended. (3) Do not take the chip out of the PROM programmer or reset the chip during programming or erasure. Flash memory is susceptible to permanent damage since a high voltage is being applied during the programming/erasing. When the reset signal is accidentally input to the chip, the period in the reset state until the reset signal is released should be longer than the normal 100 s. (4) The flash memory is initially in the erased state when the device is shipped by Renesas Technology. For other chips for which the history of erasure is unknown, auto-erasing as a check and supplement for the initialization (erase) level is recommended. (5) This LSI does not support modes such as the product identification mode of general purpose EPROM. Therefore, the device name is not automatically set in the PROM programmer. (6) For further information on the PROM programmer and its software version, please refer to the instruction manual for the socket adapter. Rev. 2.0, 06/04, page 645 of 980 18.10 Further Information 18.10.1 Serial Communication Interface Specification for Boot Mode Initiating boot mode enables the boot program to communicate with the host by using the internal SCI. The serial communication interface specification is shown below. * Status The boot program has three states. (1) Bit-Rate-Adjustment State In this state, the boot program adjusts the bit rate to communicate with the host. Initiating boot mode enables starting of the boot program and entry to the bit-rate-adjustment state. The program receives the command from the host to adjust the bit rate. After adjusting the bit rate, the program enters the inquiry/selection state. (2) Inquiry/Selection State In this state, the boot program responds to inquiry commands from the host. The device name, clock mode, and bit rate are selected. After selection of these settings, the program is made to enter the programming/erasing state by the command for a transition to the programming/erasing state. The program transfers the libraries required for erasure to the RAM and erases the user MATs and user boot MATs before the transition. (3) Programming/erasing state Programming and erasure by the boot program take place in this state. The boot program is made to transfer the programming/erasing programs to the RAM by commands from the host. Sum checks and blank checks are executed by sending these commands from the host. These boot program states are shown in figure 18.23. Rev. 2.0, 06/04, page 646 of 980 Reset Bit-Rate-Adjustment State Inquiry/Selection wait Transition to Programming/erasing Inquiry Selection Operations for Inquiry Operations for Selection Operations for Erasing User MATs and User Boot MATs Programming/erasing selection wait Programming Operations for Programming Erasing Operations for Erasing Checking Operations for Checking Figure 18.23 Boot Program States * Bit-Rate-Adjustment state The bit rate is calculated by measuring the period of transfer of a low-level byte (H'00) from the host. The bit rate can be changed by the command for a new bit rate selection. After the bit rate has been adjusted, the boot program enters the inquiry and selection state. The bit-rate-adjustment sequence is shown in figure 18.24. Rev. 2.0, 06/04, page 647 of 980 Host H'00 (30 times maximum) Boot Program Measuring the 1-Bit Length H'00 (Completion of Adjustment) H'55 H'E6 (Response to Boot) H'FF (Error) Figure 18.24 Bit-Rate-Adjustment Sequence * Communications Protocol After adjustment of the bit rate, the protocol for communications between the host and the boot program is as shown below. (1) One-byte commands and one-byte responses These commands and responses are comprised of a single byte. These are consists of the inquiries and the ACK for successful completion. (2) n-byte commands or n-byte responses These commands and responses are comprised of n bytes of data. These are selections and responses to inquiries. The amount of programming data is not included under this heading because it is determined in another command. (3) Error response The error response is a response to inquiries. It consists of an error response and an error code and comes two bytes. (4) Programming of 128 bytes The size is not specified in commands. The size of n is indicated in response to the programming unit inquiry. (5) Memory read response This response consists of four bytes of data. Rev. 2.0, 06/04, page 648 of 980 One-Byte Command or One-Byte Response n-Byte Command or n-Byte Response Command or Response Data Size Command or Response Checksum Error Response Error Code Error Response 128-Byte Programming Address Command Data (n bytes) Checksum Memory Read Response Size Response Data Checksum Figure 18.25 Communication Protocol Format Command (1 byte) : Commands including inquiries, selection, programming, erasing, and checking Response (1 byte) : Response to an inquiry Size (1 byte) : The amount of data for transmission excluding the command, amount of data, and checksum Checksum (1 byte) : The checksum is calculated so that the total of all values from the command byte to the SUM byte becomes H'00. Data (n bytes) : Detailed data of a command or response Error Response (1 byte) : Error response to a command Error Code (1 byte) : Type of the error Address (4 bytes) : Address for programming Data (n bytes) : Data to be programmed (the size is indicated in the response to the programming unit inquiry.) Size (4 bytes) : Four-byte response to a memory read Rev. 2.0, 06/04, page 649 of 980 * Inquiry and Selection States The boot program returns information from the flash memory in response to the host's inquiry commands and sets the device code, clock mode, and bit rate in response to the host's selection command. Inquiry and selection commands are listed below. Table 18.16 Inquiry and Selection Commands Command H'20 H'10 H'21 H'11 H'22 Command Name Supported Device Inquiry Device Selection Clock Mode Inquiry Clock Mode Selection Multiplication Ratio Inquiry Description Inquiry regarding device codes and product names of F-ZTAT Selection of device code Inquiry regarding numbers of clock modes and values of each mode Indication of the selected clock mode Inquiry regarding the number of frequency-multiplied clock types, the number of multiplication ratios, and the values of each multiple Inquiry regarding the maximum and minimum values of the main clock and peripheral clocks Inquiry regarding the number of user boot MATs and the start and last addresses of each MAT Inquiry regarding the a number of user MATs and the start and last addresses of each MAT Inquiry regarding the number of blocks and the start and last addresses of each block Inquiry regarding the unit of programming data Selection of new bit rate Erasing of user MAT and user boot MAT, and entry to programming/erasing state Inquiry into the operated status of the boot program H'23 Operating Clock Frequency Inquiry H'24 User Boot MAT Information Inquiry H'25 User MAT Information Inquiry H'26 Block for Erasing Information Inquiry H'27 H'3F H'40 Programming Unit Inquiry New Bit Rate Selection Transition to Programming/erasing State Boot Program Status Inquiry H'4F The selection commands, which are device selection (H'10), clock mode selection (H'11), and new bit rate selection (H'3F), should be sent from the host in that order. These commands will Rev. 2.0, 06/04, page 650 of 980 certainly be needed. When two or more selection commands are sent at once, the last command will be valid. All of these commands, except for the boot program status inquiry command (H'4F), will be valid until the boot program receives the programming/erasing transition (H'40). The host can choose the needed commands out of the commands and inquiries listed above. The boot program status inquiry command (H'4F) is valid after the boot program has received the programming/erasing transition command (H'40). (1) Supported device inquiry The boot program will return the device codes of supported devices and the product code of the F-ZTAT in response to the supported device inquiry. Command H'20 Command, H'20, (1 byte) : Inquiry regarding supported devices Response H'30 A number of characters Size Device code A number of devices Product name *** SUM Response, H'30, (1 byte) : Response to the supported device inquiry Size (1 byte) : Number of bytes to be transmitted, excluding the command, amount of data, and checksum, that is, the amount of data contributes by the product names, the number of devices, characters, and device codes A number of devices (1 byte) : The number of device types supported by the boot program A number of characters (1 byte) : The number of characters in the device codes and boot program's name Device code (4 bytes) : Code of the supporting product Product name (n bytes) : Type name of the boot program in ASCII-coded characters SUM (1 byte) : Checksum The checksum is calculated so that the total number of all values from the command byte to the SUM byte becomes H'00. (2) Device Selection The boot program will set the supported device to the specified device code. The program will return the selected device code in response to the inquiry after this setting has been made. Command H'10 Size Device code SUM Rev. 2.0, 06/04, page 651 of 980 Command, H'10, (1 byte) : Device selection Size (1 byte) : Amount of device-code data This is fixed to 4 Device code (4 bytes) : Device code returned in response to the supported device inquiry (ASCII-code) SUM (1 byte) : Checksum Response H'06 Response, H'06, (1 byte) : Response to the device selection command ACK will be returned when the device code matches. Error response H'90 ERROR Error response, H'90, (1 byte) : Error response to the device selection command Error : (1 byte) : Error code H'11 : Sum check error H'21 : Device code error, that is, the device code does not match (3) Clock Mode Inquiry The boot program will return the supported clock modes in response to the clock mode inquiry. Command H'21 Command, H'21, (1 byte) : Inquiry regarding clock mode Response H'31 Size A number of Mode modes SUM Response, H'31, (1 byte) : Response to the clock-mode inquiry Size (1 byte) : Amount of data that represents the number of modes and modes A number of clock modes (1 byte) : The number of supported clock modes H'00 indicates no clock mode or the device allows to read the clock mode. Mode (1 byte) : Values of the supported clock modes (i.e. H'01 means clock mode 1.) SUM (1 byte) : Checksum (4) Clock Mode Selection The boot program will set the specified clock mode. The program will return the selected clockmode information after this setting has been made. The clock-mode selection command should be sent after the device-selection commands. Command H'11 Size Mode SUM Command, H'11, (1 byte) : Selection of clock mode Size (1 byte) : Amount of data that represents the modes Rev. 2.0, 06/04, page 652 of 980 Mode (1 byte) : A clock mode returned in reply to the supported clock mode inquiry. SUM (1 byte) : Checksum Response H'06 Response, H'06, (1 byte) : Response to the clock mode selection command ACK will be returned when the clock mode matches. Error response H'91 ERROR Error response, H'91, (1 byte) : Error response to the clock mode selection command ERROR, (1 byte) : Error code H'11 : Checksum error H'22 : Clock mode error, that is, the clock mode does not match. Even when the clock mode value is H'00 or H'01 for clock mode inquiry, clock mode selection is performed for each value. (5) Multiplication Ratio-Inquiry The boot program will return the supported multiplication and division ratios. Command H'22 Command, H'22, (1 byte) : Inquiry regarding multiplication ratio Response H'32 Size The Number of Clock *** The number of multiplication ratios Multiplication ratio *** SUM Response, H'32, (1 byte) : Response to the multiplication ratio inquiry Size (1 byte) : The amount of data that represents the clock sources, the number of multiplication ratios, and the multiplication ratios A number of types (1 byte) : The number of supported multiplied clock types (e.g. when there are two multiplied clock types, which are the main and peripheral clocks, the number of types will be H'02.) Rev. 2.0, 06/04, page 653 of 980 A number of multiplication ratios (1 byte) : The number of multiplication ratios for each type (e.g. the number of multiplication ratios to which the main clock can be set and the peripheral clock can be set.) Multiplication ratio (1 byte) Multiplication ratio : The value of the multiplication ratio (e.g. when the clockfrequency multiplier is four, the value of multiplication ratio will be H'04.) Division ratio : The inverse of the division ratio, i.e. a negative number (e.g. when the clock is divided by two, the value of division ratio will be H'FE. H'FE = D'-2) The number of multiplication ratios returned is the same as the number of multiplication ratios and as many groups of data are returned as there are types. SUM (1 byte) : Checksum (6) Operating Clock Frequency Inquiry The boot program will return the number of operating clock frequencies, and the maximum and minimum values. Command H'23 Command, H'23, (1 byte) : Inquiry regarding operating clock frequencies Response H'33 Size A number of operating clock frequencies The minimum value of operating clock frequency *** SUM The maximum value of operating clock frequency Response, H'33, (1 byte) : Response to operating clock frequency inquiry Size (1 byte) : The number of bytes that represents the minimum values, maximum values, and the number of types. A number of types (1 byte) : The number of supported operating clock frequency types (e.g. when there are two operating clock frequency types, which are the main and peripheral clocks, the number of types will be H'02.) Minimum value of operating clock frequency (2 bytes) : The minimum value of the multiplied or divided clock frequency. The minimum and maximum values represent the values in MHz, valid to the hundredths place of MHz, and multiplied by 100. (e.g. when the value is 20.00 MHz, it will be D'2000 and H'07D0.) Maximum value (2 bytes) : Maximum value among the multiplied or divided clock frequencies. Rev. 2.0, 06/04, page 654 of 980 There are as many pairs of minimum and maximum values as there are operating clock frequencies. SUM (1 byte) : Checksum (7) User Boot MAT Information Inquiry The boot program will return the number of user boot MATs and their addresses. Command H'24 Command, H'24, (1 byte) : Inquiry regarding user boot MAT information Response H'34 Size A Number of Areas Area-Start Address *** SUM Area-Last Address Response, H'34, (1 byte) : Response to user boot MAT information inquiry Size (1 byte) : The number of bytes that represents the number of areas, area-start addresses, and area-last address A Number of Areas (1 byte) : The number of non-consecutive user boot MAT areas When user boot MAT areas are consecutive, the number of areas returned is H'01. Area-Start Address (4 bytes) : Start address of the area Area-Last Address (4 bytes) : Last address of the area There are as many groups of data representing the start and last addresses as there are areas. SUM (1 byte) : Checksum (8) User MAT Information Inquiry The boot program will return the number of user MATs and their addresses. Command H'25 Command, H'25, (1 byte) : Inquiry regarding user MAT information Rev. 2.0, 06/04, page 655 of 980 Response H'35 Size A Number of Areas Area-Start Address *** SUM Area-Last Address Response, H'35, (1 byte) : Response to the user MAT information inquiry Size (1 byte) : The number of bytes that represents the number of areas, area-start address and area-last address A Number of Areas (1 byte) : The number of non-consecutive user MAT areas When the user MAT areas are consecutive, the number of areas is H'01. Area-Start Address (4 bytes) : Start address of the area Area-Last Address (4 bytes) : Last address of the area There are as many groups of data representing the start and last addresses as there are areas. SUM (1 byte) : Checksum (9) Erased Block Information Inquiry The boot program will return the number of erased blocks and their addresses. Command H'26 Command, H'26, (1 byte) : Inquiry regarding erased block information Response H'36 Size A number of blocks Block Last Address Block Start Address *** SUM Response, H'36, (1 byte) : Response to the number of erased blocks and addresses Size (1 byte) : The number of bytes that represents the number of blocks, block-start addresses, and block-last addresses. A number of blocks (1 byte) : Number of erased blocks in flash memory Block Start Address (4 bytes) : Start address of a block Block Last Address (4 bytes) : Last address of a block There are as many groups of data representing the start and last addresses as there are blocks. Rev. 2.0, 06/04, page 656 of 980 SUM : Checksum (10) Programming Unit Inquiry The boot program will return the programming unit used to program data. Command H'27 Command, H'27, (1 byte) : Inquiry regarding programming unit Response H'37 Size Programming unit SUM Response, H'37, (1 byte) : Response to programming unit inquiry Size (1 byte) : The number of bytes that indicate the programming unit, which is fixed to 2 Programming unit (2 bytes) : A unit for programming This is the unit for reception of programming. SUM (1 byte) : Checksum (11) New Bit-Rate Selection The boot program will set a new bit rate and return the new bit rate. This selection should be sent after sending the clock mode selection command. Command H'3F Size Bit rate Input frequency Number of Multiplication Multiplication multiplication ratio 1 ratio 2 ratios SUM Command, H'3F, (1 byte) : Selection of new bit rate Size (1 byte) : The number of bytes that represents the bit rate, input frequency, number of multiplication ratios, and multiplication ratio Bit rate (2 bytes) : New bit rate One hundredth of the value (e.g. when the value is 19200 bps, the bit rate is H'00C0, which is D'192.) Input frequency (2 bytes) : Frequency of the clock input to the boot program This is valid to the hundredths place and represents the value in MHz multiplied by 100. (e.g. when the value is 20.00 MHz, the input frequency is H'07D0 (= D'2000).) Number of multiplication ratios (1 byte) : The number of multiplication ratios to which the device can be set. Normally the value is two: main operating frequency and peripheral module operating frequency. (Should be set to H'01 for this LSI.) Multiplication ratio 1 (1 byte) : The value of multiplication or division ratios for the main operating frequency Rev. 2.0, 06/04, page 657 of 980 Multiplication ratio (1 byte) : The value of the multiplication ratio (e.g. when the clock frequency is multiplied by four, the multiplication ratio will be H'04. With this LSI it should be set to H'01.) Division ratio : The inverse of the division ratio, as a negative number (e.g. when the clock frequency is divided by two, the value of division ratio will be H'FE. H'FE = D'2. With this LSI it should be set to H'01.) Multiplication ratio 2 (1 byte) : The value of multiplication or division ratios for the peripheral frequency Multiplication ratio (1 byte) : The value of the multiplication ratio (e.g. when the clock frequency is multiplied by four, the multiplication ratio will be H'04. Cannot be set for this LSI.) Division ratio : The inverse of the division ratio, as a negative number (e.g. when the clock is divided by two, the value of division ratio will be H'FE. H'FE = D'-2. With this LSI it should be set to H'01.) SUM (1 byte) : Checksum Response H'06 Response, H'06, (1 byte) : Response to selection of a new bit rate When it is possible to set the bit rate, the response will be ACK. Error response H'BF ERROR Error response, H'BF, (1 byte) : Error response to selection of new bit rate ERROR : (1 byte) : Error code H'11 H'24 H'25 H'26 H'27 : Sum checking error : Bit-rate selection error The rate is not available. : Error in input frequency This input frequency is not within the specified range. : Multiplication-ratio error* The ratio does not match an available ratio. : Operating frequency error* The frequency is not within the specified range. Note: * This error does not occur with this LSI. Rev. 2.0, 06/04, page 658 of 980 * Received data check The methods for checking of received data are listed below. (1) Input frequency The received value of the input frequency is checked to ensure that it is within the range of minimum to maximum frequencies which matches the clock modes of the specified device. When the value is out of this range, an input-frequency error is generated. (2) Multiplication ratio The received value of the multiplication ratio or division ratio is checked to ensure that it matches the clock modes of the specified device. When the value is out of this range, an input-frequency error is generated. (3) Operating frequency error Operating frequency is calculated from the received value of the input frequency and the multiplication or division ratio. The input frequency is input to the LSI and the LSI is operated at the operating frequency. The expression is given below. Operating frequency = Input frequency x Multiplication ratio , or Operating frequency = Input frequency / Division ratio The calculated operating frequency should be checked to ensure that it is within the range of minimum to maximum frequencies which are available with the clock modes of the specified device. When it is out of this range, an operating frequency error is generated. (4) Bit rate Peripheral operating clock (), bit rate (B), clock select (CKS) in the serial mode register (SMR). The error as calculated by the method below is checked to ensure that it is less than 4%. When it is 4% or more, a bit-rate selection error is generated. Error (%) = {[ x 106 ] -1} x100 (N+1) x B x 64 x 2(2xn-1) When the new bit rate is selectable, the rate will be set in the register after sending ACK in response. The host will send an ACK with the new bit rate for confirmation and the boot program will response with that rate. Confirmation H'06 Confirmation, H'06, (1 byte) : Confirmation of a new bit rate Response H'06 Response, H'06, (1 byte) : Response to confirmation of a new bit rate The sequence of new bit-rate selection is shown in figure 18.26. Rev. 2.0, 06/04, page 659 of 980 Host Setting a new bit rate Waiting for one-bit period at the specified bit rate Setting a new bit rate H'06 (ACK) with the new bit rate H'06 (ACK) with the new bit rate H'06 (ACK) Boot program Setting a new bit rate Figure 18.26 New Bit-Rate Selection Sequence * Transition to Programming/Erasing State The boot program will transfer the erasing program, and erase the user MATs and user boot MATs in that order. On completion of this erasure, ACK will be returned and will enter the programming/erasing state. The host should select the device code, clock mode, and new bit rate with device selection, clockmode selection, and new bit-rate selection commands, and then send the command for the transition to programming/erasing state. These procedure should be carried out before sending of the programming selection command or program data. Command H'40 Command, H'40, (1 byte) : Transition to programming/erasing state Response H'06 Response, H'06, (1 byte) : Response to transition to programming/erasing state The boot program will send ACK when the user MAT and user boot MAT have been erased by the transferred erasing program. Error response H'C0 H'51 Error response, H'C0, (1 byte) : Error response for user boot MAT blank check Error code, H'51, (1 byte) : Erasing error An error occurred and erasure was not completed. Rev. 2.0, 06/04, page 660 of 980 * Command Error A command error will occur when a command is undefined, the order of commands is incorrect, or a command is unacceptable. Issuing a clock-mode selection command before a device selection or an inquiry command after the transition to programming/erasing state command, are examples. Error response H'80 H'xx Error response, H'80, (1 byte) : Command error Command, H'xx, (1 byte) : Received command * Command Order The order for commands in the inquiry selection state is shown below. (1) A supported device inquiry (H'20) should be made to inquire about the supported devices. (2) The device should be selected from among those described by the returned information and set with a device-selection (H'10) command. (3) A clock-mode inquiry (H'21) should be made to inquire about the supported clock modes. (4) The clock mode should be selected from among those described by the returned information and set. (5) After selection of the device and clock mode, inquiries for other required information should be made, such as the multiplication-ratio inquiry (H'22) or operating frequency inquiry (H'23). (6) A new bit rate should be selected with the new bit-rate selection (H'3F) command, according to the returned information on multiplication ratios and operating frequencies. (7) After selection of the device and clock mode, the information of the user boot MAT and user MAT should be made to inquire about the user boot MATs information inquiry (H'24), user MATs information inquiry (H'25), erased block information inquiry (H'26), programming unit inquiry (H'27). (8) After making inquiries and selecting a new bit rate, issue the transition to programming/erasing state (H'40) command. The boot program will then enter the programming/erasing state. * Programming/erasing State A programming selection command makes the boot program select the programming method, an 128-byte programming command makes it program the memory with data, and an erasing selection command and block erasing command make it erase the block. The programming/erasing commands are listed below. Rev. 2.0, 06/04, page 661 of 980 Table 18.17 Programming/erasing Command Command H'42 H'43 H'50 H'48 H'58 H'52 H'4A H'4B H'4C H'4D H'4F Command Name User boot MAT programming selection User MAT programming selection 128-byte programming Erasing selection Block erasing Memory read User boot MAT sum check User MAT sum check User boot MAT blank check User MAT blank check Boot program status inquiry Description Transfers the user boot MAT programming program Transfers the user MAT programming program Programs 128 bytes of data Transfers the erasing program Erases a block of data Reads the contents of memory Checks the checksum of the user boot MAT Checks the checksum of the user MAT Checks whether the contents of the user boot MAT are blank Checks whether the contents of the user MAT are blank Inquires into the boot program's status * Programming Programming is executed by a programming-selection command and an 128-byte programming command. Firstly, the host should send the programming-selection command and select the programming method and programming MATs. There are two programming selection commands, and selection is according to the area and method for programming. (1) User boot MAT programming selection (2) User MAT programming selection After issuing the programming selection command, the host should send the 128-byte programming command. The 128-byte programming command that follows the selection command represents the data programmed according to the method specified by the selection command. When more than 128-byte data is programmed, 128-byte commands should repeatedly be executed. Sending an 128-byte programming command with H'FFFFFFFF as the address will stop the programming. On completion of programming, the boot program will wait for selection of programming or erasing. Where the sequence of programming operations that is executed includes programming with another method or of another MAT, the procedure must be repeated from the programming selection command. Rev. 2.0, 06/04, page 662 of 980 The sequence for programming-selection and 128-byte programming commands is shown in figure 18.27. Host Programming selection (H'42, H'43) Boot program Transfer of the programming program ACK 128-byte programming (address, data) Repeat ACK 128-byte programming (H'FFFFFFFF) ACK Programming Figure 18.27 Programming Sequence (1) User boot MAT programming selection The boot program will transfer a programming program. The data is programmed to the user boot MATs by the transferred programming program. Command H'42 Command, H'42, (1 byte) : User boot-program programming selection Response H'06 Response, H'06, (1 byte) : Response to user boot-program programming selection When the programming program has been transferred, the boot program will return ACK. Error response H'C2 ERROR Error response : H'C2 (1 byte): Error response to user boot MAT programming selection ERROR : (1 byte): Error code H'54 : Selection processing error (transfer error occurs and processing is not completed) (2) User MAT programming selection. The boot program will transfer a programming program. The data is programmed to the user MATs by the transferred programming program. Rev. 2.0, 06/04, page 663 of 980 Command H'43 Command, H'43, (1 byte) : User-program programming selection Response H'06 Response, H'06, (1 byte) : Response to user-program programming selection When the programming program has been transferred, the boot program will return ACK. Error response H'C3 ERROR Error response: H'C3 (1 byte): Error response to user MAT programming selection ERROR: (1 byte): Error code H'54: Selection processing error (transfer error occurs and processing is not completed) (3) 128-byte programming The boot program will use the programming program transferred by the programming selection to program the user boot MATs or user MATs. Command H'50 Data *** SUM Address *** Command, H'50, (1 byte) : 128-byte programming Programming Address (4 bytes) : Start address for programming Multiple of the size specified in response to the programming unit inquiry (i.e. H'00, H'01, H'00, H'00 : H'00010000) Programming Data (128 bytes) : Data to be programmed The size is specified in the response to the programming unit inquiry. SUM (1 byte) : Checksum Response H'06 Response, H'06, (1 byte) : Response to 128-byte programming On completion of programming, the boot program will return ACK. Error response H'D0 ERROR Error response, H'D0, (1 byte) : Error response for 128-byte programming ERROR : (1 byte) : Error code H'11 : Checksum Error H'28 : Address error The address is not within the specified range. Rev. 2.0, 06/04, page 664 of 980 H'53 : Programming error A programming error has occurred and programming cannot be continued. The specified address should match the unit for programming of data. For example, when the programming is in 128-byte units, the lower byte of the address should be H'00 or H'80. When there are less than 128 bytes of data to be programmed, the host should fill the rest with H'FF. Sending the 128-byte programming command with the address of H'FFFFFFFF will stop the programming operation. The boot program will interpret this as the end of the programming and wait for selection of programming or erasing. Command H'50 Address SUM Command, H'50, (1 byte) : 128-byte programming Programming Address (4 bytes) : End code is H'FF, H'FF, H'FF, H'FF. SUM (1 byte) : Checksum Response H'06 Response: H'06 (1 byte): Response to 128-byte programming On completion of programming, the boot program will return ACK. Error response H'D0 ERROR Error Response, H'D0, (1 byte) : Error response for 128-byte programming ERROR : (1 byte) : Error code H'11 : Checksum error H'53 : Programming error An error has occurred in programming and programming cannot be continued. * Erasure Erasure is performed with the erasure selection and block erasure command. Firstly, erasure is selected by the erasure selection command and the boot program then erases the specified block. The command should be repeatedly executed if two or more blocks are to be erased. Sending a block-erasure command from the host with the block number H'FF will stop the erasure operating. On completion of erasing, the boot program will wait for selection of programming or erasing. The sequences of the issuing of erasure selection commands and the erasure of data are shown in figure 18.28. Rev. 2.0, 06/04, page 665 of 980 Host Preparation for Erasure (H'48) Boot Program Transfer of Erasure Program ACK Erasure (Erased Block Number) ACK Erasure (H'FF) ACK Repeat Erasure Figure 18.28 Erasure Sequence (1) Erasure Selection The boot program will transfer the erasure program. User MAT data is erased by the transferred erasure program. Command H'48 Command, H'48, (1 byte) : Erasure selection Response H'06 Response, H'06, (1 byte) : Response for erasure selection After the erasure program has been transferred, the boot program will return ACK. Error response H'C8 ERROR Error response: H'C8 (1 byte): Error response to erasing selection ERROR: (1 byte): Error code H'54: Selection processing error (transfer error occurs and processing is not completed) (2) Block Erasure The boot program will erase the contents of the specified block. Command H'58 Size Block Number SUM Command, H'58, (1 byte) : Erasure Size (1 byte) : The number of bytes that represents the erasure block number This is fixed to 1. Rev. 2.0, 06/04, page 666 of 980 Block Number (1 byte) : Number of the block to be erased SUM (1 byte) : Checksum Response H'06 Response, H'06, (1 byte) : Response to Erasure After erasure has been completed, the boot program will return ACK. Error response H'D8 ERROR Error Response, H'D8, (1 byte) : Error code ERROR (1 byte) : Error code H'11 : Sum check error H'29 : Block number error Block number is incorrect. H'51 : Erasure error An error has occurred during erasure. On receiving block number H'FF, the boot program will stop erasure and wait for a selection command. Command H'58 Size Block Number SUM Command, H'58, (1 byte) : Erasure Size (1 byte) : The number of bytes that represents the block number This is fixed to 1. Block Number (1 byte) : H'FF Stop code for erasure SUM (1 byte) : Checksum Response H'06 Response, H'06, (1 byte) : Response to end of erasure (ACK) When erasure is to be performed after the block number H'FF has been sent, the procedure should be executed from the erasure selection command. * Memory read The boot program will return the data in the specified address. Command H'52 Read size Size Area Read address SUM Command: H'52 (1 byte): Memory read Size (1 byte): Amount of data that represents the area, read address, and read size (fixed at 9) Rev. 2.0, 06/04, page 667 of 980 Area (1 byte) H'00 : User boot MAT H'01 : User MAT An address error occurs when the area setting is incorrect. Read address (4 bytes): Start address to be read from Read size (4 bytes): Size of data to be read SUM (1 byte): Checksum Response H'52 Data SUM Read size *** Response: H'52 (1 byte): Response to memory read Read size (4 bytes): Size of data to be read Data (n bytes): Data for the read size from the read address SUM (1 byte): Checksum Error response H'D2 ERROR Error response: H'D2 (1 byte): Error response to memory read ERROR: (1 byte): Error code H'11: Sum check error H'2A: Address error The read address is not in the MAT. H'2B: Size error The read size exceeds the MAT. * User-Boot Program Sum check The boot program will return the byte-by-byte total of the contents of the bytes of the user-boot program. Command H'4A Command, H'4A, (1 byte) : Sum check for user-boot program Response H'5A Size Checksum of user boot program SUM Response, H'5A, (1 byte) : This is fixed to 4. Response to the sum check of user-boot program Size (1 byte) : The number of bytes that represents the checksum Checksum of user boot program (4 bytes) : Checksum of user boot MATs The total of the data is obtained in byte units. SUM (1 byte) : Sum check for data being transmitted Rev. 2.0, 06/04, page 668 of 980 * User-Program Sum check The boot program will return the byte-by-byte total of the contents of the bytes of the user program. Command H'4B Command, H'4B, (1 byte) : Sum check for user program Response H'5B Size Checksum of user program SUM Response, H'5B, (1 byte) : Response to the sum check of the user program Size (1 byte) : The number of bytes that represents the checksum This is fixed to 4. Checksum of user boot program (4 bytes) : Checksum of user MATs The total of the data is obtained in byte units. SUM (1 byte) : Sum check for data being transmitted * User Boot MAT Blank check The boot program will check whether or not all user boot MATs are blank and return the result. Command H'4C Command, H'4C, (1 byte) : Blank check for user boot MAT Response H'06 Response, H'06, (1 byte) : Response to the blank check of user boot MAT If all user MATs are blank (H'FF), the boot program will return ACK. Error response H'CC H'52 Error Response, H'CC, (1 byte) : Response to blank check for user boot MAT Error Code, H'52, (1 byte) * User MAT Blank Check The boot program will check whether or not all user MATs are blank and return the result. Command H'4D : Erasure has not been completed. Command, H'4D, (1 byte) : Blank check for user MATs Response H'06 Response, H'06, (1 byte) : Response to the blank check for user boot MATs If the contents of all user MATs are blank (H'FF), the boot program will return ACK. Rev. 2.0, 06/04, page 669 of 980 Error response H'CD H'52 Error Response, H'CD, (1 byte) : Error response to the blank check of user MATs. Error code H'52 (1 byte) : Erasure has not been completed. * Boot Program State Inquiry The boot program will return indications of its present state and error condition. This inquiry can be made in the inquiry/selection state or the programming/erasing state. Command H'4F Command, H'4F, (1 byte) : Inquiry regarding boot program's state Response H'5F Size STATUS ERROR SUM Response, H'5F, (1 byte) : Response to boot program state inquiry Size (1 byte) : The number of bytes that represents the STATUS and ERROR. This is fixed to 2. STATUS (1 byte) : State of the boot program For details, see table 18.18. ERROR (1 byte): Error state ERROR = 0 indicates normal operation. ERROR = 1 indicates error has occurred For details, see table 18.19. SUM (1 byte): Checksum Rev. 2.0, 06/04, page 670 of 980 Table 18.18 Status Code Code H'11 H'12 H'13 H'1F H'31 H'3F H'4F H'5F Description Device Selection Wait Clock Mode Selection Wait Bit Rate Selection Wait Programming/Erasing State Transition Wait (Bit rate selection is completed) Programming State for Erasure Programming/Erasing Selection Wait (Erasure is completed) Programming Data Receive Wait (Programming is completed) Erasure Block Specification Wait (Erasure is completed) Table 18.19 Error Code Code H'00 H'11 H'12 H'21 H'22 H'24 H'25 H'26 H'27 H'29 H'2A H'2B H'51 H'52 H'53 H'54 H'80 H'FF Description No Error Sum Check Error Program Size Error Device Code Mismatch Error Clock Mode Mismatch Error Bit Rate Selection Error Input Frequency Error Multiplication Ratio Error Operating Frequency Error Block Number Error Address Error Data Length Error Erasure Error Erasure Incompletion Error Programming Error Selection Error Command Error Bit-Rate-Adjustment Confirmation Error Rev. 2.0, 06/04, page 671 of 980 18.10.2 AC Characteristics and Timing in Writer Mode Table 18.20 AC Characteristics in Memory Read Mode Condition : VCC = 3.0 V to 3.6 V, VSS = 0 V, Ta = 25C 5C Code Command write cycle CE hold time CE setup time Data hold time Data setup time Programming pulse width WE rise time WE fall time Symbol tnxtc tceh tces tdh tds twep tr tf Min 20 0 0 50 50 70 30 30 Max Unit s ns ns ns ns ns ns ns Note Command write A18-0 tces tceh tnxtc Memory read mode Address stable CE OE tf twep tr WE tds I/O7-0 tdh Note : Data is latched at the rising edge of WE. Figure 18.29 Memory Read Timing after Command Write Rev. 2.0, 06/04, page 672 of 980 Table 18.21 AC Characteristics in Transition from Memory Read Mode to Others Condition : VCC = 3.0 V to 3.6 V, VSS = 0 V, Ta = 25C 5C Code Command write cycle CE hold time CE setup time Data hold time Data setup time Programming pulse width WE rise time WE fall time Symbol tnxtc tceh tces tdh tds twep tr tf Min 20 0 0 50 50 70 30 30 Max Unit s ns ns ns ns ns ns ns Note Memory Read Mode A18-0 Other Mode Command Write Address Stable tnxtc tces tceh CE OE tf twep tr WE tds I/O7-0 tdh Note : WE and OE should not be enabled simultaneously. Figure 18.30 Timing at Transition from Memory Read Mode to Other Modes Rev. 2.0, 06/04, page 673 of 980 Table 18.22 AC Characteristics Memory Read Mode Condition : VCC = 3.0 V to 3.6 V, VSS = 0 V, Ta = 25C 5C Code Access time CE output delay time OE output delay time Output disable delay time Data output hold time Symbol tacc tce toe tdf toh 5 Min Max 20 150 150 100 Unit s ns ns ns ns Note A18-0 Address Stable Address Stable CE OE WE I/O7-0 VIL VIL VIH tacc toh tacc toh CE/OE Figure 18.31 CE OE Enable State Read A18-0 Address Stable tce Address Stable tce CE OE WE I/O7-0 VIH tacc toe toe tacc toh tdf toh tdf CE/OE Figure 18.32 CE OE Clock Read Rev. 2.0, 06/04, page 674 of 980 Table 18.23 AC Characteristics Auto-Write Mode Condition : VCC = 3.0 V to 3.6 V, VSS = 0 V, Ta = 25C 5C Code Command write cycle CE hold time CE setup time Data hold time Data setup time Programming pulse width Status polling start time Status polling access time Address setup time Address hold time Memory programming time Programming setup time Programming end setup time WE rise time WE fall time Symbol tnxtc tceh tces tdh tds twep twsts tspa tas tah twrite tpns tpnh tr tf 0 60 1 100 100 30 30 3000 Min 20 0 0 50 50 70 1 150 Max Unit s ns ns ns ns ns ms ns ns ns ms ns ns ns ns Note FWE A18-0 tpnh Address Stable tpns tces tceh tnxtc tnxtc CE OE WE tf twep tr tas tah Data Transfer 1 byte to 128 bytes twsts tspa tds I/O7 tdh twrite Identification Signal of Programming Operation End I/O6 Identification Signal of Programming Operation Successful End H'40 or H'45 1st byte Din 128th byte Din H'00 I/O5-0 Figure 18.33 Timing in Auto-Write Mode Rev. 2.0, 06/04, page 675 of 980 Table 18.24 AC Characteristics Auto-Erase Mode Condition : VCC = 3.0 V to 3.6 V, VSS = 0 V, Ta = 25C 5C Code Command write cycle CE hold time CE setup time Data hold time Data setup time Programming pulse width Status polling start time Status polling access time Memory erase time Erase setup time Erase end setup time WE rise time WE fall time Symbol tnxtc tceh tces tdh tds twep tests tspa terase tens tenh tr tf 100 100 100 30 30 Min 20 0 0 50 50 70 1 150 40000 Max Unit s ns ns ns ns ns ms ns ms ns ns ns ns Note FWE A18-0 tenh tens tces tceh tnxtc tnxtc CE OE WE tf twep tr tests tspa tds I/O7 tdh terase Erase end identification signal Erase normal and confirmation signal H'00 I/O6 I/O5-0 H'20 or H'25 H'20 or H'25 Figure 18.34 Timing in Auto-Erase Mode Rev. 2.0, 06/04, page 676 of 980 Table 18.25 AC Characteristics Status Read Mode Condition : VCC = 3.0 V to 3.6 V, VSS = 0 V, Ta = 25C 5C Code Command write cycle CE hold time CE setup time Data hold time Data setup time Programming pulse width OE output delay time Disable delay time CE output delay time WE rise time WE fall time Symbol tnxtc tceh tces tdh tds twep toe tdf tce tr tf Min 20 0 0 50 50 70 150 100 150 30 30 Max Unit s ns ns ns ns ns ns ns ns ns ns Note A18-0 tces tceh tnxtc tces tceh tnxtc tnxtc tce CE OE WE tf twep twep tr tf tr toe tdf tds I/O7-0 H'71 tdh tds H'71 tdh Note: I/O3 and I/O2 are undefined. Figure 18.35 Timing in Status Read Mode Table 18.26 Stipulated Transition Times to Command Wait State Condition : VCC = 3.0 V to 3.6 V, VSS = 0 V, Ta = 25C 5C Code Standby release (oscillation settling time) PROM mode setup time VCC hold time Symbol tosc1 tbmv tdwn Min 30 10 0 Max Unit ms ms ms Note Rev. 2.0, 06/04, page 677 of 980 tosc1 VCC tbmv Memory read mode Command wait state Auto-program mode Auto-erase mode Command wait state Normal/abnormal end identification tdwn 4-5 FWE Note: Set the FWE input pin low level, except in the auto-program and auto-erase modes. Figure 18.36 Oscillation Stabilization Time, PROM Mode Setup Time, and Power-Down Sequence 18.10.3 Procedure Program and Storable Area for Programming Data In the descriptions in the previous section, the programming/erasing procedure programs and storable areas for program data are assumed to be in the on-chip RAM. However, the program and the data can be stored in and executed from other areas, such as part of flash memory which is not to be programmed or erased, or somewhere in the external address space. * Conditions that Apply to Programming/Erasing (1) The on-chip programming/erasing program is downloaded from the address set by FTDAR in on-chip RAM, therefore, this area is not available for use. (2) The on-chip programming/erasing program will use the 128 bytes as a stack. So, make sure that this area is secured. (3) Since download by setting the SCO bit to 1 will cause the MATs to be switched, it should be executed in on-chip RAM. (4) The flash memory is accessible until the start of programming or erasing, that is, until the result of downloading has been judged. When in a mode in which the external address space is not accessible, such as single-chip mode, the required procedure programs, NMI handling vector, NMI handler and user branch program should be transferred to the on-chip RAM before programming/erasing of the flash memory starts. (5) The flash memory is not accessible during programming/erasing operations, therefore, the operation program is downloaded to the on-chip RAM to be executed. The NMI-handling vector and programs such as that which activate the operation program, user program at the user-branch destination during programming/erasing operation, and NMI handler should thus be stored in on-chip memory other than flash memory or the external address space. (6) After programming/erasing, the flash memory should be inhibited until FKEY is cleared. The reset state (RES = 0) must be in place for more than 100 s when the LSI mode is changed to reset on completion of a programming/erasing operation. Rev. 2.0, 06/04, page 678 of 980 Transitions to the reset state, and hardware standby mode are inhibited during programming/erasing. When the reset signal is accidentally input to the chip, a longer period in the reset state than usual (100 s) is needed before the reset signal is released. (7) Switching of the MATs by FMATS should be needed when programming/erasing of the user boot MAT is operated in user-boot mode. The program which switches the MATs should be executed from the on-chip RAM. See section 18.8, Switching between User MAT and User Boot MAT. Please make sure you know which MAT is selected when switching between them. (8) When the data storable area indicated by programming parameter FMPDR is within the flash memory area, an error will occur even when the data stored is normal. Therefore, the data should be transferred to the on-chip RAM to place the address that FMPDR indicates in an area other than the flash memory. In consideration of these conditions, there are three factors; operating mode, the bank structure of the user MAT, and operations. The areas in which the programming data can be stored for execution are shown in table 18.27. Table 18.27 Executable MAT Initiated Mode Operation Programming Erasing Note: * User Program Mode Table 18.28 (1) Table 18.28 (2) Programming/Erasing is possible to user MATs. User Boot Mode* Table 18.28 (3) Table 18.28 (4) Rev. 2.0, 06/04, page 679 of 980 Table 18.28 (1) Useable Area for Programming in User Program Mode Storable /Executable Area On-chip User RAM MAT x* Selected MAT Embedded Program Storage Area -- Item Programming Storage Area for Procedure Program Data Operation for Selection of Onchip Program to be Downloaded Operation for Writing H'A5 to Key Register Execution of Writing SC0 = 1 to FCCS (Download) Operation for Key Register Clear Judgement of Download Result Operation for Download Error Operation for Settings of Initial Parameter Execution of Initialization Judgement of Initialization Result Operation for Initialization Error External Space User (Expanded Mode) MAT -- x x x x Rev. 2.0, 06/04, page 680 of 980 Storable /Executable Area On-chip User RAM MAT x Selected MAT Embedded Program Storage Area Item NMI Handling Routine Operation for Inhibit of Interrupt Operation for Writing H'5A to Key Register Operation for Settings of Program Parameter Execution of Programming Judgement of Program Result Operation for Program Error Operation for Key Register Clear Note: * External Space User (Expanded Mode) MAT x x x x x x Transferring the data to the on-chip RAM enables this area to be used. Rev. 2.0, 06/04, page 681 of 980 Table 18.28 (2) Useable Area for Erasure in User Program Mode Storable /Executable Area On-chip User RAM MAT Selected MAT Embedded Program Storage Area Item Erasing Procedure Operation for Selection of Onchip Program to be Downloaded Operation for Writing H'A5 to Key Register Execution of Writing SC0 = 1 to FCCS (Download) Operation for Key Register Clear Judgement of Download Result Operation for Download Error Operation for Settings of Default Parameter Execution of Initialization Judgement of Initialization Result Operation for Initialization Error NMI Handling Routine External Space User (Expanded Mode) MAT x x x x x Rev. 2.0, 06/04, page 682 of 980 Storable /Executable Area On-chip User RAM MAT Selected MAT Embedded Program Storage Area Item Operation for Inhibit of Interrupt Operation for Writing H'5A to Key Register Operation for Settings of Erasure Parameter Execution of Erasure Judgement of Erasure Result Operation for Erasure Error Operation for Key Register Clear External Space User (Expanded Mode) MAT x x x x x x Rev. 2.0, 06/04, page 683 of 980 Table 18.28 (3) Useable Area for Programming in User Boot Mode Storable/Executable Area User On-chip Boot RAM MAT x* 1 Selected MAT User Boot MAT -- Embedded Program Storage Area -- Item Programming Storage Area for procedure Program Data Operation for Selection of Onchip Program to be Downloaded Operation for Writing H'A5 to Key Register Execution of Writing SC0 = 1 to FCCS (Download) Operation for Key Register Clear Judgement of Download Result Operation for Download Error Operation for Settings of Default Parameter Execution of Initialization Judgement of Initialization Result Operation for Initialization Error NMI Handling Routine External Space (Expanded User Mode) MAT -- x x x x x Rev. 2.0, 06/04, page 684 of 980 Storable/Executable Area User On-chip Boot RAM MAT x x x x x x* x x x 2 Selected MAT User Boot MAT Embedded Program Storage Area Item Operation for Interrupt Inhibit Switching MATs by FMATS Operation for Writing H'5A to Key Register Operation for Settings of Program Parameter Execution of Programming Judgement of Program Result Operation for Program Error Operation for Key Register Clear Switching MATs by FMATS External Space (Expanded User Mode) MAT x x Notes: *1 Transferring the data to the on-chip RAM enables this area to be used. *2 Switching FMATS by a program in the on-chip RAM enables this area to be used. Rev. 2.0, 06/04, page 685 of 980 Table 18.28 (4) Useable Area for Erasure in User Boot Mode Storable/Executable Area User On-chip Boot RAM MAT Selected MAT User Boot MAT Embedded Program Storage Area Item Erasing Procedure Operation for Selection of Onchip Program to be Downloaded Operation for Writing H'A5 to Key Register Execution of Writing SC0 = 1 to FCCS (Download) Operation for Key Register Clear Judgement of Download Result Operation for Download Error Operation for Settings of Default Parameter Execution of Initialization Judgement of Initialization Result Operation for Initialization Error NMI Handling Routine External Space (Expanded User Mode) MAT x x x x x Rev. 2.0, 06/04, page 686 of 980 Storable/Executable Area User On-chip Boot RAM MAT x x x x x x* x x x x Selected MAT User Boot MAT Embedded Program Storage Area Item Operation for Interrupt Inhibit Switching MATs by FMATS Operation for Writing H'5A to Key Register Operation for Settings of Erasure Parameter Execution of Erasure Judgement of Erasure Result Operation for Erasure Error Operation for Key Register Clear Switching MATs by FMATS Note: * External Space (Expanded User Mode) MAT x Switching FMATS by a program in the on-chip RAM enables this area to be used. Rev. 2.0, 06/04, page 687 of 980 Rev. 2.0, 06/04, page 688 of 980 Section 19 Clock Pulse Generator 19.1 Overview The H8/3029 has a built-in clock pulse generator (CPG) that generates the system clock () and other internal clock signals (/2 to /4096). After duty adjustment, a frequency divider divides the 1 clock frequency to generate the system clock (). The system clock is output at the pin* and furnished as a master clock to prescalers that supply clock signals to the on-chip supporting modules. Frequency division ratios of 1/1, 1/2, 1/4, and 1/8 can be selected for the frequency 2 divider by settings in a division control register (DIVCR)* . Power consumption in the chip is reduced in almost direct proportion to the frequency division ratio. Notes: *1 Usage of the pin differs depending on the chip operating mode and the PSTOP bit setting in the module standby control register (MSTCR). For details, see section 20.7, System Clock Output Disabling Function. *2 The division ratio of the frequency divider can be changed dynamically during operation. The clock output at the pin also changes when the division ratio is changed. The frequency output at the pin is shown below. = EXTAL x n where, EXTAL: Frequency of crystal resonator or external clock signal n: 19.1.1 Block Diagram Frequency division ratio (n = 1/1, 1/2, 1/4, or 1/8) Figure 19.1 shows a block diagram of the clock pulse generator. CPG XTAL Oscillator EXTAL Duty adjustment circuit Frequency divider Prescalers Division control register Data bus pin /2 to /4096 Figure 19.1 Block Diagram of Clock Pulse Generator Rev. 2.0, 06/04, page 689 of 980 19.2 Oscillator Circuit Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock signal. 19.2.1 Connecting a Crystal Resonator Circuit Configuration: A crystal resonator can be connected as in the example in figure 19.2. Damping resistance Rd should be selected according to table 19.1 (1), and external capacitances CL1 and CL2 according to table 19.1 (2). An AT-cut parallel-resonance crystal should be used. CL1 EXTAL XTAL Rd CL2 Figure 19.2 Connection of Crystal Resonator (Example) If a crystal resonator with a frequency higher than 20 MHz is connected, the external load capacitance values in table 19.1 (2) should not exceed 10 pF. Also, in order to improve the accuracy of the oscillation frequency, a thorough study of oscillation matching evaluation, etc., should be carried out when deciding the circuit constants. Table 19.1 (1) Damping Resistance Value Frequency f (MHz) 13 < f 16 0 16 < f 18 0 18 < f 25 0 Damping Resistance Value 10 f 13 Rd () 0 Note: A crystal resonator between 10 MHz and 25 MHz can be used. If the chip is to be operated at less than 10 MHz, the on-chip frequency divider should be used. (A crystal resonator of less than 10 MHz cannot be used.) Table 19.1 (2) External Capacitance Values Frequency f (MHz) 20 < f 25 10 10 f 20 10 to 22 External Capacitance Value CL1 = CL2 (pF) Rev. 2.0, 06/04, page 690 of 980 Crystal Resonator: Figure 19.3 shows an equivalent circuit of the crystal resonator. The crystal resonator should have the characteristics listed in table 19.2. CL L XTAL Rs EXTAL C0 AT-cut parallel-resonance type Figure 19.3 Crystal Resonator Equivalent Circuit Table 19.2 Crystal Resonator Parameters Frequency (MHz) Rs max () Co (pF) 10 30 7 (max) 12 30 7 (max) 16 20 7 (max) 18 20 7 (max) 20 20 7 (max) 25 20 7 (max) Use a crystal resonator with a frequency equal to the system clock frequency (). Notes on Board Design: When a crystal resonator is connected, the following points should be noted: Other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation. See figure 19.4. When the board is designed, the crystal resonator and its load capacitors should be placed as close as possible to the XTAL and EXTAL pins. Avoid C L2 Signal A Signal B H8/3029 chip XTAL EXTAL C L1 Figure 19.4 Oscillator Circuit Block Board Design Precautions Rev. 2.0, 06/04, page 691 of 980 19.2.2 External Clock Input Circuit Configuration: An external clock signal can be input as shown in the examples in figure 19.5. If the XTAL pin is left open, the stray capacitance should not exceed 10 pF. If the stray capacitance at the XTAL pin exceeds 10 pF in configuration a, use the connection shown in configuration b instead, and hold the external clock high in standby mode. EXTAL External clock input XTAL Open (a) XTAL pin left open EXTAL External clock input XTAL (b) Complementary clock input at XTAL pin Figure 19.5 External Clock Input (Examples) External Clock: The external clock frequency should be equal to the system clock frequency when not divided by the on-chip frequency divider. Table 19.3 shows the clock timing, figure 19.6 shows the external clock input timing, and figure 19.7 shows the external clock output settling delay timing. When the appropriate external clock is input via the EXTAL pin, its waveform is corrected by the on-chip oscillator and duty adjustment circuit. When the appropriate external clock is input via the EXTAL pin, its waveform is corrected by the on-chip oscillator and duty adjustment circuit. The resulting stable clock is output to external devices after the external clock settling time (tDEXT) has passed after the clock input. The system must remain reset with the reset signal low during tDEXT, while the clock output is unstable. Rev. 2.0, 06/04, page 692 of 980 Table 19.3 Clock Timing VCC = 3.0 V to 3.6 V Item External clock input low pulse width External clock input high pulse width External clock rise time External clock fall time Clock low pulse width Clock high pulse width External clock output settling delay time Note: * Symbol Min tEXL tEXH tEXr tEXf tCL tCH tDEXT* 15 15 -- -- 0.4 0.4 500 Max -- -- 5 5 0.6 0.6 -- Unit ns ns ns ns tcyc tcyc s Figure 19.7 Figure 21.13 Test Conditions Figure 19.6 tDEXT includes a RES pulse width (tRESW). tRESW = 20 tcyc tEXH VCC x 0.7 EXTAL 0.3 V tEXr tEXf tEXL VCC x 0.5 Figure 19.6 External Clock Input Timing Rev. 2.0, 06/04, page 693 of 980 VCC 56*; EXTAL VIH (internal or external) 4-5 tDEXT Figure 19.7 External Clock Output Settling Delay Timing 19.3 Duty Adjustment Circuit The duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate . 19.4 Prescalers The prescalers divide the system clock () to generate internal clocks (/2 to /4096). 19.5 Frequency Divider The frequency divider divides the duty-adjusted clock signal to generate the system clock (). The frequency division ratio can be changed dynamically by modifying the value in DIVCR, as described below. Power consumption in the chip is reduced in almost direct proportion to the frequency division ratio. The system clock generated by the frequency divider can be output at the pin. Rev. 2.0, 06/04, page 694 of 980 19.5.1 Register Configuration Table 19.4 summarizes the frequency division register. Table 19.4 Frequency Division Register Address* H'EE01B Note: * Name Division control register Abbreviation DIVCR R/W R/W Initial Value H'FC Lower 20 bits of the address in advanced mode. 19.5.2 Division Control Register (DIVCR) DIVCR is an 8-bit readable/writable register that selects the division ratio of the frequency divider. Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 DIV1 0 R/W 0 DIV0 0 R/W Reserved bits Divide bits 1 and 0 These bits select the frequency division ratio DIVCR is initialized to H'FC by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 2--Reserved: These bits cannot be modified and are always read as 1. Bits 1 and 0--Divide (DIV1, DIV0): These bits select the frequency division ratio, as follows. Bit 1 DIV1 0 0 1 1 Bit 0 DIV0 0 1 0 1 Frequency Division Ratio 1/1 1/2 1/4 1/8 (Initial value) Rev. 2.0, 06/04, page 695 of 980 19.5.3 Usage Notes The DIVCR setting changes the frequency, so note the following points. * Select a frequency division ratio that stays within the assured operation range specified for the clock cycle time tcyc in the AC electrical characteristics. Note that min = lower limit of the operating frequency range. Ensure that is not below this lower limit. * All on-chip module operations are based on . Note that the timing of timer operations, serial communication, and other time-dependent processing differs before and after any change in the division ratio. The waiting time for exit from software standby mode also changes when the division ratio is changed. For details, see section 20.4.3, Selection of Waiting Time for Exit from Software Standby Mode. Rev. 2.0, 06/04, page 696 of 980 Section 20 Power-Down State 20.1 Overview The H8/3029 has a power-down state that greatly reduces power consumption by halting the CPU, and a module standby function that reduces power consumption by selectively halting on-chip modules. The power-down state includes the following three modes: * Sleep mode * Software standby mode * Hardware standby mode The module standby function can halt on-chip supporting modules independently of the powerdown state. The modules that can be halted are the 16-bit timer, 8-bit timer, SCI0, SCI1, SCI2, DMAC, DRAM interface, and A/D converter. Table 20.1 indicates the methods of entering and exiting the power-down modes and module standby mode, and gives the status of the CPU and on-chip supporting modules in each mode. Rev. 2.0, 06/04, page 697 of 980 State CPU Other SCI0 Active Active Active Active Active Held output Held SCI1 SCI2 A/D Modules RAM output *4 Ports Conditions * Interrupt * RES * STBY Registers DMAC Timer Active Active Active Active Interface Timer DRAM 8-Bit I/O Exiting 16-Bit clock Entering Mode Conditions Clock CPU Sleep SLEEP instruc- Active Halted Held mode tion executed while SSBY = 0 in SYSCR Halted Halted Halted and reset reset reset reset reset and and and and output Halted Halted Halted Halted and reset and reset held*1 reset and and Halted Held Halted High Held * NMI * IRQ0 to IRQ2 * RES * STBY Halted and reset Halted*2 and held*1 reset reset reset reset reset and and and and and and reset Halted*2 Halted*2 Halted*2 Halted*2 Halted*2 Halted*2 reset reset reset reset reset reset reset Active -- High impedance*2 -- * STBY * RES * Clear MSTCR bit to 0*5 and and and and and and and Halted Halted Halted Halted Halted Halted Halted Held*3 High impedance High * STBY impedance * RES Software SLEEP instruc- Halted Halted Held standby tion executed Rev. 2.0, 06/04, page 698 of 980 mined reset Halted*2 and reset and mode while SSBY = 1 in SYSCR Hardware Low input at Halted Halted Undeter- Halted standby STBY pin mode Module Corresponding Active Active -- standby bit set to 1 in MSTCR Notes: *1 RTCNT and bits 7 and 6 of RTMCSR are initialized. Other bits and registers hold their previous states. *2 State in which the corresponding MSTCR bit was set to 1. For details see section 20.2.2, Module Standby Control Register H (MSTCRH) and section 20.2.3, Table 20.1 Power-Down State and Module Standby Function Module Standby Control Register L (MSTCRL). *3 The RAME bit must be cleared to 0 in SYSCR before the transition from the program execution state to hardware standby mode. *4 When P67 is used as the output pin. *5 When a MSTCR bit is set to 1, the registers of the corresponding on-chip supporting module are initialized. To restart the module, first clear the MSTCR bit to 0, then set up the module registers again. Legend SYSCR: System control register SSBY: Software standby bit MSTCRH: Module standby control register H MSTCRL: Module standby control register L 20.2 Register Configuration The H8/3029 has a system control register (SYSCR) that controls the power-down state, and module standby control registers H (MSTCRH) and L (MSTCRL) that control the module standby function. Table 20.2 summarizes these registers. Table 20.2 Control Register Address* H'EE012 H'EE01C H'EE01D Note: * Name System control register Module standby control register H Module standby control register L Abbreviation SYSCR MSTCRH MSTCRL R/W R/W R/W R/W Initial Value H'09 H'78 H'00 Lower 20 bits of the address in advanced mode. 20.2.1 Bit System Control Register (SYSCR) 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 UE 1 R/W 2 NMIEG 0 R/W 1 SSOE 0 R/W 0 RAME 1 R/W RAM enable Software standby output port enable NMI edge select User bit enable Standby timer select 2 to 0 These bits select the waiting time of the CPU and peripheral functions Software standby Enables transition to software standby mode Initial value Read/Write SYSCR is an 8-bit readable/writable register. Bit 7 (SSBY), bits 6 to 4 (STS2 to STS0), and bit 1 (SSOE) control the power-down state. For information on the other SYSCR bits, see section 3.3, System Control Register (SYSCR). Rev. 2.0, 06/04, page 699 of 980 Bit 7--Software Standby (SSBY): Enables transition to software standby mode. When software standby mode is exited by an external interrupt, this bit remains set to 1 after the return to normal operation. To clear this bit, write 0. Bit 7 SSBY 0 1 Description SLEEP instruction causes transition to sleep mode SLEEP instruction causes transition to software standby mode (Initial value) Bits 6 to 4--Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU and on-chip supporting modules wait for the clock to settle when software standby mode is exited by an external interrupt. If the clock is generated by a crystal resonator, set these bits according to the clock frequency so that the waiting time will be at least 7 ms (oscillation settling time). See table 20.3. If an external clock is used, set these bits so that the waiting time will be at least 100 s. Bit 6 STS2 0 Bit 5 STS1 0 1 1 0 1 Bit 4 STS0 0 1 0 1 0 1 0 1 Description Waiting time = 8,192 states Waiting time = 16,384 states Waiting time = 32,768 states Waiting time = 65,536 states Waiting time = 131,072 states Waiting time = 262,144 states Waiting time = 1,024 states Illegal setting (Initial value) Bit 1--Software Standby Output Port Enable (SSOE): Specifies whether the address bus and bus control signals (CS0 to CS7, AS, RD, HWR, LWR, UCAS, LCAS, and RFSH) are kept as outputs or fixed high, or placed in the high-impedance state in software standby mode. Bit 1 SSOE 0 1 Description In software standby mode, the address bus and bus control signals are all high-impedance In software standby mode, the address bus retains its output state and bus control signals are fixed high (Initial value) Rev. 2.0, 06/04, page 700 of 980 20.2.2 Module Standby Control Register H (MSTCRH) MSTCRH is an 8-bit readable/writable register that controls output of the system clock (). It also controls the module standby function, which places individual on-chip supporting modules in the standby state. Module standby can be designated for the SCI0, SCI1, SCI2. Bit Modes 1 to 5 : Initial value Mode 7 : Initial value Read/Write 7 PSTOP 0 1 R/W 6 -- 1 1 -- 5 -- 1 1 -- 4 -- 1 1 -- 3 -- 1 1 -- 2 0 0 R/W 1 0 0 R/W 0 0 0 R/W MSTPH2 MSTPH1 MSTPH0 Reserved bit clock stop Enables or disables output of the system clock Module standby H2 to 0 These bits select modules to be placed in standby In modes 1 to 5, MSTCRH is initialized to H'78 by a reset and in hardware standby mode, while in mode 7 it is initialized to H'F8. It is not initialized in software standby mode. Bit 7-- Clock Stop (PSTOP): Enables or disables output of the system clock (). Bit 1 PSTOP 0 1 Description System clock output is enabled System clock output is disabled (Initial value : When modes 1 to 5 are selected) (Initial value : When mode 7 is selected) Bits 6 to 3--Reserved: These bits cannot be modified and are always read as 1. Bit 2--Module Standby H2 (MSTPH2): Selects whether to place the SCI2 in standby. Bit 2 MSTPH2 0 1 Description SCI2 operates normally SCI2 is in standby state (Initial value) Rev. 2.0, 06/04, page 701 of 980 Bit 1--Module Standby H1 (MSTPH1): Selects whether to place the SCI1 in standby. Bit 1 MSTPH1 0 1 Description SCI1 operates normally SCI1 is in standby state (Initial value) Bit 0--Module Standby H0 (MSTPH0): Selects whether to place the SCI0 in standby. Bit 0 MSTPH0 0 1 Description SCI0 operates normally SCI0 is in standby state (Initial value) 20.2.3 Module Standby Control Register L (MSTCRL) MSTCRL is an 8-bit readable/writable register that controls the module standby function, which places individual on-chip supporting modules in the standby state. Module standby can be designated for the DMAC, 16-bit timer, DRAM interface, 8-bit timer, and A/D converter modules. Bit Initial value Read/Write 7 MSTPL7 0 R/W 6 -- 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 -- 0 R/W 0 MSTPL0 0 R/W MSTPL5 MSTPL4 MSTPL3 MSTPL2 Reserved bits Module standby L7, L5 to L2, L0 These bits select modules to be placed in standby MSTCRL is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7--Module Standby L7 (MSTPL7): Selects whether to place the DMAC in standby. Bit 7 MSTPL7 0 1 Description DMAC operates normally DMAC is in standby state (Initial value) Rev. 2.0, 06/04, page 702 of 980 Bit 6--Reserved: This bit can be written and read. Bit 5--Module Standby L5 (MSTPL5): Selects whether to place the DRAM interface in standby. Bit 5 MSTPL5 0 1 Description DRAM interface operates normally DRAM interface is in standby state (Initial value) Bit 4--Module Standby L4 (MSTPL4): Selects whether to place the 16-bit timer in standby. Bit 4 MSTPL4 0 1 Description 16-bit timer operates normally 16-bit timer is in standby state (Initial value) Bit 3--Module Standby L3 (MSTPL3): Selects whether to place 8-bit timer channels 0 and 1 in standby. Bit 3 MSTPL3 0 1 Description 8-bit timer channels 0 and 1 operate normally 8-bit timer channels 0 and 1 are in standby state (Initial value) Bit 2--Module Standby L2 (MSTPL2): Selects whether to place 8-bit timer channels 2 and 3 in standby. Bit 2 MSTPL2 0 1 Description 8-bit timer channels 2 and 3 operate normally 8-bit timer channels 2 and 3 are in standby state (Initial value) Bit 1--Reserved: This bit can be written and read. Bit 0--Module Standby L0 (MSTPL0): Selects whether to place the A/D converter in standby. Bit 0 MSTPL0 0 1 Description A/D converter operates normally A/D converter is in standby state (Initial value) Rev. 2.0, 06/04, page 703 of 980 20.3 20.3.1 Sleep Mode Transition to Sleep Mode When the SSBY bit is cleared to 0 in SYSCR, execution of the SLEEP instruction causes a transition from the program execution state to sleep mode. Immediately after executing the SLEEP instruction the CPU halts, but the contents of its internal registers are retained. The DMA controller (DMAC), DRAM interface, and on-chip supporting modules do not halt in sleep mode. Modules which have been placed in standby by the module standby function, however, remain halted. 20.3.2 Exit from Sleep Mode Sleep mode is exited by an interrupt, or by input at the RES or STBY pin. Exit by Interrupt: An interrupt terminates sleep mode and causes a transition to the interrupt exception handling state. Sleep mode is not exited by an interrupt source in an on-chip supporting module if the interrupt is disabled in the on-chip supporting module. Sleep mode is not exited by an interrupt other than NMI if the interrupt is masked by interrupt priority settings and the settings of the I and UI bits in CCR, IPR. Exit by RES Input: Low input at the RES pin exits from sleep mode to the reset state. Exit by STBY Input: Low input at the STBY pin exits from sleep mode to hardware standby mode. Rev. 2.0, 06/04, page 704 of 980 20.4 20.4.1 Software Standby Mode Transition to Software Standby Mode To enter software standby mode, execute the SLEEP instruction while the SSBY bit is set to 1 in SYSCR. In software standby mode, current dissipation is reduced to an extremely low level because the CPU, clock, and on-chip supporting modules all halt. The DMAC and on-chip supporting modules are reset and halted. As long as the specified voltage is supplied, however, CPU register contents and on-chip RAM data are retained. The settings of the I/O ports and DRAM interface* are also held. When the WDT is used as a watchdog timer (WT/IT = 1), the TME bit must be cleared to 0 before setting SSBY. Also, when setting TME to 1, SSBY should be cleared to 0. Clear the BRLE bit in BRCR (inhibiting bus release) before making a transition to software standby mode. Note: * RTCNT and bits 7 and 6 of RTMCSR are initialized. Other bits and registers hold their previous states. 20.4.2 Exit from Software Standby Mode Software standby mode can be exited by input of an external interrupt at the NMI, IRQ0, IRQ1, or IRQ2 pin, or by input at the RES or STBY pin. Exit by Interrupt: When an NMI, IRQ0, IRQ1, or IRQ2 interrupt request signal is received, the clock oscillator begins operating. After the oscillator settling time selected by bits STS2 to STS0 in SYSCR, stable clock signals are supplied to the entire chip, software standby mode ends, and interrupt exception handling begins. Software standby mode is not exited if the interrupt enable bits of interrupts IRQ0, IRQ1, and IRQ2 are cleared to 0, or if these interrupts are masked in the CPU. Exit by RES Input: When the RES input goes low, the clock oscillator starts and clock pulses are supplied immediately to the entire chip. The RES signal must be held low long enough for the clock oscillator to stabilize. When RES goes high, the CPU starts reset exception handling. Exit by STBY Input: Low input at the STBY pin causes a transition to hardware standby mode. Rev. 2.0, 06/04, page 705 of 980 20.4.3 Selection of Waiting Time for Exit from Software Standby Mode Bits STS2 to STS0 in SYSCR and bits DIV1 and DIV0 in DIVCR should be set as follows. Crystal Resonator: Set STS2 to STS0, DIV1, and DIV0 so that the waiting time (for the clock to stabilize) is at least 7 ms. Table 20.3 indicates the waiting times that are selected by STS2 to STS0, DIV1, and DIV0 settings at various system clock frequencies. External Clock: Set STS2 to STS0, DIV1, and DIV0 so that the waiting time is at least 100 s. Table 20.3 Clock Frequency and Waiting Time for Clock to Settle DIV1 DIV0 STS2 STS1 STS0 Waiting Time 25 MHz 0 0 0 0 0 0 1 1 1 1 0 1 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 8192 states 16384 states 32768 states 65536 states 2.6 5.2 10.5 21.0* 3.3 6.6 13.1* 26.2 52.4 104.9 0.41 3.6 7.3* 14.6 29.1 58.3 116.5 0.46 8192 states 16384 states 32768 states 65536 states 1.3 2.6 5.2 10.5* 1.6 3.3 6.6 13.1* 26.2 52.4 0.20 1.8 3.6 7.3* 14.6 29.1 58.3 0.23 8192 states 16384 states 32768 states 65536 states 0.7 1.3 2.6 5.2 0.8 1.6 3.3 6.6 13.1* 26.2 0.10 0.91 1.8 3.6 7.3* 14.6 29.1 0.11 8192 states 16384 states 32768 states 65536 states 0.3 0.7 1.3 2.6 20 MHz 0.4 0.8 1.6 3.3 6.6 13.1* 0.05 18 MHz 0.46 0.91 1.8 3.6 7.3* 14.6 0.057 16 MHz 0.51 1.0 2.0 4.1 8.2* 16.4 0.064 Illegal setting 1.02 2.0 4.1 8.2* 16.4 32.8 0.13 Illegal setting 2.0 4.1 8.2* 16.4 32.8 65.5 0.26 Illegal setting 4.1 8.2* 16.4 32.8 65.5 131.1 0.51 Illegal setting 5.5 10.9* 21.8 43.7 87.4 174.8 0.68 6.6 13.1* 26.2 52.4 104.9 209.7 0.82 ms 2.7 5.5 10.9* 21.8 43.7 87.4 0.34 3.3 6.6 13.1* 26.2 52.4 104.9 0.41 ms 1.4 2.7 5.5 10.9* 21.8 43.7 0.17 1.6 3.3 6.6 13.1* 26.2 52.4 0.20 ms 12 MHz 0.65 1.3 2.7 5.5 10.9* 21.8 0.085 10 MHz 0.8 1.6 3.3 6.6 13.1* 26.2 0.10 Unit ms 131072 states 5.2 262144 states 10.5* 1024 states 0.04 131072 states 10.5* 262144 states 21.0 1024 states 0.08 131072 states 21.0 262144 states 41.9 1024 states 0.16 131072 states 41.9 262144 states 83.9 1024 states 0.33 * : Recommended setting Rev. 2.0, 06/04, page 706 of 980 20.4.4 Sample Application of Software Standby Mode Figure 20.1 shows an example in which software standby mode is entered at the fall of NMI and exited at the rise of NMI. With the NMI edge select bit (NMIEG) cleared to 0 in SYSCR (selecting the falling edge), an NMI interrupt occurs. Next the NMIEG bit is set to 1 (selecting the rising edge) and the SSBY bit is set to 1; then the SLEEP instruction is executed to enter software standby mode. Software standby mode is exited at the next rising edge of the NMI signal. Clock oscillator NMI NMIEG SSBY NMI interrupt handler NMIEG = 1 SSBY = 1 Software standby mode (powerdown state) Oscillator settling time (tosc2) NMI exception handling SLEEP instruction Figure 20.1 NMI Timing for Software Standby Mode (Example) 20.4.5 Note The I/O ports retain their existing states in software standby mode. If a port is in the high output state, its output current is not reduced. Rev. 2.0, 06/04, page 707 of 980 20.5 20.5.1 Hardware Standby Mode Transition to Hardware Standby Mode Regardless of its current state, the chip enters hardware standby mode whenever the STBY pin goes low. Hardware standby mode reduces power consumption drastically by halting all functions of the CPU, DMAC, DRAM interface, and on-chip supporting modules. All modules are reset except the on-chip RAM. As long as the specified voltage is supplied, on-chip RAM data is retained. I/O ports are placed in the high-impedance state. Clear the RAME bit to 0 in SYSCR before STBY goes low to retain on-chip RAM data. The inputs at the mode pins (MD2 to MD0) should not be changed during hardware standby mode. Note : Do not select the hardware standby mode during the reset period following power-on. 20.5.2 Exit from Hardware Standby Mode Hardware standby mode is exited by inputs at the STBY and RES pins. While RES is low, when STBY goes high, the clock oscillator starts running. RES should be held low long enough for the clock oscillator to settle. When RES goes high, reset exception handling begins, followed by a transition to the program execution state. 20.5.3 Timing for Hardware Standby Mode Figure 20.2 shows the timing relationships for hardware standby mode. To enter hardware standby mode, first drive RES low, then drive STBY low. To exit hardware standby mode, first drive STBY high, wait for the clock to settle, then bring RES from low to high. Rev. 2.0, 06/04, page 708 of 980 Clock oscillator RES STBY Oscillator settling time Reset exception handling Figure 20.2 Hardware Standby Mode Timing 20.5.4 Timing for Hardware Standby Mode at Power-On Figure 20.3 shows the timing relationships for entering hardware standby mode when the power is turned on. To make a transition to hardware standby mode when the power is turned on, hold the RES pin low for the stipulated time while keeping the STBY pin high. After the reset is cleared, set the STBY pin low. For details on exiting hardware standby mode, see section 20.5.3, Timing for Hardware Standby Mode. Power supply RES Reset period STBY Hardware standby mode Figure 20.3 Timing for Hardware Standby Mode at Power-On Rev. 2.0, 06/04, page 709 of 980 20.6 20.6.1 Module Standby Function Module Standby Timing The module standby function can halt several of the on-chip supporting modules (SCI2, SCI1, SCI0, the DMAC, 16-bit timer, 8-bit timer, DRAM interface, and A/D converter) independently in the power-down state. This standby function is controlled by bits MSTPH2 to MSTPH0 in MSTCRH and bits MSTPL7 to MSTPL0 in MSTCRL. When one of these bits is set to 1, the corresponding on-chip supporting module is placed in standby and halts at the beginning of the next bus cycle after the MSTCR write cycle. 20.6.2 Read/Write in Module Standby When an on-chip supporting module is in module standby, read/write access to its registers is disabled. Read access always results in H'FF data. Write access is ignored. 20.6.3 Usage Notes When using the module standby function, note the following points. DMAC: When setting a bit in MSTCR to 1 to place the DMAC in module standby, make sure that the DMAC is not currently requesting the bus right. If the corresponding bit in MSTCR is set to 1 when a bus request is present, operation of the bus arbiter becomes ambiguous and a malfunction may occur. DRAM Interface: When the module standby function is used on the DRAM interface, set the MSTCR bit to 1 while DRAM space is deselected. On-Chip Supporting Module Interrupts: Before setting a module standby bit, first disable interrupts by that module. When an on-chip supporting module is placed in standby by the module standby function, its registers are initialized, including registers with interrupt request flags. Pin States: Pins used by an on-chip supporting module lose their module functions when the module is placed in module standby. What happens after that depends on the particular pin. For details, see section 8, I/O Ports. Pins that change from the input to the output state require special care. For example, if SCI1 is placed in module standby, the receive data pin loses its receive data function and becomes a port pin. If its port DDR bit is set to 1, the pin becomes a data output pin, and its output may collide with external SCI transmit data. Data collision should be prevented by clearing the port DDR bit to 0 or taking other appropriate action. Register Resetting: When an on-chip supporting module is halted by the module standby function, all its registers are initialized. To restart the module, after its MSTCR bit is cleared to 0, its registers must be set up again. It is not possible to write to the registers while the MSTCR bit is set to 1. Rev. 2.0, 06/04, page 710 of 980 MSTCR Access from DMAC Disabled: To prevent malfunctions, MSTCR can only be accessed from the CPU. It can be read by the DMAC, but it cannot be written by the DMAC. 20.7 System Clock Output Disabling Function Output of the system clock () can be controlled by the PSTOP bit in MSTCRH. When the PSTOP bit is set to 1, output of the system clock halts and the pin is placed in the highimpedance state. Figure 20.4 shows the timing of the stopping and starting of system clock output. When the PSTOP bit is cleared to 0, output of the system clock is enabled. Table 20.4 indicates the state of the pin in various operating states. MSTCRH write cycle (PSTOP = 1) T1 pin High impedance T2 T3 MSTCRH write cycle (PSTOP = 0) T1 T2 T3 Figure 20.4 Starting and Stopping of System Clock Output Table 20.4 Pin State in Various Operating States Operating State Hardware standby Software standby Sleep mode Normal operation PSTOP = 0 High impedance Always high System clock output System clock output PSTOP = 1 High impedance High impedance High impedance High impedance Rev. 2.0, 06/04, page 711 of 980 Rev. 2.0, 06/04, page 712 of 980 Section 21 Electrical Characteristics 21.1 21.1.1 Electrical Characteristics of HD64F3029F25 and HD64F3029TE25 Absolute Maximum Ratings Table 21.1 lists the absolute maximum ratings. Table 21.1 Absolute Maximum Ratings Item Power supply voltage Input voltage (FWE)* Input voltage (port 7) Reference voltage Analog power supply voltage Analog input voltage Operating temperature Storage temperature 2 2 Symbol VCC* Vin Vin Vin VREF AVCC VAN Topr Tstg 1 Value -0.3 to +4.6 -0.3 to VCC +0.3 -0.3 to VCC +0.3 -0.3 to AVCC +0.3 -0.3 to AVCC +0.3 -0.3 to +4.6 -0.3 to AVCC +0.3 Regular specifications: -20 to +75* -55 to +125 3 Unit V V V V V V V C C Input voltage (except for port 7)* Caution: Permanent damage to the chip may result if absolute maximum ratings are exceeded. Notes: *1 Do not apply the power supply voltage to the VCL pin. Connect an external capacitor between this pin and GND. *2 12 V must not be applied to any pin, as this may cause permanent damage to the device. *3 The operating temperature range for flash memory programming/erasing is Ta = 0 to +75C (Regular specifications). Rev. 2.0, 06/04, page 713 of 980 21.1.2 DC Characteristics Table 21.2 lists the DC characteristics. Table 21.3 lists the permissible output currents. Table 21.2 DC Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 to 3.6 V, VREF = 3.0 V to AVCC* , 1 VSS = AVSS = 0 V* , Ta =-20C to +75C (Regular specifications), [Programming/erasing conditions: Ta = 0C to +75C (Regular specifications)] Item Schmitt trigger Port A, input voltages P80 to P82 STBY, RES, NMI, MD2 to MD0, FWE EXTAL Port 7 Ports 1 to 6, P83, P84, P90 to P95, port B Input low voltage STBY, RES, FWE, MD2 to MD0 NMI, EXTAL, ports 1 to 7, P83, P84, P90 to P95, port B Output high voltage Output low voltage All output pins All output pins Ports 1, 2, and 5 Input leakage STBY, RES, current NMI, FWE, MD2 to MD0 Port 7 |Iin| VOH VOL VIL Symbol VT VT - + + - 1 Min VCC x 0.2 -- VCC x 0.9 Typ -- -- -- Max -- VCC x 0.7 -- VCC + 0.3 Unit V V V V Test Conditions VT - VT Input high voltage VIH VCC x 0.05 -- VCC x 0.7 VCC x 0.7 VCC x 0.7 -- -- -- VCC + 0.3 VCC + 0.3 V V AVCC + 0.3 V -0.3 -- VCC x 0.1 V -0.3 -- VCC x 0.2 V VCC - 0.5 VCC - 1.0 -- -- -- -- -- -- -- -- -- -- 0.4 1.0 1.0 V V V V A IOH = -200 A IOH = -1 mA IOL = 1.6 mA IOL = 5 mA Vin = 0.5 V to VCC - 0.5 V Vin = 0.5 V to AVCC - 0.5 V -- -- 1.0 A Rev. 2.0, 06/04, page 714 of 980 Item Three-state leakage current Input pull-up MOS current Input capacitance Ports 1 to 6, Ports 8 to B Ports 2, 4, and 5 FWE NMI All input pins except NMI Current 2 dissipation* Normal operation Sleep mode Module standby mode Standby mode Flash memory programming/ 4 erasing* Analog power During A/D supply current conversion During A/D and D/A conversion Idle Symbol |ITSI| Min -- Typ -- Max 1.0 Unit A Test Conditions Vin = 0.5 V to VCC - 0.5 V Vin = 0 V Vin = 0 V, f = fmin, Ta = 25C -Ip Cin 10 -- -- -- -- -- -- -- 20(3.3V) 17(3.3V) 16(3.3V) 15(3.3V) -- 30(3.3V) 300 80 50 15 38 35 34 70 100 48 A pF pF pF mA mA mA A A mA ICC* 3 -- -- -- -- -- -- f = 25 MHz f = 25 MHz f = 25 MHz Ta 50C 50C < Ta f = 25 MHz (reference values) AICC -- -- 0.6 0.6 1.5 1.5 mA mA -- -- 0.02(3.3V) 5.0 -- 15 A A Ta 50C at DASTE = 0 50C < Ta at DASTE = 0 Rev. 2.0, 06/04, page 715 of 980 Item Reference current During A/D conversion During A/D and D/A conversion Idle RAM standby voltage VCL output Voltage* VCC start Voltage* 6 6 5 Symbol AICC Min -- -- Typ 0.25 1.2 Max 0.8 3.0 Unit mA mA Test Conditions -- VRAM VCL VCC START SVCC 3.0 1.5 -- 0.05 0.02 -- 1.9 0 -- 5.0 -- 2.3 0.8 -- A V V V V/ms DASTE = 0 VCC = 3.3V Ta = 25C Normal operation VCC rise rate* Notes: *1 If the A/D converter is not used, do not leave the AVCC, VREF, and AVSS pins open. Connect AVCC and VREF to VCC, and connect AVSS to VSS. *2 Current dissipation values are for VIH min = VCC - 0.5 V and VIL max = 0.5 V with all output pins unloaded and the on-chip MOS pull-up transistors in the off state. *3 ICC max. (normal operation) = 11 (mA) + 0.13 (mA/(MHz x V)) x VCC x f ICC max. (sleep mode) = 11 (mA) + 0.11 (mA/(MHz x V)) x VCC x f ICC max. (sleep mode + module standby mode) = 11 (mA) + 0.10 (mA/(MHz x V)) x VCC x f The Typ values for power consumption are reference values. *4 Sum of current dissipation in normal operation and current dissipation in program/erase operations. *5 This value is applied when the external capacitor of 0.1 F is connected. This characteristic does not specify the permissible range of voltage input from the external circuit but specifies the voltage output by the LSI. *6 These characteristics are applied under the condition in which the RES pin goes low when powering on. Rev. 2.0, 06/04, page 716 of 980 Table 21.3 Permissible Output Currents Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VREF = 3.0 V to AVCC, VSS = AVSS = 0 V, Ta = -20C to +75C (Regular specifications) Item Permissible output low current (per pin) Permissible output low current (total) Ports 1, 2, and 5 Other output pins Total of 20 pins in Ports 1, 2, and 5 Total of all output pins, including the above Permissible output high current (per pin) Permissible output high current (total) All output pins Total of all output pins | -IOH | | -IOH | IOL Symbol IOL Min -- -- -- -- -- -- Typ -- -- -- -- -- -- Max 10 2.0 80 120 2.0 40 Unit mA mA mA mA mA mA Notes: 1. To protect chip reliability, do not exceed the output current values in table 21.3. 2. When directly driving a darlington pair or LED, always insert a current-limiting resistor in the output line, as shown in figures 21.1 and 21.2. H8/3029F-ZTAT 2 k Port Darlington pair Figure 21.1 Darlington Pair Drive Circuit (Example) Rev. 2.0, 06/04, page 717 of 980 H8/3029F-ZTAT 600 Ports 1, 2, 5 LED Figure 21.2 Sample LED Circuit Rev. 2.0, 06/04, page 718 of 980 21.1.3 AC Characteristics Clock timing parameters are listed in table 21.4, control signal timing parameters in table 21.5, and bus timing parameters in table 21.6. Timing parameters of the on-chip supporting modules are listed in table 21.7. Table 21.4 Clock Timing Condition: Ta = -20C to +75C (Regular specifications), VCC = 3.0 V to 3.6 V, ACCC = 3.0 V to 3.6 V, VREF = 3.0 V to AVCC, VSS = AVSS = 0 V, fmax = 25 MHz Symbol tcyc tCL tCH tCr tCf tOSC1 Min 40 10 10 -- -- 20 7 Max 100 -- -- 10 10 -- -- Unit ns ns ns ns ns ms ms Figure 21.10 Figure 20.1 Test Conditions Figure 21.13 Item Clock cycle time Clock pulse low width Clock pulse high width Clock rise time Clock fall time Clock oscillator settling time at reset Clock oscillator settling tOSC2 time in software standby Table 21.5 Control Signal Timing Conditions: Ta = -20C to +75C (Regular specifications), VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VREF = 3.0 V to AVCC, VSS = AVSS = 0 V, fmax = 25 MHz Item RES setup time RES pulse width Mode programming setup time NMI, IRQ setup time NMI, IRQ hold time NMI, IRQ pulse width Symbol tRESS tRESW tMDS tNMIS tNMIH tNMIW Min 150 20 200 150 10 200 Max -- -- -- -- -- -- Unit ns tcyc ns ns ns ns Figure 21.12 Test Conditions Figure 21.11 Rev. 2.0, 06/04, page 719 of 980 Table 21.6 Bus Timing Conditions: Ta = -20C to +75C (Regular specifications), VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VREF = 3.0 V to AVCC, VSS = AVSS = 0 V, fmax = 25 MHz Item Address delay time Address hold time Read strobe delay time Address strobe delay time Write strobe delay time Strobe delay time Write strobe pulse width 1 Write strobe pulse width 2 Address setup time 1 Address setup time 2 Read data setup time Read data hold time Write data delay time Write data setup time 1 Write data setup time 2 Write data hold time Symbol tAD tAH tRSD tASD tWSD tSD tWSW1 tWSW2 tAS1 tAS2 tRDS tRDH tWDD tWDS1 tWDS2 tWDH Min -- 0.5 tcyc - 20 -- -- -- -- 1.0 tcyc - 25 1.5 tcyc - 25 0.5 tcyc - 20 1.0 tcyc - 20 25 0 -- 1.0 tcyc- 30 2.0 tcyc- 30 0.5 tcyc- 15 Max 25 -- 25 25 25 25 -- -- -- -- -- -- 35 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions Figure 21.13, Figure 21.14, Figure 21.16, Figure 21.17, Figure 21.19 Rev. 2.0, 06/04, page 720 of 980 Item Read data access time 1 Read data access time 2 Read data access time 3 Read data access time 4 Precharge time 1 Precharge time 2 Wait setup time Wait hold time Bus request setup time Bus acknowledge delay time 1 Bus acknowledge delay time 2 Bus-floating time RAS precharge time CAS precharge time Low address hold time RAS delay time 1 RAS delay time 2 CAS delay time 1 CAS delay time 2 WE delay time Symbol tACC1 tACC2 tACC3 tACC4 tPCH1 tPCH2 tWTS tWTH tBRQS tBACD1 tBACD2 tBZD tRP tCP tRAH tRAD1 tRAD2 tCASD1 tCASD2 tWCD Min -- -- -- -- 1.0 tcyc - 20 0.5 tcyc - 20 25 5 25 -- -- -- 1.5 tcyc - 25 0.5 tcyc - 15 0.5 tcyc - 15 -- -- -- -- -- Max 2.0 tcyc- 45 3.0 tcyc - 45 1.5 tcyc - 45 2.5 tcyc - 45 -- -- -- -- -- 30 30 30 -- -- -- 25 30 25 25 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions Figure 21.13, Figure 21.14, Figure 21.16, Figure 21.17 Figure 21.15 Figure 21.18 Figure 21.19 to Figure 21.20 Rev. 2.0, 06/04, page 721 of 980 Item CAS pulse width 1 CAS pulse width 2 CAS pulse width 3 RAS access time Address access time CAS access time WE setup time WE hold time Write data setup time WE write data hold time CAS setup time 1 CAS setup time 2 CAS hold time RAS pulse width Signal rising time (all input pins except for EXTAL) Signal falling time (all input pins except for EXTAL) Symbol tCAS1 tCAS2 tCAS3 tRAC tAA tCAC tWCS tWCH tWDS tWDH tCSR1 tCSR2 tCHR tRAS tSR Min 1.5 tcyc - 20 1.0 tcyc - 20 1.0 tcyc - 20 -- -- -- 0.5 tcyc - 20 0.5 tcyc - 15 0.5 tcyc - 20 0.5 tcyc - 15 0.5 tcyc - 20 0.5 tcyc - 15 0.5 tcyc - 15 1.5 tcyc - 15 -- Max -- -- -- 2.5 tcyc - 40 2.0 tcyc - 50 1.5 tcyc - 50 -- -- -- -- -- -- -- -- 100 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions Figure 21.19 to Figure 21.21 Figure 21.30 tSF -- 100 ns Note: In order to secure the address hold time relative to the rise of the RD strobe, address update mode 2 should be used. For details see section 6.3.5, Address Output Method. Rev. 2.0, 06/04, page 722 of 980 Table 21.7 Timing of On-Chip Supporting Modules Conditions: Ta = -20C to +75C (Regular specifications), VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VREF = 3.0 V to AVCC, VSS = AVSS = 0 V, fmax = 25 MHz Module Item Ports and TPC Output data delay time Input data setup time Input data hold time 16-bit timer Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width 8-bit timer Single edge Both edges Symbol tPWD tPRS tPRH tTOCD tTICS tTCKS tTCKWH tTCKWL tTOCD tTICS tTCKS tTCKWH tTCKWL Min -- 50 50 -- 50 50 1.5 2.5 -- 50 50 1.5 2.5 Max 50 -- -- 50 -- -- -- -- 50 -- -- -- -- Unit ns ns ns ns ns ns tcyc tcyc ns ns ns tcyc tcyc Figure 21.24 Figure 21.23 Figure 21.24 Figure 21.23 Test Conditions Figure 21.22 Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width Single edge Both edges Rev. 2.0, 06/04, page 723 of 980 Module Item SCI Input clock cycle Symbol AsyntScyc chronous Synchronous tSCKr tSCKf tSCKW tTXD tRXS Min 4 6 -- -- 0.4 -- 100 Max -- -- 1.5 1.5 0.6 100 -- Unit tcyc tcyc tcyc tcyc tScyc ns ns Test Conditions Figure 21.25 Input clock rise time Input clock fall time Input clock pulse width Transmit data delay time Receive data setup time (synchronous) Receive data hold time (synchronous) DMAC Clock input Clock output Figure 21.26 tRXH 100 0 -- -- 25 10 -- -- 50 50 -- -- ns ns ns ns ns ns Figure 21.27, Figure 21.28 Figure 21.29 TEND delay time 1 tTED1 TEND delay time 2 tTED2 DREQ setup time DREQ hold time tDRQS tDRQH RL H8/3029F-ZTAT output pin C = 90 pF: Ports 4, 6, 8 A19 to A0, D15 to D8 C = 30 pF: Ports 9, A, B R L = 2.4 k R H = 12 k C RH Input/output timing measurement levels * Low: Vcc 0.2 V * High: Vcc 0.7 V Figure 21.3 Output Load Circuit Rev. 2.0, 06/04, page 724 of 980 21.1.4 A/D Conversion Characteristics Table 21.8 lists the A/D conversion characteristics. Table 21.8 A/D Conversion Characteristics Conditions: Ta = -20C to +75C (Regular specifications), VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VREF = 3.0 V to AVCC, VSS = AVSS = 0 V, fmax = 25 MHz Item ConverResolution sion time: Conversion time (single 134 states mode) Analog input capacitance Permissible 13 MHz signal-source impedance > 13 MHz Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Item ConverResolution sion time*: Conversion time (single 70 states mode) Analog input capacitance Permissible signal-source impedance Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Note: * Min 10 5.36 -- -- -- -- -- -- -- -- Min 10 5.38 -- -- -- -- -- -- -- Typ 10 -- -- -- -- -- -- -- -- -- Typ 10 -- -- -- -- -- -- -- -- Max 10 -- 20 10 5 3.5 3.5 3.5 0.5 4.0 Max 10 -- 20 5 7.5 7.5 7.5 0.5 8.0 Unit bits s pF k k LSB LSB LSB LSB LSB Unit bits s pF k LSB LSB LSB LSB LSB When using an operating frequency above f = 70 (state) /5.38 (s) = 13.0 (MHz), do not select 70-state conversion time. Rev. 2.0, 06/04, page 725 of 980 21.1.5 D/A Conversion Characteristics Table 21.9 lists the D/A conversion characteristics. Table 21.9 D/A Conversion Characteristics Conditions: Ta = -20C to +75C (Regular specifications), VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VREF = 3.0 V to AVCC, VSS = AVSS = 0 V, fmax = 25 MHz Item Resolution Conversion time (centering time) Absolute accuracy* Min 8 -- -- -- Note: * Typ 8 -- 2.0 -- Max 8 10 3.0 2.0 Unit bits s LSB LSB 20 pF capacitive load 2 M resistive load 4 M resistive load Test Conditions Except in software standby mode. Rev. 2.0, 06/04, page 726 of 980 21.1.6 Flash Memory Characteristics Table 21.10 shows the flash memory characteristics. Table 21.10 Flash Memory Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, Ta = 0C to +75C (operating temperature range for programming/erasing : Regular specifications) Item Programming time*1, *2, *4 Erase time*1, *2, *4 Symbol Min tP tE -- -- -- -- Programming time (total)*1, *2, *4 Erase time (total)*1, *2, *4 tP tE -- -- -- Typ 3 80 500 1000 10 10 20 Max 30 800 5000 Unit ms/128 bytes ms/4-kbyte blocks ms/32-kbyte blocks Notes 10000 ms/64-kbyte blocks 30 30 60 -- -- s/512 kbytes s/512 kbytes s/512 kbytes times year Ta = 25C, (when data is all 0) Ta = 25C Ta = 25C Programming and erase time (total)*1, *2, *4 tPE Reprogramming count Data retention time* 4 NWEC tDRP 100*3 -- 10 -- Notes: *1 Programming time and erase time depend on data. *2 Programming time and erase time do not include the data transfer time. *3 Minimum value when all characteristics after reprogramming are guaranteed (the characteristics are guaranteed while the reprogramming count is from one to the minimum reprogramming count). *4 Characteristics when the flash memory is rewritten within the minimum reprogramming count. Rev. 2.0, 06/04, page 727 of 980 21.2 Electrical Characteristics of HD64F3029F25W and HD64F3029TE25W Absolute Maximum Ratings 21.2.1 Table 21.11 lists the absolute maximum ratings. Table 21.11 Absolute Maximum Ratings Item Power supply voltage Input voltage (FWE)* Input voltage (port 7) Reference voltage Analog power supply voltage Analog input voltage Operating temperature Storage temperature 2 2 Symbol VCC* Vin Vin Vin VREF AVCC VAN Topr Tstg 1 Value -0.3 to +4.6 -0.3 to VCC +0.3 -0.3 to VCC +0.3 -0.3 to AVCC +0.3 -0.3 to AVCC +0.3 -0.3 to +4.6 -0.3 to AVCC +0.3 Wide-range specifications: -40 to +85* -55 to +125 3 Unit V V V V V V V C C Input voltage (except for port 7)* Caution: Permanent damage to the chip may result if absolute maximum ratings are exceeded. Notes: *1 Do not apply the power supply voltage to the VCL pin. Connect an external capacitor between this pin and GND. *2 12 V must not be applied to any pin, as this may cause permanent damage to the device. *3 The operating temperature range for flash memory programming/erasing is Ta = 0 to +85C (Wide-range specifications). Rev. 2.0, 06/04, page 728 of 980 21.2.2 DC Characteristics Table 21.12 lists the DC characteristics. Table 21.13 lists the permissible output currents. Table 21.12 DC Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VREF = 3.0 V to AVCC* , 1 VSS = AVSS = 0 V* , Ta =-40C to +85C (Wide-range specifications), [Programming/erasing conditions: Ta = 0C to +85C (Wide-range specifications)] Item Schmitt trigger Port A, input voltages P80 to P82 STBY, RES, NMI, MD2 to MD0, FWE EXTAL Port 7 Ports 1 to 6, P83, P84, P90 to P95, port B Input low voltage STBY, RES, FWE, MD2 to MD0 NMI, EXTAL, ports 1 to 7, P83, P84, P90 to P95, port B Output high voltage Output low voltage All output pins All output pins Ports 1, 2, and 5 Input leakage STBY, RES, current NMI, FWE, MD2 to MD0 Port 7 |Iin| VOH VOL VIL Symbol VT VT - + + - 1 Min VCC x 0.2 -- VCC x 0.9 Typ -- -- -- Max -- VCC x 0.7 -- VCC + 0.3 Unit V V V V Test Conditions VT - VT Input high voltage VIH VCC x 0.05 -- VCC x 0.7 VCC x 0.7 VCC = 0.7 -- -- -- VCC + 0.3 VCC + 0.3 V V AVCC + 0.3 V -0.3 -- VCC x 0.1 V -0.3 -- VCC x 0.2 V VCC - 0.5 VCC - 1.0 -- -- -- -- -- -- -- -- -- -- 0.4 1.0 1.0 V V V V A IOH = -200 A IOH = -1 mA IOL = 1.6 mA IOL = 5 mA Vin = 0.5 V to VCC - 0.5 V Vin = 0.5 V to AVCC - 0.5 V -- -- 1.0 A Rev. 2.0, 06/04, page 729 of 980 Item Three-state leakage current Input pull-up MOS current Input capacitance Ports 1 to 6, Ports 8 to B Ports 2, 4, and 5 FWE NMI All input pins except NMI Current 2 dissipation* Normal operation Sleep mode Module standby mode Standby mode Flash memory programming/ 4 erasing* Analog power During A/D supply current conversion During A/D and D/A conversion Idle Symbol |ITSI| Min -- Typ -- Max 1.0 Unit A Test Conditions Vin = 0.5 V to VCC - 0.5 V Vin = 0 V Vin = 0 V, f = fmin, Ta = 25C -Ip Cin 10 -- -- -- -- -- -- -- 2.0(3.3V) 17(3.3V) 16(3.3V) 15(3.3V) -- 30(3.3V) 300 80 50 15 38 35 34 70 100 48 A pF pF pF mA mA mA A A mA ICC* 3 -- -- -- -- -- -- f = 25 MHz f = 25 MHz f = 25 MHz Ta 50C 50C < Ta f = 25 MHz (reference values) AICC -- -- 0.6 0.6 1.5 1.5 mA mA -- -- 0.02(3.3V) 5.0 -- 15 A A Ta 50C at DASTE = 0 50C < Ta at DASTE = 0 Rev. 2.0, 06/04, page 730 of 980 Item Reference current During A/D conversion During A/D and D/A conversion Idle RAM standby voltage VCL output voltage* VCC start Voltage* 6 6 5 Symbol AICC Min -- -- Typ 0.25 1.2 Max 0.8 3.0 Unit mA mA Test Conditions -- VRAM VCL VCC START SVCC 3.0 1.5 -- 0.05 0.02 -- 1.9 0 -- 5.0 -- 2.3 0.8 -- A V V V V/ms DASTE = 0 VCC = 3.3V Ta = 25C Normal operation VCC rise rate* Notes: *1 If the A/D converter is not used, do not leave the AVCC, VREF, and AVSS pins open. Connect AVCC and VREF to VCC, and connect AVSS to VSS. *2 Current dissipation values are for VIH min = VCC - 0.5 V and VIL max = 0.5 V with all output pins unloaded and the on-chip MOS pull-up transistors in the off state. *3 ICC max. (normal operation) = 11 (mA) + 0.13 (mA/(MHz x V)) x VCC x f ICC max. (sleep mode) = 11 (mA) + 0.11 (mA/(MHz x V)) x VCC x f ICC max. (sleep mode + module standby mode) = 11 (mA) + 0.10 (mA/(MHz x V)) x VCC x f The Typ values for power consumption are reference values. *4 Sum of current dissipation in normal operation and current dissipation in program/erase operations. *5 This value is applied when the external capacitor of 0.1 F is connected. This characteristic does not specify the permissible range of voltage input from the external circuit but specifies the voltage output by the LSI. *6 These characteristics are applied under the condition in which the RES pin goes low when powering on. Rev. 2.0, 06/04, page 731 of 980 Table 21.13 Permissible Output Currents Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VREF = 3.0 V to AVCC, VSS = AVSS = 0 V, Ta = -40C to +85C (Wide-range specifications), Item Permissible output low current (per pin) Permissible output low current (total) Ports 1, 2, and 5 Other output pins Total of 20 pins in Ports 1, 2, and 5 Total of all output pins, including the above Permissible output high current (per pin) Permissible output high current (total) All output pins Total of all output pins | -IOH | | -IOH | IOL Symbol IOL Min -- -- -- -- -- -- Typ -- -- -- -- -- -- Max 10 2.0 80 120 2.0 40 Unit mA mA mA mA mA mA Notes: 1. To protect chip reliability, do not exceed the output current values in table 21.13. 2. When directly driving a darlington pair or LED, always insert a current-limiting resistor in the output line, as shown in figures 21.4 and 21.5. H8/3029F-ZTAT 2 k Port Darlington pair Figure 21.4 Darlington Pair Drive Circuit (Example) Rev. 2.0, 06/04, page 732 of 980 H8/3029F-ZTAT 600 Ports 1, 2, 5 LED Figure 21.5 Sample LED Circuit Rev. 2.0, 06/04, page 733 of 980 21.2.3 AC Characteristics Clock timing parameters are listed in table 21.14, control signal timing parameters in table 21.15, and bus timing parameters in table 21.16. Timing parameters of the on-chip supporting modules are listed in table 21.17. Table 21.14 Clock Timing Condition: Ta = -40C to +85C (Wide-range specifications), VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6V, VREF = 3.0 V to AVCC, VSS = AVSS = 0 V, fmax = 25 MHz Symbol tcyc tCL tCH tCr tCf tOSC1 Min 40 10 10 -- -- 20 7 Max 100 -- -- 10 10 -- -- Unit ns ns ns ns ns ms ms Figure 21.10 Figure 20.1 Test Conditions Figure 21.13 Item Clock cycle time Clock pulse low width Clock pulse high width Clock rise time Clock fall time Clock oscillator settling time at reset Clock oscillator settling tOSC2 time in software standby Table 21.15 Control Signal Timing Conditions: Ta = -40C to +85C (Wide-range specifications), VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VREF = 3.0 V to AVCC, VSS = AVSS = 0 V, fmax = 25 MHz Item RES setup time RES pulse width Mode programming setup time NMI, IRQ setup time NMI, IRQ hold time NMI, IRQ pulse width Symbol tRESS tRESW tMDS tNMIS tNMIH tNMIW Min 150 20 200 150 10 200 Max -- -- -- -- -- -- Unit ns tcyc ns ns ns ns Figure 21.12 Test Conditions Figure 21.11 Rev. 2.0, 06/04, page 734 of 980 Table 21.16 Bus Timing Conditions: Ta = -40C to +85C (Wide-range specifications), VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VREF = 3.0 V to AVCC, VSS = AVSS = 0 V, fmax = 25 MHz Item Address delay time Address hold time Read strobe delay time Address strobe delay time Write strobe delay time Strobe delay time Write strobe pulse width 1 Write strobe pulse width 2 Address setup time 1 Address setup time 2 Read data setup time Read data hold time Write data delay time Write data setup time 1 Write data setup time 2 Write data hold time Symbol tAD tAH tRSD tASD tWSD tSD tWSW1 tWSW2 tAS1 tAS2 tRDS tRDH tWDD tWDS1 tWDS2 tWDH Min -- 0.5 tcyc - 20 -- -- -- -- 1.0 tcyc - 25 1.5 tcyc - 25 0.5 tcyc - 20 1.0 tcyc - 20 25 0 -- 1.0 tcyc- 30 2.0 tcyc- 30 0.5 tcyc- 15 Max 25 -- 25 25 25 25 -- -- -- -- -- -- 35 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions Figure 21.13, Figure 21.14, Figure 21.16, Figure 21.17, Figure 21.19 Rev. 2.0, 06/04, page 735 of 980 Item Read data access time 1 Read data access time 2 Read data access time 3 Read data access time 4 Precharge time 1 Precharge time 2 Wait setup time Wait hold time Bus request setup time Bus acknowledge delay time 1 Bus acknowledge delay time 2 Bus-floating time RAS precharge time CAS precharge time Low address hold time RAS delay time 1 RAS delay time 2 CAS delay time 1 CAS delay time 2 WE delay time Symbol tACC1 tACC2 tACC3 tACC4 tPCH1 tPCH2 tWTS tWTH tBRQS tBACD1 tBACD2 tBZD tRP tCP tRAH tRAD1 tRAD2 tCASD1 tCASD2 tWCD Min -- -- -- -- 1.0 tcyc - 20 0.5 tcyc - 20 25 5 25 -- -- -- 1.5 tcyc - 25 0.5 tcyc - 15 0.5 tcyc - 15 -- -- -- -- -- Max 2.0 tcyc- 45 3.0 tcyc - 45 1.5 tcyc - 45 2.5 tcyc - 45 -- -- -- -- -- 30 30 30 -- -- -- 25 30 25 25 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions Figure 21.13, Figure 21.14, Figure 21.16, Figure 21.17 Figure 21.15 Figure 21.18 Figure 21.19, Figure 21.20 Rev. 2.0, 06/04, page 736 of 980 Item CAS pulse width 1 CAS pulse width 2 CAS pulse width 3 RAS access time Address access time CAS access time WE setup time WE hold time Write data setup time WE write data hold time CAS setup time 1 CAS setup time 2 CAS hold time RAS pulse width Signal rising time (all input pins except for EXTAL) Signal falling time (all input pins except for EXTAL) Symbol tCAS1 tCAS2 tCAS3 tRAC tAA tCAC tWCS tWCH tWDS tWDH tCSR1 tCSR2 tCHR tRAS tSR Min 1.5 tcyc - 20 1.0 tcyc - 20 1.0 tcyc - 20 -- -- -- 0.5 tcyc - 20 0.5 tcyc - 15 0.5 tcyc - 20 0.5 tcyc - 15 0.5 tcyc - 20 0.5 tcyc - 15 0.5 tcyc - 15 1.5 tcyc - 15 -- Max -- -- -- 2.5 tcyc - 40 2.0 tcyc - 50 1.5 tcyc - 50 -- -- -- -- -- -- -- -- 100 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions Figure 21.19 to Figure 21.21 Figure 21.30 tSF -- 100 ns Note: In order to secure the address hold time relative to the rise of the RD strobe, address update mode 2 should be used. For details see section 6.3.5, Address Output Method. Rev. 2.0, 06/04, page 737 of 980 Table 21.17 Timing of On-Chip Supporting Modules Conditions: Ta = -40C to +85C (Wide-range specifications), VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VREF = 3.0 V to AVCC, VSS = AVSS = 0 V, fmax = 25 MHz Module Item Ports and TPC Output data delay time Input data setup time Input data hold time 16-bit timer Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width 8-bit timer Single edge Both edges Symbol tPWD tPRS tPRH tTOCD tTICS tTCKS tTCKWH tTCKWL tTOCD tTICS tTCKS tTCKWH tTCKWL Min -- 50 50 -- 50 50 1.5 2.5 -- 50 50 1.5 2.5 Max 50 -- -- 50 -- -- -- -- 50 -- -- -- -- Unit ns ns ns ns ns ns tcyc tcyc ns ns ns tcyc tcyc Figure 21.24 Figure 21.23 Figure 21.24 Figure 21.23 Test Conditions Figure 21.22 Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width Single edge Both edges Rev. 2.0, 06/04, page 738 of 980 Module Item SCI Input clock cycle Symbol AsyntScyc chronous Synchronous tSCKr tSCKf tSCKW tTXD tRXS Min 4 6 -- -- 0.4 -- 100 Max -- -- 1.5 1.5 0.6 100 -- Unit tcyc tcyc tcyc tcyc tScyc ns ns Test Conditions Figure 21.25 Input clock rise time Input clock fall time Input clock pulse width Transmit data delay time Receive data setup time (synchronous) Receive data hold time (synchronous) DMAC Clock input Clock output Figure 21.26 tRXH 100 0 -- -- 25 10 -- -- 50 50 -- -- ns ns ns ns ns ns Figure 21.27, Figure 21.28 Figure 21.29 TEND delay time 1 tTED1 TEND delay time 2 tTED2 DREQ setup time DREQ hold time tDRQS tDRQH RL H8/3029F-ZTAT output pin C = 90 pF: Ports 4, 6, 8 A19 to A0, D15 to D8 C = 30 pF: Ports 9, A, B R L = 2.4 k R H = 12 k C RH Input/output timing measurement levels * Low: Vcc 0.2 V * High: Vcc 0.7 V Figure 21.6 Output Load Circuit Rev. 2.0, 06/04, page 739 of 980 21.2.4 A/D Conversion Characteristics Table 21.18 lists the A/D conversion characteristics. Table 21.18 A/D Conversion Characteristics Conditions: Ta = -40C to +85C (Wide-range specifications), VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VREF = 3.0 V to AVCC, VSS = AVSS = 0 V, fmax = 25 MHz Item ConverResolution sion time: Conversion time (single 134 states mode) Analog input capacitance Permissible 13 MHz signal-source impedance > 13 MHz Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Item ConverResolution sion time*: Conversion time (single 70 states mode) Analog input capacitance Permissible signal-source impedance Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Note: * Min 10 5.36 -- -- -- -- -- -- -- -- Min 10 5.38 -- -- -- -- -- -- -- Typ 10 -- -- -- -- -- -- -- -- -- Typ 10 -- -- -- -- -- -- -- -- Max 10 -- 20 10 5 3.5 3.5 3.5 0.5 4.0 Max 10 -- 20 5 7.5 7.5 7.5 0.5 8.0 Unit bits s pF k k LSB LSB LSB LSB LSB Unit bits s pF k LSB LSB LSB LSB LSB When using an operating frequency above f = 70 (state) /5.38 (s) = 13.0 (MHz), do not select 70-state conversion time. Rev. 2.0, 06/04, page 740 of 980 21.2.5 D/A Conversion Characteristics Table 21.19 lists the D/A conversion characteristics. Table 21.19 D/A Conversion Characteristics Conditions: Ta = -40C to +85C (Wide-range specifications), VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VREF = 3.0 V to AVCC, VSS = AVSS = 0 V, fmax = 25 MHz Item Resolution Conversion time (centering time) Absolute accuracy* Min 8 -- -- -- Note: * Typ 8 -- 2.0 -- Max 8 10 3.0 2.0 Unit bits s LSB LSB 20 pF capacitive load 2 M resistive load 4 M resistive load Test Conditions Except in software standby mode. Rev. 2.0, 06/04, page 741 of 980 21.2.6 Flash Memory Characteristics Table 21.20 lists the flash memory characteristics. Table 21.20 Flash Memory Characteristics (1) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, Ta = 0C to +85C (operating temperature range for programming/erasing: Wide-range specifications) Item Programming time*1, *2, *4 Erase time*1, *2, *4 Symbol tP tE Min -- -- -- -- Programming time (total)*1, *2, *4 Erase time (total)*1, *2, *4 Programming and erase time (total)*1, *2, *4 Reprogramming count Data retention time* 4 Typ 3 80 500 1000 10 10 20 -- -- Max 30 800 5000 10000 30 30 60 -- -- Unit ms/128 bytes ms/4-kbyte block ms/32-kbyte block ms/64-kbyte block s/512 kbytes s/512 kbytes s/512 kbytes Times Year Test Conditions tP tE tPE NWEC tDRP -- -- -- 100*3 10 Ta = 25C, when data is all 0. Ta = 25C Ta = 25C Notes: *1 Programming time and Erase time depend on data. *2 Programming time and Erase time do not include the data transfer time. *3 Minimum value when all characteristics after reprogramming are guaranteed (the characteristics are guaranteed while the reprogramming count is from one to the minimum reprogramming count). *4 Characteristics when the flash memory is rewritten within the minimum reprogramming count. Rev. 2.0, 06/04, page 742 of 980 21.3 Electrical Characteristics of HD64F3029FBL25 and HD64F3029TEBL25 Absolute Maximum Ratings 21.3.1 Table 21.21 lists the absolute maximum ratings. Table 21.21 Absolute Maximum Ratings Item Power supply voltage Input voltage (FWE)* Input voltage (port 7) Reference voltage Analog power supply voltage Analog input voltage Operating temperature Storage temperature 2 2 Symbol VCC* Vin Vin Vin VREF AVCC VAN Topr Tstg 1 Value -0.3 to +4.6 -0.3 to VCC +0.3 -0.3 to VCC +0.3 -0.3 to AVCC +0.3 -0.3 to AVCC +0.3 -0.3 to +4.6 -0.3 to AVCC +0.3 Unit V V V V V V V Input voltage (except for port 7)* C -20 to +75 3 (Standard characteristics specifications)* -55 to +125 C Caution: Permanent damage to the chip may result if absolute maximum ratings are exceeded. Notes: *1 Do not apply the power supply voltage to the VCL pin. Connect an external capacitor between this pin and GND. *2 12 V must not be applied to any pin, as this may cause permanent damage to the device. *3 The operating temperature range for flash memory programming/erasing is Ta = 0 to +75C (Standard characteristics specifications). Rev. 2.0, 06/04, page 743 of 980 21.3.2 DC Characteristics Table 21.22 lists the DC characteristics. Table 21.23 lists the permissible output currents. Table 21.22 DC Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VREF = 3.0 V to AVCC* , 1 VSS = AVSS = 0 V* , Ta =-20C to +75C (Standard characteristics specifications), [Programming/erasing conditions: Ta = 0C to +75C (Standard characteristics specifications)] Item Schmitt trigger Port A, input voltages P80 to P82 STBY, RES, NMI, MD2 to MD0, FWE EXTAL Port 7 Ports 1 to 6, P83, P84, P90 to P95, port B Input low voltage STBY, RES, FWE, MD2 to MD0 NMI, EXTAL, ports 1 to 7, P83, P84, P90 to P95, port B Output high voltage Output low voltage All output pins All output pins Ports 1, 2, and 5 Input leakage STBY, RES, current NMI, FWE, MD2 to MD0 Port 7 |Iin| VOH VOL VIL Symbol VT VT - + + - 1 Min VCC x 0.2 -- VCC x 0.9 Typ -- -- -- Max -- VCC x 0.7 -- VCC + 0.3 Unit V V V V Test Conditions VT - VT Input high voltage VIH VCC x 0.05 -- VCC x 0.7 VCC x 0.7 VCC x 0.7 -- -- -- VCC + 0.3 VCC + 0.3 V V AVCC + 0.3 V -0.3 -- VCC x 0.1 V -0.3 -- VCC x 0.2 V VCC - 0.5 VCC - 1.0 -- -- -- -- -- -- -- -- -- -- 0.4 1.0 1.0 V V V V A IOH = -200 A IOH = -1 mA IOL = 1.6 mA IOL = 5 mA Vin = 0.5 V to VCC - 0.5 V Vin = 0.5 V to AVCC - 0.5 V -- -- 1.0 A Rev. 2.0, 06/04, page 744 of 980 Item Three-state leakage current Input pull-up MOS current Input capacitance Ports 1 to 6, Ports 8 to B Ports 2, 4, and 5 FWE NMI All input pins except NMI Current 2 dissipation* Normal operation Sleep mode Module standby mode Flash memory programming/ 4 erasing* Analog power During A/D supply current conversion During A/D and D/A conversion Symbol |ITSI| Min -- Typ -- Max 1.0 Unit A Test Conditions Vin = 0.5 V to VCC - 0.5 V Vin = 0 V Vin = 0 V, f = fmin, Ta = 25C -Ip Cin 10 -- -- -- -- -- -- -- 20(3.3V) 17(3.3V) 16(3.3V) 30(3.3V) 300 80 50 15 38 35 34 48 A pF pF pF mA mA mA mA ICC* 3 -- -- -- -- f = 25 MHz f = 25 MHz f = 25 MHz f = 25 MHz (reference values) AICC -- -- 0.6 0.6 1.5 1.5 mA mA Rev. 2.0, 06/04, page 745 of 980 Item Reference current During A/D conversion During A/D and D/A conversion RAM standby voltage VCL output 5 voltage* Normal operation Symbol AICC Min -- -- Typ 0.25 1.2 -- 1.9 Max 0.8 3.0 -- 2.3 Unit mA mA V V Test Conditions VRAM VCL 3.0 1.5 VCC = 3.3 V, Ta = 25C Notes: *1 If the A/D converter is not used, do not leave the AVCC, VREF, and AVSS pins open. Connect AVCC and VREF to VCC, and connect AVSS to VSS. *2 Current dissipation values are for VIH min = VCC - 0.5 V and VIL max = 0.5 V with all output pins unloaded and the on-chip MOS pull-up transistors in the off state. *3 ICC max. (normal operation) = 11 (mA) + 0.13 (mA/(MHz x V)) x VCC x f ICC max. (sleep mode) = 11 (mA) + 0.11 (mA/(MHz x V)) x VCC x f ICC max. (sleep mode + module standby mode) = 11 (mA) + 0.10 (mA/(MHz x V)) x VCC x f The Typ values for power consumption are reference values. *4 Sum of current dissipation in normal operation and current dissipation in program/erase operations. *5 This value is applied when the external capacitor of 0.1 F is connected. This characteristic does not specify the permissible range of voltage input from the external circuit but specifies the voltage output by the LSI. Rev. 2.0, 06/04, page 746 of 980 Table 21.23 Permissible Output Currents Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V 3.6 V, VREF = 3.0 V to AVCC, VSS = AVSS = 0 V, Ta = -20C to +75C (Standard characteristics specifications) Item Permissible output low current (per pin) Permissible output low current (total) Ports 1, 2, and 5 Other output pins Total of 20 pins in Ports 1, 2, and 5 Total of all output pins, including the above Permissible output high current (per pin) Permissible output high current (total) All output pins Total of all output pins | -IOH | | -IOH | IOL Symbol IOL Min -- -- -- -- -- -- Typ -- -- -- -- -- -- Max 10 2.0 80 120 2.0 40 Unit mA mA mA mA mA mA Notes: 1. To protect chip reliability, do not exceed the output current values in table 21.23. 2. When directly driving a darlington pair or LED, always insert a current-limiting resistor in the output line, as shown in figures 21.7 and 21.8. H8/3029F-ZTAT 2 k Port Darlington pair Figure 21.7 Darlington Pair Drive Circuit (Example) Rev. 2.0, 06/04, page 747 of 980 H8/3029F-ZTAT 600 Ports 1, 2, 5 LED Figure 21.8 Sample LED Circuit Rev. 2.0, 06/04, page 748 of 980 21.3.3 AC Characteristics Clock timing parameters are listed in table 21.24, control signal timing parameters in table 21.25, and bus timing parameters in table 21.26. Timing parameters of the on-chip supporting modules are listed in table 21.27. Table 21.24 Clock Timing Condition: Ta = -20C to +75C (Standard characteristics specifications), VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VREF = 3.0 V to AVCC, VSS = AVSS = 0 V, fmax = 25 MHz Symbol tcyc tCL tCH tCr tCf tOSC1 Min 40 10 10 -- -- 20 7 Max 62.5 -- -- 10 10 -- -- Unit ns ns ns ns ns ms ms Figure 21.10 Figure 20.1 Test Conditions Figure 21.13 Item Clock cycle time Clock pulse low width Clock pulse high width Clock rise time Clock fall time Clock oscillator settling time at reset Clock oscillator settling tOSC2 time in software standby Table 21.25 Control Signal Timing Conditions: Ta = -20C to +75C (Standard characteristics specifications), VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VREF = 3.0 V to AVCC, VSS = AVSS = 0 V, fmax = 25 MHz Item RES setup time RES pulse width Mode programming setup time NMI, IRQ setup time NMI, IRQ hold time NMI, IRQ pulse width Symbol tRESS tRESW tMDS tNMIS tNMIH tNMIW Min 150 20 200 150 10 200 Max -- -- -- -- -- -- Unit ns tcyc ns ns ns ns Figure 21.12 Test Conditions Figure 21.11 Rev. 2.0, 06/04, page 749 of 980 Table 21.26 Bus Timing Conditions: Ta = -20C to +75C (Standard characteristics specifications), VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VREF = 3.0 V to AVCC, VSS = AVSS = 0 V, fmax = 25 MHz Item Address delay time Address hold time Read strobe delay time Address strobe delay time Write strobe delay time Strobe delay time Write strobe pulse width 1 Write strobe pulse width 2 Address setup time 1 Address setup time 2 Read data setup time Read data hold time Write data delay time Write data setup time 1 Write data setup time 2 Write data hold time Symbol tAD tAH tRSD tASD tWSD tSD tWSW1 tWSW2 tAS1 tAS2 tRDS tRDH tWDD tWDS1 tWDS2 tWDH Min -- 0.5 tcyc - 20 -- -- -- -- 1.0 tcyc - 25 1.5 tcyc - 25 0.5 tcyc - 20 1.0 tcyc - 20 25 0 -- 1.0 tcyc- 30 2.0 tcyc- 30 0.5 tcyc- 15 Max 25 -- 25 25 25 25 -- -- -- -- -- -- 35 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions Figure 21.13, Figure 21.14, Figure 21.16, Figure 21.17, Figure 21.19 Rev. 2.0, 06/04, page 750 of 980 Item Read data access time 1 Read data access time 2 Read data access time 3 Read data access time 4 Precharge time 1 Precharge time 2 Wait setup time Wait hold time Bus request setup time Bus acknowledge delay time 1 Bus acknowledge delay time 2 Bus-floating time RAS precharge time CAS precharge time Low address hold time RAS delay time 1 RAS delay time 2 CAS delay time 1 CAS delay time 2 WE delay time Symbol tACC1 tACC2 tACC3 tACC4 tPCH1 tPCH2 tWTS tWTH tBRQS tBACD1 tBACD2 tBZD tRP tCP tRAH tRAD1 tRAD2 tCASD1 tCASD2 tWCD Min -- -- -- -- 1.0 tcyc - 20 0.5 tcyc - 20 25 5 25 -- -- -- 1.5 tcyc - 25 0.5 tcyc - 15 0.5 tcyc - 15 -- -- -- -- -- Max 2.0 tcyc- 45 3.0 tcyc - 45 1.5 tcyc - 45 2.5 tcyc - 45 -- -- -- -- -- 30 30 30 -- -- -- 25 30 25 25 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions Figure 21.13, Figure 21.14, Figure 21.16, Figure 21.17 Figure 21.15 Figure 21.18 Figure 21.19, Figure 21.20 Rev. 2.0, 06/04, page 751 of 980 Item CAS pulse width 1 CAS pulse width 2 CAS pulse width 3 RAS access time Address access time CAS access time WE setup time WE hold time Write data setup time WE write data hold time CAS setup time 1 CAS setup time 2 CAS hold time RAS pulse width Signal rising time (all input pins except for EXTAL) Signal falling time (all input pins except for EXTAL) Symbol tCAS1 tCAS2 tCAS3 tRAC tAA tCAC tWCS tWCH tWDS tWDH tCSR1 tCSR2 tCHR tRAS tSR Min 1.5 tcyc - 20 1.0 tcyc - 20 1.0 tcyc - 20 -- -- -- 0.5 tcyc - 20 0.5 tcyc - 15 0.5 tcyc - 20 0.5 tcyc - 15 0.5 tcyc - 20 0.5 tcyc - 15 0.5 tcyc - 15 1.5 tcyc - 15 -- Max -- -- -- 2.5 tcyc - 40 2.0 tcyc - 50 1.5 tcyc - 50 -- -- -- -- -- -- -- -- 100 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions Figure 21.19 to Figure 21.21 Figure 21.30 tSF -- 100 ns Note: In order to secure the address hold time relative to the rise of the RD strobe, address update mode 2 should be used. For details see section 6.3.5, Address Output Method. Rev. 2.0, 06/04, page 752 of 980 Table 21.27 Timing of On-Chip Supporting Modules Conditions: Ta = -20C to +75C (Standard characteristics specifications), VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VREF = 3.0 V to AVCC, VSS = AVSS = 0 V, fmax = 25 MHz Module Item Ports and TPC Output data delay time Input data setup time Input data hold time 16-bit timer Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width 8-bit timer Single edge Both edges Symbol tPWD tPRS tPRH tTOCD tTICS tTCKS tTCKWH tTCKWL tTOCD tTICS tTCKS tTCKWH tTCKWL Min -- 50 50 -- 50 50 1.5 2.5 -- 50 50 1.5 2.5 Max 50 -- -- 50 -- -- -- -- 50 -- -- -- -- Unit ns ns ns ns ns ns tcyc tcyc ns ns ns tcyc tcyc Figure 21.24 Figure 21.23 Figure 21.24 Figure 21.23 Test Conditions Figure 21.22 Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width Single edge Both edges Rev. 2.0, 06/04, page 753 of 980 Module Item SCI Input clock cycle Symbol AsyntScyc chronous Synchronous tSCKr tSCKf tSCKW tTXD tRXS Min 4 6 -- -- 0.4 -- 100 Max -- -- 1.5 1.5 0.6 100 -- Unit tcyc tcyc tcyc tcyc tScyc ns ns Test Conditions Figure 21.25 Input clock rise time Input clock fall time Input clock pulse width Transmit data delay time Receive data setup time (synchronous) Receive data hold time (synchronous) DMAC Clock input Clock output Figure 21.26 tRXH 100 0 -- -- 25 10 -- -- 50 50 -- -- ns ns ns ns ns ns Figure 21.27, Figure 21.28 Figure 21.29 TEND delay time 1 tTED1 TEND delay time 2 tTED2 DREQ setup time DREQ hold time tDRQS tDRQH RL H8/3029F-ZTAT output pin C = 90 pF: Ports 4, 6, 8 A19 to A0, D15 to D8 C = 30 pF: Ports 9, A, B R L = 2.4 k R H = 12 k C RH Input/output timing measurement levels * Low: Vcc 0.2 V * High: Vcc 0.7 V Figure 21.9 Output Load Circuit Rev. 2.0, 06/04, page 754 of 980 21.3.4 A/D Conversion Characteristics Table 21.28 lists the A/D conversion characteristics. Table 21.28 A/D Conversion Characteristics Conditions: Ta = -20C to +75C (Standard characteristics specifications), VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VREF = 3.0 V to AVCC, VSS = AVSS = 0 V, fmax = 25 MHz Item ConverResolution sion time: Conversion time (single 134 states mode) Analog input capacitance Permissible signal-source impedance Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Item ConverResolution sion time*: Conversion time (single 70 states mode) Analog input capacitance Permissible signal-source impedance Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Note: * Min 10 5.36 -- -- -- -- -- -- -- Min 10 5.38 -- -- -- -- -- -- -- Typ 10 -- -- -- -- -- -- -- -- Typ 10 -- -- -- -- -- -- -- -- Max 10 -- 20 5 3.5 3.5 3.5 0.5 4.0 Max 10 -- 20 5 7.5 7.5 7.5 0.5 8.0 Unit bits s pF k LSB LSB LSB LSB LSB Unit bits s pF k LSB LSB LSB LSB LSB When using an operating frequency above f = 70 (state) /5.38 (s) = 13.0 (MHz), do not select 70-state conversion time. Rev. 2.0, 06/04, page 755 of 980 21.3.5 D/A Conversion Characteristics Table 21.29 lists the D/A conversion characteristics. Table 21.29 D/A Conversion Characteristics Conditions: Ta = -20C to +75C (Standard characteristics specifications), VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VREF = 3.0 V to AVCC, VSS = AVSS = 0 V, fmax = 25 MHz Item Resolution Conversion time (centering time) Absolute accuracy* Min 8 -- -- -- Note: * Typ 8 -- 2.0 -- Max 8 10 3.0 2.0 Unit bits s LSB LSB 20 pF capacitive load 2 M resistive load 4 M resistive load Test Conditions Except in software standby mode. Rev. 2.0, 06/04, page 756 of 980 21.3.6 Flash Memory Characteristics Table 21.30 lists the flash memory characteristics. Table 21.30 Flash Memory Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, Ta = 0C to +75C (operating temperature range for programming/erasing: Standard characteristics specifications) Item Programming time*1, *2, *4 Erase time*1, *2, *4 Symbol tP tE Min -- -- -- -- Programming time (total)*1, *2, *4 Erase time (total)*1, *2, *4 Programming and erase time (total)*1, *2, *4 Reprogramming count Data retention time* 4 Typ 3 80 500 1000 10 10 20 -- -- Max 30 800 5000 10000 30 30 60 -- -- Unit ms/128 bytes ms/4-kbyte block ms/32-kbyte block ms/64-kbyte block s/512 kbytes s/512 kbytes s/512 kbytes Times Year Test Conditions tP tE tPE NWEC tDRP -- -- -- 100*3 10 Ta = 25C, all "0" Ta = 25C Ta = 25C Notes: *1 Programming and erase time depend on the data size. *2 Programming and erase time and excluded the data transfer time. *3 It is the number of times of min. which guarantees all the characteristics after reprogramming. (A guarantee is the range of a 1-min. value.) *4 It is the characteristic when reprogramming is performed by specification within the limits including a min. value. Rev. 2.0, 06/04, page 757 of 980 21.4 Operational Timing This section shows timing diagrams. 21.4.1 Clock Timing Clock timing is shown as follows: * Oscillator settling timing Figure 21.10 shows the oscillator settling timing. VCC STBY tOSC1 RES tOSC1 Figure 21.10 Oscillator Settling Timing Rev. 2.0, 06/04, page 758 of 980 21.4.2 Control Signal Timing Control signal timing is shown as follows: * Reset input timing Figure 21.11 shows the reset input timing. * Interrupt input timing Figure 21.12 shows the interrupt input timing for NMI and IRQ5 to IRQ0. tRESS RES tMDS FWE MD2 to MD0 tRESW tRESS Figure 21.11 Reset Input Timing tNMIS NMI tNMIS IRQ E tNMIS IRQ L IRQ E : Edge-sensitive IRQ i IRQ L : Level-sensitive IRQ i (i = 0 to 5) tNMIW NMI IRQ j (j = 0 to 5) tNMIH tNMIH Figure 21.12 Interrupt Input Timing Rev. 2.0, 06/04, page 759 of 980 21.4.3 Bus Timing Bus timing is shown as follows: * Basic bus cycle: two-state access Figure 21.13 shows the timing of the external two-state access cycle. * Basic bus cycle: three-state access Figure 21.14 shows the timing of the external three-state access cycle. * Basic bus cycle: three-state access with one wait state Figure 21.15 shows the timing of the external three-state access cycle with one wait state inserted. Burst ROM access timing/burst cycle: two-state access Figure 21.16 shows the timing of the two-state burst cycle. Burst ROM access timing/burst cycle: three-state access Figure 21.17 shows the timing of the three-state burst cycle. Burst release mode timing Figure 21.18 shows the timing in bus release mode. Rev. 2.0, 06/04, page 760 of 980 T1 tcyc tCH tAD A23 to A0, CSn tCf tcyc tCr tCL T2 tPCH1 tASD AS tAS1 tASD RD (read) tAS1 tACC1 D15 to D0 (read) tPCH1 tASD HWR, LWR (write) tAS1 tWSW1 tWDS1 tSD tAH tRDS tRDH* tACC3 tRSD tPCH2 tACC3 tSD tAH tWDD D15 to D0 (write) tWDH Note: * Specification from the earliest negation timing of A23 to A0, +5n, and 4,. Figure 21.13 Basic Bus Cycle: two State Access Rev. 2.0, 06/04, page 761 of 980 T1 A23 to A0, CSn T2 T3 tACC4 AS tACC4 RD (read) tACC2 D15 to D0 (read) tWSD HWR, LWR (write) tAS2 tWDD D15 to D0 (write) tWDS2 tWSW2 tRDS Figure 21.14 Basic Bus Cycle: three State Access Rev. 2.0, 06/04, page 762 of 980 T1 A23 to A0, CSn AS T2 TW T3 RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tWTS WAIT tWTH tWTS tWTH Figure 21.15 Basic Bus Cycle: three State Access with One Wait State Rev. 2.0, 06/04, page 763 of 980 T1 tAD A23 to A3 CSn T2 T3 T1 T2 tAD A2 to A0 tASD tACC4 tSD tAH tASD tSD tAH AS tAS1 tASD tACC4 tAS1 tRSD RD tAS1 tACC2 tRDS tACC1 tRDS tRDH* D15 to D0 Note: * Specification from the earliest negation timing of A23 to A0, CSn, and RD. Figure 21.16 Burst ROM Access Timing: two State Access Rev. 2.0, 06/04, page 764 of 980 T1 tAD A23 to A3 CSn T2 T3 T1 T2 T3 tAD A2 to A0 tASD tACC4 tSD tAH tASD tSD tAH AS tAS1 tASD tACC4 tAS1 tRSD RD tAS1 tACC2 tRDS tACC2 tRDS tRDH* D15 to D0 Note: * Specification from the earliest negation timing of A23 to A0, +5n, and 4,. Figure 21.17 Burst ROM Access Timing: three State Access tBRQS BREQ tBACD2 tBACD1 BACK tBRQS A23 to A0, AS, RD, HWR, LWR tBZD tBZD Figure 21.18 Bus-Release Mode Timing Rev. 2.0, 06/04, page 765 of 980 21.4.4 DRAM Interface Bus Timing DRAM interface bus timing is shown as follows: * DRAM bus timing: read and write access Figure 21.19 shows the timing of the read and write access. * DRAM bus timing: CAS before RAS refresh Figure 21.20 shows the timing of the CAS before RAS refresh. * DRAM bus timing: self-refresh Figure 21.21 shows the timing of the self-refresh. Rev. 2.0, 06/04, page 766 of 980 Tp Tr TC1 TC2 tAD A23 to A0 tAD tAD tAS1 tRP CS5 to CS2 (RAS5 to RAS2) tRAD1 tRAH tRAD2 tASD UCAS, LCAS (read) tCAS1 tCASD2 tCP RD (WE) (read) High tRAC tRDS tRDH* tAA tCAC tCASD1 tCASD2 tCAS2 tCP tASD tWCD D15 to D0 (read) UCAS, LCAS (write) RD (WE) (write) tWCS tWDD D15 to D0 (write) tWDS tWCH tWDH RFSH High Note: * Specification from the earliest negation timing of RAS and CAS. Figure 21.19 DRAM Bus Timing (Read/Write) Rev. 2.0, 06/04, page 767 of 980 TRp TR1 TR2 tRAD1 tRP CS5 to CS2 (RAS5 to RAS2) tRAS tCASD1 tCSR1 UCAS, LCAS tCAS3 tCASD2 tCHR tRAD2 RD (WE) (high) tRAD1 tCSR1 tCHR tRAS tRAD2 RFSH Figure 21.20 DRAM Bus Timing (CAS Before RAS Refresh) Rev. 2.0, 06/04, page 768 of 980 tCSR2 CS5 to CS2 (RAS5 to RAS2) UCAS, LCAS RD (WE) (high) tCSR2 RFSH Figure 21.21 DRAM Bus Timing (Self-Refresh) 21.4.5 TPC and I/O Port Timing Figure 21.22 shows the TPC and I/O port input/output timing. T1 tPRS Port 1 to B (read) tPWD Port 1 to 6, 8 to B (write) tPRH T2 T3 Figure 21.22 TPC and I/O Port Input/Output Timing Rev. 2.0, 06/04, page 769 of 980 21.4.6 Timer Input/Output Timing 16-bit timer and 8-bit timer timing is shown below. * Timer input/output timing Figure 21.23 shows the timer input/output timing. * Timer external clock input timing Figure 21.24 shows the timer external clock input timing. tTOCD Output compare*1 tTICS Input capture*2 Notes: *1 TIOCA0 to TIOCA2, TIOCB0 to TIOCB2, TMO0, TMO2, TMIO1, TMIO3 *2 TIOCA0 to TIOCA2, TIOCB0 to TIOCB2, TMIO1, TMIO3 Figure 21.23 Timer Input/Output Timing tTCKS tTCKS TCLKA to TCLKD tTCKWL tTCKWH Figure 21.24 Timer External Clock Input Timing Rev. 2.0, 06/04, page 770 of 980 21.4.7 SCI Input/Output Timing SCI timing is shown as follows: * SCI input clock timing Figure 21.25 shows the SCI input clock timing. * SCI input/output timing (synchronous mode) Figure 21.26 shows the SCI input/output timing in synchronous mode. tSCKW SCK0 to SCK2 tScyc tSCKr tSCKf Figure 21.25 SCI Input Clock Timing tScyc SCK0, SCK1 tTXD TxD0 to TxD2 (transmit data) RxD0 to RxD2 (receive data) tRXS tRXH Figure 21.26 SCI Input/Output Timing in Synchronous Mode Rev. 2.0, 06/04, page 771 of 980 21.4.8 DMAC Timing DMAC timing is shown as follows. * DMAC TEND output timing for 2 state access Figure 21.27 shows the DMAC TEND output timing for two state access. * DMAC TEND output timing for 3 state access Figure 21.28 shows the DMAC TEND output timing for three state access. * DMAC DREQ input timing Figure 21.29 shows DMAC DREQ input timing. T1 tTED1 TEND tTED2 T2 Figure 21.27 DMAC TEND Output Timing for two State Access T1 tTED1 TEND tTED2 T2 T3 Figure 21.28 DMAC TEND Output Timing for three State Access tDRQS DREQ tDRQH Figure 21.29 DMAC DREQ Input Timing Rev. 2.0, 06/04, page 772 of 980 21.4.9 Input Signal Timing Figure 21.30 shows the rising and falling timing for input signals. All input pins except for the EXTAL pin tSR tSF Figure 21.30 Rising and Falling Timing for Input Signals Rev. 2.0, 06/04, page 773 of 980 Rev. 2.0, 06/04, page 774 of 980 Appendix A Instruction Set A.1 Instruction List Operand Notation Symbol Rd Rs Rn ERd ERs ERn (EAd) (EAs) PC SP CCR N Z V C disp + - x / ( ), < > Description General destination register General source register General register General destination register (address register or 32-bit register) General source register (address register or 32-bit register) General register (32-bit register) Destination operand Source operand Program counter Stack pointer Condition code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Displacement Transfer from the operand on the left to the operand on the right, or transition from the state on the left to the state on the right Addition of the operands on both sides Subtraction of the operand on the right from the operand on the left Multiplication of the operands on both sides Division of the operand on the left by the operand on the right Logical AND of the operands on both sides Logical OR of the operands on both sides Exclusive logical OR of the operands on both sides NOT (logical complement) Contents of operand Note: General registers include 8-bit registers (R0H to R7H and R0L to R7L) and 16-bit registers (R0 to R7 and E0 to E7). Rev. 2.0, 06/04, page 775 of 980 Condition Code Notation Symbol Description Changed according to execution result * 0 1 -- Undetermined (no guaranteed value) Cleared to 0 Set to 1 Not affected by execution of the instruction Varies depending on conditions, described in notes Rev. 2.0, 06/04, page 776 of 980 Table A.1 Instruction Set 1. Data transfer instructions Addressing Mode and Instruction Length (bytes) @-ERn/@ERn+ Operand Size No. of States*1 @(d, ERn) @aa Condition Code -- Mnemonic MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @ERs, Rd Operation #xx:8 Rd8 I HN Z V C B B B 2 2 2 4 ---- ---- ---- ---- 0-- 0-- 0-- 0-- 2 2 4 6 Rs8 Rd8 @ERs Rd8 @(d:16, ERs) Rd8 @(d:24, ERs) Rd8 2 @ERs Rd8 ERs32+1 ERs32 2 4 6 2 4 @aa:8 Rd8 @aa:16 Rd8 @aa:24 Rd8 Rs8 @ERd Rs8 @(d:16, ERd) Rs8 @(d:24, ERd) 2 ERd32-1 ERd32 Rs8 @ERd 2 4 6 Rs8 @aa:8 Rs8 @aa:16 Rs8 @aa:24 #xx:16 Rd16 MOV.B @(d:16, ERs), B Rd MOV.B @(d:24, ERs), B Rd MOV.B @ERs+, Rd B 8 ---- 0-- 10 ---- 0-- 6 MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B @aa:24, Rd MOV.B Rs, @ERd MOV.B Rs, @(d:16, ERd) MOV.B Rs, @(d:24, ERd) MOV.B Rs, @-ERd B B B B B ---- ---- ---- ---- ---- 0-- 0-- 0-- 0-- 0-- 4 6 8 4 6 B 8 ---- 0-- 10 B ---- 0-- 6 MOV.B Rs, @aa:8 MOV.B Rs, @aa:16 MOV.B Rs, @aa:24 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @ERs, Rd B B B W4 W W 2 2 4 ---- ---- ---- ---- ---- ---- ---- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 4 6 8 4 2 4 6 Rs16 Rd16 @ERs Rd16 @(d:16, ERs) Rd16 @(d:24, ERs) Rd16 2 @ERs Rd16 ERs32+2 @ERd32 4 @aa:16 Rd16 MOV.W @(d:16, ERs), W Rd MOV.W @(d:24, ERs), W Rd MOV.W @ERs+, Rd W 8 ---- 0-- 10 ---- 0-- 6 MOV.W @aa:16, Rd W ---- 0-- 6 Rev. 2.0, 06/04, page 777 of 980 Advanced @(d, PC) Normal @@aa @ERn #xx Rn Addressing Mode and Instruction Length (bytes) @-ERn/@ERn+ Operand Size No. of States*1 @(d, ERn) @aa Condition Code -- Mnemonic MOV.W @aa:24, Rd MOV.W Rs, @ERd MOV.W Rs, @(d:16, ERd) MOV.W Rs, @(d:24, ERd) MOV.W Rs, @-ERd Operation @aa:24 Rd16 Rs16 @ERd I HN Z V C W W W 2 4 6 ---- ---- ---- 0-- 0-- 0-- 8 4 6 Rs16 @(d:16, ERd) Rs16 @(d:24, ERd) 2 ERd32-2 ERd32 Rs16 @ERd 4 6 Rs16 @aa:16 Rs16 @aa:24 #xx:32 Rd32 W 8 ---- 0-- 10 W ---- 0-- 6 MOV.W Rs, @aa:16 MOV.W Rs, @aa:24 MOV.L #xx:32, Rd MOV.L ERs, ERd MOV.L @ERs, ERd MOV.L @(d:16, ERs), ERd MOV.L @(d:24, ERs), ERd MOV.L @ERs+, ERd W W L L L L 6 2 4 6 ---- ---- ---- ---- ---- 0-- 0-- 0-- 0-- 0-- 0-- 6 8 6 2 8 10 ERs32 ERd32 @ERs ERd32 @(d:16, ERs) ERd32 -- -- @(d:24, ERs) ERd32 -- -- 4 @ERs ERd32 ERs32+4 ERs32 6 8 @aa:16 ERd32 @aa:24 ERd32 ERs32 @ERd ---- L 10 0-- 14 L 0-- 10 MOV.L @aa:16, ERd MOV.L @aa:24, ERd MOV.L ERs, @ERd MOV.L ERs, @(d:16, ERd) MOV.L ERs, @(d:24, ERd) MOV.L ERs, @-ERd L L L L 4 6 ---- ---- ---- 0-- 0-- 0-- 0-- 10 12 8 10 ERs32 @(d:16, ERd) -- -- ERs32 @(d:24, ERd) -- -- 4 ERd32-4 ERd32 ERs32 @ERd 6 8 ERs32 @aa:16 ERs32 @aa:24 2 @SP Rn16 SP+2 SP 4 @SP ERn32 SP+4 SP ---- L 10 0-- 14 L 0-- 10 MOV.L ERs, @aa:16 MOV.L ERs, @aa:24 POP.W Rn L L W ---- ---- ---- 0-- 0-- 0-- 10 12 6 POP.L ERn L ---- 0-- 10 Rev. 2.0, 06/04, page 778 of 980 Advanced @(d, PC) Normal @@aa @ERn #xx Rn Addressing Mode and Instruction Length (bytes) No. of States*1 @-ERn/@ERn+ Operand Size @(d, ERn) @aa Condition Code Mnemonic PUSH.W Rn Operation I HN Z V C W 2 SP-2 SP Rn16 @SP 4 SP-4 SP ERn32 @SP 4 Cannot be used in the H8/3029 Cannot be used in the H8/3029 ---- 0-- 6 PUSH.L ERn L ---- 0-- 10 MOVFPE @aa:16, Rd MOVTPE Rs, @aa:16 B Cannot be used in the H8/3029 Cannot be used in the H8/3029 B 4 2. Arithmetic instructions Addressing Mode and Instruction Length (bytes) No. of States*1 @-ERn/@ERn+ Operand Size @(d, ERn) @aa Condition Code Mnemonic ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W #xx:16, Rd ADD.W Rs, Rd ADD.L #xx:32, ERd Operation Rd8+#xx:8 Rd8 I -- -- HN Z V C B B 2 2 2 2 4 2 6 Rd8+Rs8 Rd8 Rd16+#xx:16 Rd16 W4 W L 6 2 -- (1) -- (1) -- (2) Rd16+Rs16 Rd16 ERd32+#xx:32 ERd32 ADD.L ERs, ERd L 2 ERd32+ERs32 ERd32 Rd8+#xx:8 +C Rd8 -- (2) 2 ADDX.B #xx:8, Rd ADDX.B Rs, Rd ADDS.L #1, ERd ADDS.L #2, ERd ADDS.L #4, ERd INC.B Rd INC.W #1, Rd INC.W #2, Rd B B L L L B W W 2 2 2 2 2 2 2 2 -- -- (3) (3) 2 2 2 2 2 2 2 2 Rd8+Rs8 +C Rd8 ERd32+1 ERd32 ERd32+2 ERd32 ERd32+4 ERd32 Rd8+1 Rd8 Rd16+1 Rd16 Rd16+2 Rd16 ------------ ------------ ------------ ---- ---- ---- -- -- -- Rev. 2.0, 06/04, page 779 of 980 Advanced @(d, PC) Normal @@aa @ERn #xx Rn -- Advanced @(d, PC) Normal @@aa @ERn #xx Rn -- Addressing Mode and Instruction Length (bytes) @-ERn/@ERn+ Operand Size No. of States*1 @(d, ERn) @aa Condition Code -- Mnemonic INC.L #1, ERd INC.L #2, ERd DAA Rd Operation ERd32+1 ERd32 ERd32+2 ERd32 Rd8 decimal adjust Rd8 Rd8-Rs8 Rd8 Rd16-#xx:16 Rd16 I HN Z V C -- -- L L B 2 2 2 ---- ---- --* -- -- (1) -- (1) -- (2) 2 2 2 *-- SUB.B Rs, Rd SUB.W #xx:16, Rd SUB.W Rs, Rd SUB.L #xx:32, ERd B W4 W L 6 2 2 4 2 6 2 Rd16-Rs16 Rd16 ERd32-#xx:32 ERd32 SUB.L ERs, ERd L 2 ERd32-ERs32 ERd32 Rd8-#xx:8-C Rd8 -- (2) 2 SUBX.B #xx:8, Rd SUBX.B Rs, Rd SUBS.L #1, ERd SUBS.L #2, ERd SUBS.L #4, ERd DEC.B Rd DEC.W #1, Rd DEC.W #2, Rd DEC.L #1, ERd DEC.L #2, ERd DAS.Rd B B L L L B W W L L B 2 2 2 2 2 2 2 2 2 2 2 -- -- (3) (3) 2 2 2 2 2 2 2 2 2 2 2 Rd8-Rs8-C Rd8 ERd32-1 ERd32 ERd32-2 ERd32 ERd32-4 ERd32 Rd8-1 Rd8 Rd16-1 Rd16 Rd16-2 Rd16 ERd32-1 ERd32 ERd32-2 ERd32 Rd8 decimal adjust Rd8 ------------ ------------ ------------ ---- ---- ---- ---- ---- --* -- -- -- -- -- *-- MULXU. B Rs, Rd B 2 Rd8 x Rs8 Rd16 ------------ (unsigned multiplication) Rd16 x Rs16 ERd32 -- -- -- -- -- -- (unsigned multiplication) Rd8 x Rs8 Rd16 (signed multiplication) Rd16 x Rs16 ERd32 (signed multiplication) Rd16 / Rs8 Rd16 (RdH: remainder, RdL: quotient) (unsigned division) ---- ---- 14 MULXU. W Rs, ERd W 2 22 MULXS. B Rs, Rd B 4 16 MULXS. W Rs, ERd W 4 ---- ---- 24 DIVXU. B Rs, Rd B 2 -- -- (6) (7) -- -- 14 Rev. 2.0, 06/04, page 780 of 980 Advanced @(d, PC) Normal @@aa @ERn #xx Rn Addressing Mode and Instruction Length (bytes) @-ERn/@ERn+ Operand Size No. of States*1 @(d, ERn) @aa Condition Code -- Mnemonic DIVXU. W Rs, ERd Operation I HN Z V C W 2 ERd32 / Rs16 ERd32 -- -- (6) (7) -- -- (Ed: remainder, Rd: quotient) (unsigned division) Rd16 / Rs8 Rd16 (RdH: remainder, RdL: quotient) (signed division) -- -- (8) (7) -- -- 22 DIVXS. B Rs, Rd B 4 16 DIVXS. W Rs, ERd W 4 ERd32 / Rs16 ERd32 -- -- (8) (7) -- -- (Ed: remainder, Rd: quotient) (signed division) Rd8-#xx:8 -- -- -- (1) -- (1) -- (2) -- (2) -- -- -- ---- 0 0-- 24 CMP.B #xx:8, Rd CMP.B Rs, Rd CMP.W #xx:16, Rd CMP.W Rs, Rd CMP.L #xx:32, ERd CMP.L ERs, ERd NEG.B Rd NEG.W Rd NEG.L ERd EXTU.W Rd B B 2 2 2 2 4 2 6 2 2 2 2 2 Rd8-Rs8 Rd16-#xx:16 W4 W L L B W L W 6 2 2 2 2 2 2 Rd16-Rs16 ERd32-#xx:32 ERd32-ERs32 0-Rd8 Rd8 0-Rd16 Rd16 0-ERd32 ERd32 0 ( EXTU.L ERd L 2 ---- 0 0-- 2 EXTS.W Rd W 2 ( 0 2 EXTS.L ERd L 2 0-- 2 Rev. 2.0, 06/04, page 781 of 980 Advanced @(d, PC) Normal @@aa @ERn #xx Rn 3. Logic instructions Addressing Mode and Instruction Length (bytes) @-ERn/@ERn+ Operand Size No. of States*1 @(d, ERn) @(d, PC) @@aa @aa Condition Code -- Mnemonic AND.B #xx:8, Rd AND.B Rs, Rd AND.W #xx:16, Rd AND.W Rs, Rd AND.L #xx:32, ERd AND.L ERs, ERd OR.B #xx:8, Rd OR.B Rs, Rd OR.W #xx:16, Rd OR.W Rs, Rd OR.L #xx:32, ERd OR.L ERs, ERd XOR.B #xx:8, Rd XOR.B Rs, Rd XOR.W #xx:16, Rd XOR.W Rs, Rd XOR.L #xx:32, ERd XOR.L ERs, ERd NOT.B Rd NOT.W Rd NOT.L ERd Operation Rd8#xx:8 Rd8 I HN Z V C B B 2 2 ---- ---- ---- ---- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 2 2 4 2 6 4 2 2 4 2 6 4 2 2 4 2 6 4 2 2 2 Rd8Rs8 Rd8 Rd16#xx:16 Rd16 W4 W L L B B W4 W L L B B W4 W L L B W L 6 4 2 2 2 2 2 2 6 4 2 2 2 6 4 2 Rd16Rs16 Rd16 ERd32#xx:32 ERd32 -- -- ERd32ERs32 ERd32 -- -- Rd8#xx:8 Rd8 Rd8Rs8 Rd8 Rd16#xx:16 Rd16 Rd16Rs16 Rd16 ---- ---- ---- ---- ERd32#xx:32 ERd32 -- -- ERd32ERs32 ERd32 -- -- Rd8#xx:8 Rd8 Rd8Rs8 Rd8 Rd16#xx:16 Rd16 Rd16Rs16 Rd16 ---- ---- ---- ---- ERd32#xx:32 ERd32 -- -- ERd32ERs32 ERd32 -- -- Rd8 Rd8 Rd16 Rd16 Rd32 Rd32 ---- ---- ---- Rev. 2.0, 06/04, page 782 of 980 Advanced Normal @ERn #xx Rn 4. Shift instructions Addressing Mode and Instruction Length (bytes) @-ERn/@ERn+ Operand Size No. of States*1 @(d, ERn) @(d, PC) @@aa @aa Condition Code -- Mnemonic SHAL.B Rd SHAL.W Rd SHAL.L ERd SHAR.B Rd SHAR.W Rd SHAR.L ERd SHLL.B Rd SHLL.W Rd SHLL.L ERd SHLR.B Rd SHLR.W Rd SHLR.L ERd ROTXL.B Rd ROTXL.W Rd ROTXL.L ERd ROTXR.B Rd ROTXR.W Rd ROTXR.L ERd ROTL.B Rd ROTL.W Rd ROTL.L ERd ROTR.B Rd ROTR.W Rd ROTR.L ERd Operation I HN Z V C B W L B W L B W L B W L B W L B W L B W L B W L 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ---- 2 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 C MSB LSB 0 ---- ---- ---- C MSB LSB ---- ---- ---- C MSB LSB 0 ---- ---- ---- 0 MSB LSB C ---- ---- ---- C MSB LSB ---- ---- ---- C MSB LSB ---- ---- ---- C MSB LSB ---- ---- ---- C MSB LSB ---- ---- Rev. 2.0, 06/04, page 783 of 980 Advanced Normal @ERn #xx Rn 5. Bit manipulation instructions Addressing Mode and Instruction Length (bytes) @-ERn/@ERn+ Operand Size No. of States*1 @(d, ERn) @aa Condition Code -- Mnemonic BSET #xx:3, Rd BSET #xx:3, @ERd BSET #xx:3, @aa:8 BSET Rn, Rd BSET Rn, @ERd BSET Rn, @aa:8 BCLR #xx:3, Rd BCLR #xx:3, @ERd BCLR #xx:3, @aa:8 BCLR Rn, Rd BCLR Rn, @ERd BCLR Rn, @aa:8 BNOT #xx:3, Rd Operation (#xx:3 of Rd8) 1 I HN Z V C B B B B B B B B B B B B B 2 4 4 2 4 4 2 4 4 2 4 4 2 ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ 2 8 8 2 8 8 2 8 8 2 8 8 2 (#xx:3 of @ERd) 1 (#xx:3 of @aa:8) 1 (Rn8 of Rd8) 1 (Rn8 of @ERd) 1 (Rn8 of @aa:8) 1 (#xx:3 of Rd8) 0 (#xx:3 of @ERd) 0 (#xx:3 of @aa:8) 0 (Rn8 of Rd8) 0 (Rn8 of @ERd) 0 (Rn8 of @aa:8) 0 (#xx:3 of Rd8) (#xx:3 of Rd8) BNOT #xx:3, @ERd B 4 (#xx:3 of @ERd) (#xx:3 of @ERd) 4 (#xx:3 of @aa:8) (#xx:3 of @aa:8) (Rn8 of Rd8) (Rn8 of Rd8) ------------ 8 BNOT #xx:3, @aa:8 B ------------ 8 BNOT Rn, Rd B 2 ------------ 2 BNOT Rn, @ERd B 4 (Rn8 of @ERd) (Rn8 of @ERd) 4 (Rn8 of @aa:8) (Rn8 of @aa:8) (#xx:3 of Rd8) Z ------------ 8 BNOT Rn, @aa:8 B ------------ 8 BTST #xx:3, Rd BTST #xx:3, @ERd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @ERd BTST Rn, @aa:8 BLD #xx:3, Rd B B B B B B B 2 4 4 2 4 4 2 ------ ------ ------ ------ ------ ------ ---- ---- ---- ---- ---- ---- 2 6 6 2 6 6 2 (#xx:3 of @ERd) Z (#xx:3 of @aa:8) Z (Rn8 of @Rd8) Z (Rn8 of @ERd) Z (Rn8 of @aa:8) Z (#xx:3 of Rd8) C ---------- Rev. 2.0, 06/04, page 784 of 980 Advanced @(d, PC) Normal @@aa @ERn #xx Rn Addressing Mode and Instruction Length (bytes) @-ERn/@ERn+ Operand Size No. of States*1 @(d, ERn) @aa Condition Code -- Mnemonic BLD #xx:3, @ERd BLD #xx:3, @aa:8 BILD #xx:3, Rd BILD #xx:3, @ERd BILD #xx:3, @aa:8 BST #xx:3, Rd BST #xx:3, @ERd BST #xx:3, @aa:8 BIST #xx:3, Rd BIST #xx:3, @ERd BIST #xx:3, @aa:8 BAND #xx:3, Rd BAND #xx:3, @ERd BAND #xx:3, @aa:8 BIAND #xx:3, Rd Operation (#xx:3 of @ERd) C I HN Z V C B B B B B B B B B B B B B B B 2 2 2 2 2 4 4 ---------- ---------- ---------- ---------- ---------- ------------ ------------ ------------ ------------ ------------ ------------ ---------- ---------- ---------- ---------- 6 6 2 6 6 2 8 8 2 8 8 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 (#xx:3 of @aa:8) C (#xx:3 of Rd8) C 4 4 (#xx:3 of @ERd) C (#xx:3 of @aa:8) C C (#xx:3 of Rd8) 4 4 C (#xx:3 of @ERd24) C (#xx:3 of @aa:8) C (#xx:3 of Rd8) 4 4 C (#xx:3 of @ERd24) C (#xx:3 of @aa:8) C(#xx:3 of Rd8) C 4 4 C(#xx:3 of @ERd24) C C(#xx:3 of @aa:8) C C (#xx:3 of Rd8) C BIAND #xx:3, @ERd B BIAND #xx:3, @aa:8 B BOR #xx:3, Rd BOR #xx:3, @ERd BOR #xx:3, @aa:8 BIOR #xx:3, Rd BIOR #xx:3, @ERd BIOR #xx:3, @aa:8 BXOR #xx:3, Rd BXOR #xx:3, @ERd BXOR #xx:3, @aa:8 BIXOR #xx:3, Rd B B B B B B B B B B 2 2 2 2 4 4 C (#xx:3 of @ERd24) C -- -- -- -- -- C (#xx:3 of @aa:8) C C(#xx:3 of Rd8) C ---------- ---------- ---------- ---------- ---------- 4 4 C(#xx:3 of @ERd24) C C(#xx:3 of @aa:8) C C (#xx:3 of Rd8) C 4 4 C (#xx:3 of @ERd24) C -- -- -- -- -- C (#xx:3 of @aa:8) C C(#xx:3 of Rd8) C ---------- ---------- ---------- ---------- ---------- ---------- ---------- 4 4 C(#xx:3 of @ERd24) C C(#xx:3 of @aa:8) C C (#xx:3 of Rd8) C BIXOR #xx:3, @ERd B BIXOR #xx:3, @aa:8 B 4 4 C (#xx:3 of @ERd24) C C (#xx:3 of @aa:8) C Rev. 2.0, 06/04, page 785 of 980 Advanced @(d, PC) Normal @@aa @ERn #xx Rn 6. Branching instructions Addressing Mode and Instruction Length (bytes) @-ERn/@ERn+ Operand Size No. of States*1 @(d, ERn) Mnemonic BRA d:8 (BT d:8) BRA d:16 (BT d:16) BRN d:8 (BF d:8) BRN d:16 (BF d:16) BHI d:8 BHI d:16 BLS d:8 BLS d:16 BCC d:8 (BHS d:8) Branch Operation Condition If condition Always is true then PC PC+d else Never next; CZ=0 #xx Rn @aa Condition Code I HN Z V C -- -- -- -- -- -- -- -- -- 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 ------------ ------------ ------------ ------------ ------------ ------------ 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 CZ=1 ------------ ------------ C=0 ------------ ------------ BCC d:16 (BHS d:16) -- BCS d:8 (BLO d:8) -- C=1 ------------ ------------ BCS d:16 (BLO d:16) -- BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 BVC d:16 BVS d:8 BVS d:16 BPL d:8 BPL d:16 BMI d:8 BMI d:16 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 BGT d:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Z=0 ------------ ------------ Z=1 ------------ ------------ V=0 ------------ ------------ V=1 ------------ ------------ N=0 ------------ ------------ N=1 ------------ ------------ NV = 0 ------------ ------------ NV = 1 ------------ ------------ Z (NV) =0 ------------ ------------ Rev. 2.0, 06/04, page 786 of 980 Advanced @(d, PC) Normal @ERn @@aa -- Addressing Mode and Instruction Length (bytes) No. of States*1 @-ERn/@ERn+ Operand Size @(d, ERn) Mnemonic BLE d:8 BLE d:16 Branch Operation Condition If condition Z (NV) = 1 is true then PC PC+d else next; PC ERn @aa Condition Code I HN Z V C -- -- 2 4 ------------ ------------ 4 6 JMP @ERn JMP @aa:24 JMP @@aa:8 BSR d:8 -- -- -- -- 2 4 2 2 ------------ ------------ ------------ ------------ 8 6 4 6 10 8 PC aa:24 PC @aa:8 PC @-SP PC PC+d:8 PC @-SP PC PC+d:16 PC @-SP PC @ERn BSR d:16 -- 4 ------------ 8 10 JSR @ERn -- 2 ------------ 6 JSR @aa:24 -- 4 PC @-SP PC @aa:24 2 PC @-SP PC @aa:8 2 PC @SP+ ------------ 8 10 JSR @@aa:8 -- ------------ 8 12 RTS -- ------------ 8 10 Rev. 2.0, 06/04, page 787 of 980 Advanced 8 @(d, PC) Normal @@aa @ERn #xx Rn -- 7. System control instructions Addressing Mode and Instruction Length (bytes) @-ERn/@ERn+ Operand Size No. of States*1 @(d, ERn) @aa Condition Code -- Mnemonic TRAPA #x:2 Operation PC @-SP CCR @-SP I HN Z V C -- 2 1 -- -- -- -- -- 14 16 RTE -- 10 SLEEP -- Transition to powerdown -- -- -- -- -- -- state 2 2 4 6 #xx:8 CCR Rs8 CCR @ERs CCR @(d:16, ERs) CCR @(d:24, ERs) CCR 4 @ERs CCR ERs32+2 ERs32 6 8 2 4 6 @aa:16 CCR @aa:24 CCR CCR Rd8 CCR @ERd CCR @(d:16, ERd) CCR @(d:24, ERd) 4 ERd32-2 ERd32 CCR @ERd 6 8 2 2 2 CCR @aa:16 CCR @aa:24 CCR#xx:8 CCR CCR#xx:8 CCR CCR#xx:8 CCR 2 PC PC+2 ------------ ------------ ------------ ------------ 2 LDC #xx:8, CCR LDC Rs, CCR LDC @ERs, CCR LDC @(d:16, ERs), CCR LDC @(d:24, ERs), CCR LDC @ERs+, CCR B B W W 2 2 6 8 W 10 12 W 8 LDC @aa:16, CCR LDC @aa:24, CCR STC CCR, Rd STC CCR, @ERd STC CCR, @(d:16, ERd) STC CCR, @(d:24, ERd) STC CCR, @-ERd W W B W W 8 10 2 6 8 W 10 ------------ 12 W ------------ 8 STC CCR, @aa:16 STC CCR, @aa:24 ANDC #xx:8, CCR ORC #xx:8, CCR XORC #xx:8, CCR NOP W W B B B -- ------------ ------------ 8 10 2 2 2 2 Rev. 2.0, 06/04, page 788 of 980 Advanced @(d, PC) Normal @@aa @ERn #xx Rn 8. Block transfer instructions Addressing Mode and Instruction Length (bytes) No. of States*1 @-ERn/@ERn+ Operand Size @(d, ERn) #xx Rn @aa Condition Code Mnemonic EEPMOV. B Operation I HN Z V C -- 4 if R4L - 0 -- -- -- -- -- -- 8+ repeat @R5 @R6 4n*2 R5+1 R5 R6+1 R6 R4L-1 R4L until R4L=0 else next; 4 if R4 - 0 repeat @R5 @R6 R5+1 R5 R6+1 R6 R4-1 R4 until R4=0 else next; ------------ 8+ 4n*2 EEPMOV. W -- Notes: *1 The number of states is the number of states required for execution when the instruction and its operands are located in on-chip memory. For other cases see section A.3. *2 n is the value set in register R4L or R4. (1) Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0. (2) Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0. (3) Retains its previous value when the result is zero; otherwise cleared to 0. (4) Set to 1 when the adjustment produces a carry; otherwise retains its previous value. (5) The number of states required for execution of an instruction that transfers data in synchronization with the E clock is variable. (6) Set to 1 when the divisor is negative; otherwise cleared to 0. (7) Set to 1 when the divisor is zero; otherwise cleared to 0. (8) Set to 1 when the quotient is negative; otherwise cleared to 0. Rev. 2.0, 06/04, page 789 of 980 Advanced @(d, PC) Normal @ERn @@aa -- A.2 A.2 Operation Code Map (1) Instruction when most significant bit of BH is 0. Instruction when most significant bit of BH is 1. 4 ORC ADD SUB Table A.2 Table A.2 (2) (2) CMP MOV OR.B XOR.B AND.B Table A.2 (2) XORC ANDC LDC Table A.2 Table A.2 (2) (2) 5 6 7 8 9 A B C D E ADDX SUBX F Table A.2 (2) Table A.2 (2) Table A.2 Instruction code: 1st byte 2nd byte AH AL BH BL 2 LDC 3 AL AH 0 1 0 NOP Table A.2 (2) STC Rev. 2.0, 06/04, page 790 of 980 MOV.B 1 Table A.2 Table A.2 Table A.2 Table A.2 (2) (2) (2) (2) Operation Code Maps 2 Operation Code Map (1) 3 BLS BVS JMP MOV MOV BIOR ADD ADDX CMP SUBX OR XOR AND MOV BIXOR BIAND BILD Table A.2 Table A.2 EEPMOV (2) (2) Table A.2 (3) DIVXU BST OR BTST BOR BXOR BAND BIST BLD XOR AND RTS BSR RTE TRAPA Table A.2 (2) BCC BCS BNE BNQ BVC BPL BMI BGE BSR BLT BGT JSR BLE 4 BRA BRN BHI 5 MULXU DIVXU MULXU 6 BSET BNOT BCLR 7 8 9 A B C D E F Table A.2 Instruction code: 1st byte 2nd byte AH AL BH BL 2 LDC/STC SLEEP ADD INC ADDS INC INC INC 3 4 5 6 7 8 9 A B C D E F Table A.2 (3) BH AH AL Table A.2 Table A.2 (3) (3) 0 1 01 MOV 0A INC 0B ADDS Operation Code Map (2) 0F SHLL SHAL SHAR ROTL ROTR EXTU EXTU NEG SHLR ROTXL ROTXR NOT DAA MOV SHAL SHAR ROTL ROTR NEG EXTS EXTS 10 SHLL 11 SHLR 12 ROTXL 13 ROTXR 17 NOT 1A DEC DEC DEC SUBS SUB DEC DEC 1B SUBS 1F BHI BLS SUB SUB OR OR CMP CMP BCC BCS XOR XOR DAS BNE AND AND BEQ BVC BVS BPL BMI CMP BGE BLT BGT BLE 58 BRA BRN 79 MOV ADD Rev. 2.0, 06/04, page 791 of 980 7A MOV ADD Table A.2 Instruction code: 1st byte 2nd byte 3rd byte 4th byte AH AL BH BL CH CL DH DL Instruction when most significant bit of DH is 0. Instruction when most significant bit of DH is 1. CL 2 3 4 5 6 7 8 9 A B C D E F AH ALBH BLCH LDC STC STC MULXS DIVXS OR BTST BOR BTST BIOR BCLR BIST BCLR BTST BOR BTST BIOR BCLR BIST BCLR BIXOR BIAND BILD BST BXOR BAND BLD BIXOR BIAND BILD BST BXOR BAND BLD XOR AND LDC 0 1 Rev. 2.0, 06/04, page 792 of 980 LDC STC LDC STC 01406 Operation Code Map (3) 01C05 MULXS 01D05 DIVIXS 01F06 7Cr06 * 1 7Cr07 * 1 7Dr06 * 1 BSET BNOT 7Dr07 * 1 BSET BNOT 7Eaa6 * 2 7Eaa7 * 2 7Faa6 * 2 BSET BNOT 7Faa7 * 2 BSET BNOT Notes: *1 r is the register designation field. *2 aa is the absolute address field. A.3 Number of States Required for Execution The tables in this section can be used to calculate the number of states required for instruction execution by the H8/300H CPU. Table A.4 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. Table A.3 indicates the number of states required per cycle according to the bus size. The number of states required for execution of an instruction can be calculated from these two tables as follows: Number of states = I * SI + J * SJ + K * SK + L * SL + M * SM + N * SN Examples of Calculation of Number of States Required for Execution Examples: Advanced mode, stack located in external address space, on-chip supporting modules accessed with 8-bit bus width, external devices accessed in three states with one wait state and 16-bit bus width. BSET #0, @FFFFC7:8 From table A.4, I = L = 2 and J = K = M = N = 0 From table A.3, SI = 4 and SL = 3 Number of states = 2 x 4 + 2 x 3 = 14 JSR @@30 From table A.4, I = J = K = 2 and L = M = N = 0 From table A.3, SI = SJ = SK = 4 Number of states = 2 x 4 + 2 x 4 + 2 x 4 = 24 Rev. 2.0, 06/04, page 793 of 980 Table A.3 Number of States per Cycle Access Conditions On-Chip Supporting Module External Device 8-Bit Bus 2-State Access 4 3-State Access 6 + 2m 16-Bit Bus 2-State Access 2 3-State Access 3+m Execution State (Cycle) Instruction fetch Stack operation Byte data access Word data access Internal operation SI SK SL SM On-Chip 8-Bit Memory Bus 2 6 16-Bit Bus 3 Branch address read SJ 3 6 2 4 3+m 6 + 2m SN 1 Legend m: Number of wait states inserted into external device access Rev. 2.0, 06/04, page 794 of 980 Table A.4 Number of Cycles per Instruction Byte Data Word Data Internal Stack Instruction Branch Operation Access Addr. Read Operation Access Fetch N M L K J I 1 1 2 1 3 1 1 1 1 1 1 2 1 3 2 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 Instruction Mnemonic ADD ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W #xx:16, Rd ADD.W Rs, Rd ADD.L #xx:32, ERd ADD.L ERs, ERd ADDS #1/2/4, ERd ADDX #xx:8, Rd ADDX Rs, Rd AND.B #xx:8, Rd AND.B Rs, Rd AND.W #xx:16, Rd AND.W Rs, Rd AND.L #xx:32, ERd AND.L ERs, ERd ANDC #xx:8, CCR BAND #xx:3, Rd BAND #xx:3, @ERd BAND #xx:3, @aa:8 BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8 ADDS ADDX AND ANDC BAND Bcc Rev. 2.0, 06/04, page 795 of 980 Instruction Mnemonic Bcc BRA d:16 (BT d:16) BRN d:16 (BF d:16) BHI d:16 BLS d:16 BCC d:16 (BHS d:16) BCS d:16 (BLO d:16) BNE d:16 BEQ d:16 BVC d:16 BVS d:16 BPL d:16 BMI d:16 BGE d:16 BLT d:16 BGT d:16 BLE d:16 BCLR #xx:3, Rd BCLR #xx:3, @ERd BCLR #xx:3, @aa:8 BCLR Rn, Rd BCLR Rn, @ERd BCLR Rn, @aa:8 BIAND #xx:3, Rd BIAND #xx:3, @ERd BIAND #xx:3, @aa:8 BILD #xx:3, Rd BILD #xx:3, @ERd BILD #xx:3, @aa:8 BIOR #xx:8, Rd BIOR #xx:8, @ERd BIOR #xx:8, @aa:8 BIST #xx:3, Rd BIST #xx:3, @ERd BIST #xx:3, @aa:8 BIXOR #xx:3, Rd BIXOR #xx:3, @ERd BIXOR #xx:3, @aa:8 BLD #xx:3, Rd BLD #xx:3, @ERd BLD #xx:3, @aa:8 Byte Data Word Data Internal Stack Instruction Branch Operation Access Addr. Read Operation Access Fetch N M L K J I 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 2 2 2 2 1 1 1 1 1 1 2 2 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 BCLR BIAND BILD BIOR BIST BIXOR BLD Rev. 2.0, 06/04, page 796 of 980 Instruction Mnemonic BNOT BNOT #xx:3, Rd BNOT #xx:3, @ERd BNOT #xx:3, @aa:8 BNOT Rn, Rd BNOT Rn, @ERd BNOT Rn, @aa:8 BOR #xx:3, Rd BOR #xx:3, @ERd BOR #xx:3, @aa:8 BSET #xx:3, Rd BSET #xx:3, @ERd BSET #xx:3, @aa:8 BSET Rn, Rd BSET Rn, @ERd BSET Rn, @aa:8 BSR d:8 Normal Byte Data Word Data Internal Stack Instruction Branch Operation Access Addr. Read Operation Access Fetch N M L K J I 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 2 1 2 1 2 2 2 1 1 1 1 1 1 2 2 2 2 2 2 1 1 2 2 2 2 BOR BSET BSR Advanced 2 BSR d:16 Normal 2 Advanced 2 BST BST #xx:3, Rd BST #xx:3, @ERd BST #xx:3, @aa:8 BTST #xx:3, Rd BTST #xx:3, @ERd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @ERd BTST Rn, @aa:8 BXOR #xx:3, Rd BXOR #xx:3, @ERd BXOR #xx:3, @aa:8 CMP.B #xx:8, Rd CMP.B Rs, Rd CMP.W #xx:16, Rd CMP.W Rs, Rd CMP.L #xx:32, ERd CMP.L ERs, ERd DAA Rd DAS Rd 1 2 2 1 2 2 1 2 2 1 2 2 1 1 2 1 3 1 1 1 BTST BXOR CMP DAA DAS Rev. 2.0, 06/04, page 797 of 980 Instruction Mnemonic DEC DEC.B Rd DEC.W #1/2, Rd DEC.L #1/2, ERd DIVXS.B Rs, Rd DIVXS.W Rs, ERd DIVXU.B Rs, Rd DIVXU.W Rs, ERd EEPMOV.B EEPMOV.W EXTS.W Rd EXTS.L ERd EXTU.W Rd EXTU.L ERd INC.B Rd INC.W #1/2, Rd INC.L #1/2, ERd JMP @ERn JMP @aa:24 JMP @@aa:8 Normal Byte Data Word Data Internal Stack Instruction Branch Operation Access Addr. Read Operation Access Fetch N M L K J I 1 1 1 2 2 1 1 2 2 1 1 1 1 1 1 1 2 2 2 1 2 1 2 1 2 1 2 1 2 2 2 2 2 2 2n + 2*1 2n + 2*1 12 20 12 20 DIVXS DIVXU EEPMOV EXTS EXTU INC JMP Advanced 2 JSR JSR @ERn Normal 2 Advanced 2 JSR @aa:24 Normal 2 Advanced 2 JSR @@aa:8 Normal 2 Advanced 2 LDC LDC #xx:8, CCR LDC Rs, CCR LDC @ERs, CCR LDC @(d:16, ERs), CCR LDC @(d:24, ERs), CCR LDC @ERs+, CCR LDC @aa:16, CCR LDC @aa:24, CCR 1 1 2 3 5 2 3 4 1 1 1 1 1 1 2 Rev. 2.0, 06/04, page 798 of 980 Instruction Mnemonic MOV MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @ERs, Rd MOV.B @(d:16, ERs), Rd MOV.B @(d:24, ERs), Rd MOV.B @ERs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B @aa:24, Rd MOV.B Rs, @ERd MOV.B Rs, @(d:16, ERd) MOV.B Rs, @(d:24, ERd) MOV.B Rs, @-ERd MOV.B Rs, @aa:8 MOV.B Rs, @aa:16 MOV.B Rs, @aa:24 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @ERs, Rd MOV.W @(d:16, ERs), Rd MOV.W @(d:24, ERs), Rd MOV.W @ERs+, Rd MOV.W @aa:16, Rd MOV.W @aa:24, Rd MOV.W Rs, @ERd MOV.W Rs, @(d:16, ERd) MOV.W Rs, @(d:24, ERd) MOV.W Rs, @-ERd MOV.W Rs, @aa:16 MOV.W Rs, @aa:24 MOV.L #xx:32, ERd MOV.L ERs, ERd MOV.L @ERs, ERd MOV.L @(d:16, ERs), ERd MOV.L @(d:24, ERs), ERd MOV.L @ERs+, ERd MOV.L @aa:16, ERd MOV.L @aa:24, ERd MOV.L ERs, @ERd MOV.L ERs, @(d:16, ERd) MOV.L ERs, @(d:24, ERd) MOV.L ERs, @-ERd MOV.L ERs, @aa:16 MOV.L ERs, @aa:24 Byte Data Word Data Internal Stack Instruction Branch Operation Access Addr. Read Operation Access Fetch N M L K J I 1 1 1 2 4 1 1 2 3 1 2 4 1 1 2 3 2 1 1 2 4 1 2 3 1 2 4 1 2 3 3 1 2 3 5 2 3 4 2 3 5 2 3 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Rev. 2.0, 06/04, page 799 of 980 Instruction Mnemonic MOVFPE MOVTPE MULXS MULXU NEG Byte Data Word Data Internal Stack Instruction Branch Operation Access Addr. Read Operation Access Fetch N M L K J I 1 1 12 20 12 20 MOVFPE @aa:16, Rd*2 2 MOVTPE Rs, @aa:16* 2 MULXS.B Rs, Rd MULXS.W Rs, ERd MULXU.B Rs, Rd MULXU.W Rs, ERd NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT.B Rd NOT.W Rd NOT.L ERd OR.B #xx:8, Rd OR.B Rs, Rd OR.W #xx:16, Rd OR.W Rs, Rd OR.L #xx:32, ERd OR.L ERs, ERd ORC #xx:8, CCR POP.W Rn POP.L ERn PUSH.W Rn PUSH.L ERn ROTL.B Rd ROTL.W Rd ROTL.L ERd ROTR.B Rd ROTR.W Rd ROTR.L ERd ROTXL.B Rd ROTXL.W Rd ROTXL.L ERd ROTXR.B Rd ROTXR.W Rd ROTXR.L ERd RTE 2 2 1 1 1 1 1 1 1 1 1 1 1 2 1 3 2 1 1 2 1 2 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 NOP NOT OR ORC POP PUSH ROTL 1 2 1 2 2 2 2 2 ROTR ROTXL ROTXR RTE 2 Rev. 2.0, 06/04, page 800 of 980 Instruction Mnemonic RTS SHAL RTS SHAL.B Rd SHAL.W Rd SHAL.L ERd SHAR.B Rd SHAR.W Rd SHAR.L ERd SHLL.B Rd SHLL.W Rd SHLL.L ERd SHLR.B Rd SHLR.W Rd SHLR.L ERd SLEEP Normal Byte Data Word Data Internal Stack Instruction Branch Operation Access Addr. Read Operation Access Fetch N M L K J I 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 Advanced 2 SHAR SHLL SHLR SLEEP STC 1 STC CCR, Rd 2 STC CCR, @ERd STC CCR, @(d:16, ERd) 3 STC CCR, @(d:24, ERd) 5 2 STC CCR, @-ERd 3 STC CCR, @aa:16 4 STC CCR, @aa:24 SUB.B Rs, Rd SUB.W #xx:16, Rd SUB.W Rs, Rd SUB.L #xx:32, ERd SUB.L ERs, ERd SUBS #1/2/4, ERd SUBX #xx:8, Rd SUBX Rs, Rd TRAPA #x:2 Normal XOR.B #xx:8, Rd XOR.B Rs, Rd XOR.W #xx:16, Rd XOR.W Rs, Rd XOR.L #xx:32, ERd XOR.L ERs, ERd XORC #xx:8, CCR 1 2 1 3 1 1 1 1 2 1 1 2 1 3 2 1 1 2 2 2 2 SUB SUBS SUBX TRAPA XOR 4 4 Advanced 2 XORC Notes: *1 n is the value set in register R4L or R4. The source and destination are accessed n + 1 times each. *2 Not available in the H8/3029. Rev. 2.0, 06/04, page 801 of 980 Appendix B Internal I/O Registers B.1 Address (Low) H'EE000 H'EE001 H'EE002 H'EE003 H'EE004 H'EE005 H'EE006 H'EE007 H'EE008 H'EE009 H'EE00A H'EE00B H'EE00C H'EE00D H'EE00E H'EE00F H'EE010 H'EE011 H'EE012 H'EE013 H'EE014 H'EE015 H'EE016 H'EE017 H'EE018 H'EE019 H'EE01A H'EE01B H'EE01C H'EE01D H'EE01E H'EE01F Addresses (EMC = 1) Data Register Bus Width Bit 7 Name P1DDR P2DDR P3DDR P4DDR P5DDR P6DDR -- P8DDR P9DDR PADDR PBDDR -- -- -- -- -- -- MDCR SYSCR BRCR ISCR IER ISR -- IPRA IPRB 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 P11DDR P21DDR P31DDR P41DDR P51DDR P61DDR -- P81DDR P91DDR PA1DDR PB1DDR -- -- -- -- -- -- MDS1 SSOE -- IRQ1SC IRQ1E IRQ1F -- IPRA1 IPRB1 -- DIV1 Bit 0 P10DDR P20DDR P30DDR P40DDR P50DDR P60DDR -- P80DDR P90DDR PA0DDR PB0DDR -- -- -- -- -- -- MDS0 RAME BRLE IRQ0SC IRQ0E IRQ0F -- IPRA0 -- DASTE DIV0 D/A converter System control System control Bus controller Interrupt controller Port 8 Port 9 Port A Port B Module Name Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR -- -- -- -- -- -- -- -- P53DDR P52DDR -- -- P66DDR P65DDR P64DDR P63DDR P62DDR -- -- -- -- -- -- P84DDR P83DDR P82DDR P95DDR P94DDR P93DDR P92DDR PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR -- -- -- -- -- -- -- SSBY A23E -- -- -- -- IPRA7 IPRB7 -- -- PSTOP -- -- -- -- -- -- -- STS2 A22E -- -- -- -- IPRA6 IPRB6 -- -- -- -- -- -- -- -- -- -- STS1 A21E -- -- -- -- -- -- -- STS0 A20E -- -- -- -- -- -- -- UE -- -- -- -- -- -- -- MDS2 NMIEG -- IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ5E IRQ5F -- IPRA5 IPRB5 -- -- -- IRQ4E IRQ4F -- IPRA4 -- -- -- -- IRQ3E IRQ3F -- IPRA3 IPRB3 -- -- -- IRQ2E IRQ2F -- IPRA2 IPRB2 -- -- DASTCR 8 DIVCR 8 MSTCRH 8 MSTCRL 8 ADRCR CSCR 8 8 MSTPH2 MSTPH1 MSTPH0 MSTPL0 MSTPL7 -- -- CS7E -- CS6E MSTPL5 MSTPL4 MSTPL3 MSTPL2 -- -- CS5E -- CS4E -- -- -- -- -- -- ADRCTL Bus controller -- Rev. 2.0, 06/04, page 802 of 980 Address (Low) H'EE020 H'EE021 H'EE022 H'EE023 H'EE024 H'EE025 H'EE026 H'EE027 H'EE028 H'EE029 H'EE02A H'EE02B H'EE02C H'EE02D H'EE02E H'EE02F H'EE030 H'EE031 H'EE032 H'EE033 H'EE034 H'EE035 H'EE036 H'EE037 H'EE038 H'EE039 H'EE03A H'EE03B H'EE03C H'EE03D H'EE03E H'EE03F Data Register Bus Width Bit 7 Name ABWCR ASTCR WCRH WCRL BCR -- DRCRA DRCRB 8 8 8 8 8 8 8 ABW7 AST7 W71 W31 ICIS1 -- DRAS2 MXC1 CMF Bit Names Bit 6 ABW6 AST6 W70 W30 ICIS0 -- DRAS1 MXC0 CMIE Bit 5 ABW5 AST5 W61 W21 Bit 4 ABW4 AST4 W60 W20 Bit 3 ABW3 AST3 W51 W11 Bit 2 ABW2 AST2 W50 W10 Bit 1 ABW1 AST1 W41 W01 RDEA -- SRFMD RCW -- Bit 0 ABW0 AST0 W40 W00 WAITE -- RFSHE RLW -- Module Name Bus controller BROME BRSTS1 BRSTS0 -- -- DRAS0 CSEL CKS2 -- -- -- BE -- RDM TPC -- RCYCE -- CKS1 CKS0 DRAM Interface RTMCSR 8 RTCNT RTCOR -- -- -- -- -- -- -- -- -- -- -- -- -- 8 8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Reserved area (access prohibited) P2PCR -- P4PCR P5PCR 8 P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR -- -- -- -- -- -- P21PCR -- P41PCR P51PCR P20PCR -- P40PCR P50PCR Port 2 8 8 P47PCR P46PCR P45PCR P44PCR P43PCR P42PCR -- -- -- -- P53PCR P52PCR Port 4 Port 5 Rev. 2.0, 06/04, page 803 of 980 Address (Low) H'EE040 H'EE041 H'EE042 H'EE043 H'EE044 H'EE045 H'EE046 H'EE047 H'EE048 H'EE049 H'EE04A H'EE04B H'EE04C H'EE04D H'EE04E H'EE04F H'EE050 H'EE051 H'EE052 H'EE053 H'EE054 H'EE055 H'EE056 H'EE057 H'EE058 H'EE059 H'EE05A H'EE05B H'EE05C H'EE05D H'EE05E H'EE05F Data Register Bus Width Bit 7 Name -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit Names Bit 6 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Module Name Rev. 2.0, 06/04, page 804 of 980 Address (Low) H'EE060 H'EE061 H'EE062 H'EE063 H'EE064 H'EE065 H'EE066 H'EE067 H'EE068 H'EE069 H'EE06A H'EE06B H'EE06C H'EE06D H'EE06E H'EE06F H'EE070 H'EE071 H'EE072 H'EE073 H'EE074 H'EE075 H'EE076 H'EE077 Data Register Bus Width Bit 7 Name -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit Names Bit 6 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Module Name Reserved area (access prohibited) RAMCR 8 -- -- -- -- RAMS RAM2 RAM1 RAM0 Flash memory* H'EE078 H'EE079 H'EE07A H'EE07B H'EE07C H'EE07D H'EE07E H'EE07F -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Rev. 2.0, 06/04, page 805 of 980 Address (Low) H'EE080 H'EE081 H'EE082 H'EE083 H'EE084 H'EE085 H'EE086 H'EE087 H'EE088 H'EE089 H'EE08A H'EE08B H'EE08C H'EE08D H'EE08E H'EE08F H'EE090 H'EE091 H'EE092 H'EE093 H'EE094 H'EE095 H'EE096 H'EE097 H'EE098 H'EE099 H'EE09A H'EE09B H'EE09C H'EE09D H'EE09E H'EE09F Register Name -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data Bus Width Bit 7 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit Names Bit 6 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Module Name Rev. 2.0, 06/04, page 806 of 980 Address (Low) H'EE0A0 H'EE0A1 H'EE0A2 H'EE0A3 H'EE0A4 H'EE0A5 H'EE0A6 H'EE0A7 H'EE0A8 H'EE0A9 H'EE0AA H'EE0AB H'EE0AC H'EE0AD H'EE0AE H'EE0AF H'EE0B0 H'EE0B1 H'EE0B2 H'EE0B3 H'EE0B4 H'EE0B5 H'EE0B6 H'EE0B7 Register Name -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- FCCS FPCS FECS Data Bus Width Bit 7 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 8 8 8 FWE -- -- Bit Names Bit 6 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- FLER -- -- Bit 3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SCO PPVS EPVB Module Name Flash memory* Reserved area (access prohibited) FKEY FMATS FTDAR FVACR 8 8 8 8 K7 MS7 TDER K6 MS6 TDA6 K5 MS5 TDA5 -- K4 MS4 TDA4 -- K3 MS3 TDA3 K2 MS2 TDA2 K1 MS1 TDA1 K0 MS0 TDA0 FVCHG -- E FVSEL FVSEL FVSEL FVSEL 3 2 1 0 H'EE0B8 H'EE0B9 H'EE0BA H'EE0BB H'EE0BC H'EE0BD H'EE0BE H'EE0BF FVADRR FVADRE FVADRH FVADRL 8 8 8 8 Reserved area (access prohibited) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Rev. 2.0, 06/04, page 807 of 980 Address (Low) H'FFF20 H'FFF21 H'FFF22 H'FFF23 H'FFF24 H'FFF25 H'FFF26 H'FFF27 Register Name MAR0AR MAR0AE MAR0AH MAR0AL Data Bus Width Bit 7 8 8 8 8 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name DMAC channel 0A ETCR0AH 8 ETCR0AL 8 IOAR0A DTCR0A 8 8 DTE DTE DTSZ DTSZ DTID SAID RPE SAIDE DTIE DTIE DTS2 DTS1 DTS0 Short address mode DTS2A DTS1A DTS0A Full address mode DMAC channel 0B H'FFF28 H'FFF29 H'FFF2A H'FFF2B H'FFF2C H'FFF2D H'FFF2E H'FFF2F MAR0BR MAR0BE MAR0BH MAR0BL 8 8 8 8 ETCR0BH 8 ETCR0BL 8 IOAR0B DTCR0B 8 8 DTE DTME DTSZ -- DTID DAID RPE DAIDE DTIE TMS DTS2 DTS1 DTS0 Short address mode DTS2B DTS1B DTS0B Full address mode DMAC channel 1A H'FFF30 H'FFF31 H'FFF32 H'FFF33 H'FFF34 H'FFF35 H'FFF36 H'FFF37 MAR1AR MAR1AE MAR1AH MAR1AL 8 8 8 8 ETCR1AH 8 ETCR1AL 8 IOAR1A DTCR1A 8 8 DTE DTE DTSZ DTSZ DTID SAID RPE SAIDE DTIE DTIE DTS2 DTS1 DTS0 Short address mode DTS2A DTS1A DTS0A Full address mode DMAC channel 1B H'FFF38 H'FFF39 H'FFF3A H'FFF3B H'FFF3C H'FFF3D H'FFF3E H'FFF3F MAR1BR MAR1BE MAR1BH MAR1BL 8 8 8 8 ETCR1BH 8 ETCR1BL 8 IOAR1B DTCR1B 8 8 DTE DTME DTSZ -- DTID DAID RPE DAIDE DTIE TMS DTS2 DTS1 DTS0 Short address mode DTS2B DTS1B DTS0B Full address mode Rev. 2.0, 06/04, page 808 of 980 Address (Low) H'FFF40 H'FFF41 H'FFF42 H'FFF43 H'FFF44 H'FFF45 H'FFF46 H'FFF47 H'FFF48 H'FFF49 H'FFF4A H'FFF4B H'FFF4C H'FFF4D H'FFF4E H'FFF4F H'FFF50 H'FFF51 H'FFF52 H'FFF53 H'FFF54 H'FFF55 H'FFF56 H'FFF57 H'FFF58 H'FFF59 H'FFF5A H'FFF5B H'FFF5C H'FFF5D H'FFF5E H'FFF5F Data Register Bus Width Bit 7 Name Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Reserved area (access prohibited) Reserved area (access prohibited) Rev. 2.0, 06/04, page 809 of 980 Address (Low) H'FFF60 H'FFF61 H'FFF62 H'FFF63 H'FFF64 H'FFF65 H'FFF66 H'FFF67 H'FFF68 H'FFF69 H'FFF6A Data Register Bus Width Bit 7 Name TSTR TSNC TMDR TOLR TISRA TISRB TISRC -- 16TCR0 TIOR0 8 8 8 8 8 8 8 8 8 -- -- -- -- -- -- -- -- -- -- Bit Names Bit 6 -- -- MDF -- IMIEA2 IMIEB2 OVIE2 -- CCLR1 IOB2 Bit 5 -- -- FDIR TOB2 IMIEA1 IMIEB1 OVIE1 -- CCLR0 IOB1 Bit 4 -- -- -- TOA2 IMIEA0 IMIEB0 OVIE0 -- CKEG1 IOB0 Bit 3 -- -- -- TOB1 -- -- -- -- CKEG0 -- Bit 2 STR2 SYNC2 PWM2 TOA1 IMFA2 IMFB2 OVF2 -- TPSC2 IOA2 Bit 1 STR1 SYNC1 PWM1 TOB0 IMFA1 IMFB1 OVF1 -- TPSC1 IOA1 Bit 0 STR0 SYNC0 PWM0 TOA0 IMFA0 IMFB0 OVF0 -- TPSC0 IOA0 Module Name 16-bit timer all channels 16-bit timer channel 0 16TCNT0 16 H H'FFF6B 16TCNT0 L H'FFF6C H'FFF6D H'FFF6E H'FFF6F H'FFF70 H'FFF71 H'FFF72 GRA0H GRA0L GRB0H GRB0L 16TCR1 TIOR1 16 16 8 8 -- -- CCLR1 IOB2 CCLR0 IOB1 CKEG1 IOB0 CKEG0 -- TPSC2 IOA2 TPSC1 IOA1 TPSC0 IOA0 16-bit timer channel 1 16TCNT1 16 H H'FFF73 16TCNT1 L H'FFF74 H'FFF75 H'FFF76 H'FFF77 H'FFF78 H'FFF79 H'FFF7A GRA1H GRA1L GRB1H GRB1L 16TCR2 TIOR2 16 16 8 8 -- -- CCLR1 IOB2 CCLR0 IOB1 CKEG1 IOB0 CKEG0 -- TPSC2 IOA2 TPSC1 IOA1 TPSC0 IOA0 16-bit timer channel 2 16TCNT2 16 H H'FFF7B 16TCNT2 L H'FFF7C H'FFF7D H'FFF7E H'FFF7F GRA2H GRA2L GRB2H GRB2L 16 16 Rev. 2.0, 06/04, page 810 of 980 Address (Low) H'FFF80 H'FFF81 H'FFF82 H'FFF83 H'FFF84 H'FFF85 H'FFF86 H'FFF87 H'FFF88 H'FFF89 Data Register Bus Width Bit 7 Name 8TCR0 8TCR1 8TCSR0 8TCSR1 TCORA0 TCORA1 TCORB0 TCORB1 8TCNT0 8TCNT1 8 8 8 8 8 8 8 8 8 8 -- -- 8 8 -- 8 8 8 8 8 8 8 8 8 8 8 -- -- 8 8 8 DAOE1 -- WRST CMIEB CMIEB CMFB CMFB OVF CMIEB CMIEB CMFB CMFB Bit Names Bit 6 CMIEA CMIEA CMFA CMFA Bit 5 OVIE OVIE OVF OVF Bit 4 CCLR1 CCLR1 ADTE ICE Bit 3 CCLR0 CCLR0 OIS3 OIS3 Bit 2 CKS2 CKS2 OIS2 OIS2 Bit 1 CKS1 CKS1 OS1 OS1 Bit 0 CKS0 CKS0 OS0 OS0 Module Name 8-bit timer channels 0 and 1 H'FFF8A -- H'FFF8B -- H'FFF8C TCSR* H'FFF8D TCNT* H'FFF8E -- H'FFF8F RSTCSR * H'FFF90 H'FFF91 H'FFF92 H'FFF93 H'FFF94 H'FFF95 H'FFF96 H'FFF97 H'FFF98 H'FFF99 8TCR2 8TCR3 8TCSR2 8TCSR3 TCORA2 TCORA3 TCORB2 TCORB3 8TCNT2 8TCNT3 -- -- WT/IT -- -- TME -- -- -- -- -- -- -- -- CKS2 -- -- CKS1 -- -- CKS0 WDT -- -- CMIEA CMIEA CMFA CMFA -- -- OVIE OVIE OVF OVF -- -- CCLR1 CCLR1 -- ICE -- -- CCLR0 CCLR0 OIS3 OIS3 -- -- CKS2 CKS2 OIS2 OIS2 -- -- CKS1 CKS1 OS1 OS1 -- -- CKS0 CKS0 OS0 OS0 8-bit timer channels 2 and 3 H'FFF9A -- H'FFF9B -- H'FFF9C DADR0 H'FFF9D DADR1 H'FFF9E DACR H'FFF9F -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- D/A converter DAOE0 -- DAE -- -- -- -- -- -- -- -- -- -- -- Rev. 2.0, 06/04, page 811 of 980 Data Address Register Bus Width Bit 7 (Low) Name H'FFFA0 TPMR H'FFFA1 TPCR H'FFFA2 NDERB H'FFFA3 NDERA H'FFFA4 NDRB* H'FFFA5 NDRA* H'FFFA6 NDRB* H'FFFA7 NDRA* H'FFFA8 -- H'FFFA9 -- H'FFFAA -- H'FFFAB -- H'FFFAC -- H'FFFAD -- H'FFFAE -- H'FFFAF -- H'FFFB0 SMR H'FFFB1 BRR H'FFFB2 SCR H'FFFB3 TDR H'FFFB4 SSR H'FFFB5 RDR H'FFFB6 SCMR H'FFFB8 SMR H'FFFB9 BRR H'FFFBA SCR H'FFFBB TDR H'FFFBC SSR H'FFFBD RDR H'FFFBE SCMR 8 8 8 8 8 8 8 8 8 8 8 8 8 8 -- TDRE TIE -- C/A TDRE TIE 8 8 8 8 8 8 8 8 -- Bit Names Bit 6 -- Bit 5 -- Bit 4 -- Bit 3 G3NOV Bit 2 G2NOV Bit 1 G1NOV Bit 0 G0NOV NDER8 NDER0 NDR8 -- NDR0 -- -- NDR8 -- NDR0 -- -- -- -- -- -- -- -- CKS0 CKE0 MPBT SMIF CKS0 CKE0 MPBT SMIF Module Name TPC G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER7 NDR15 NDR15 NDR7 NDR7 -- -- -- -- -- -- -- -- -- -- -- -- C/A NDER6 NDR14 NDR14 NDR6 NDR6 -- -- -- -- -- -- -- -- -- -- -- -- CHR RIE RDRF -- CHR RIE RDRF -- NDER5 NDR13 NDR13 NDR5 NDR5 -- -- -- -- -- -- -- -- -- -- -- -- PE TE ORER -- PE TE ORER -- NDER4 NDR12 NDR12 NDR4 NDR4 -- -- -- -- -- -- -- -- -- -- -- -- O/E RE NDER3 NDR11 -- NDR3 -- -- NDR11 -- NDR3 -- -- -- -- -- -- -- -- STOP MPIE NDER2 NDR10 -- NDR2 -- -- NDR10 -- NDR2 -- -- -- -- -- -- -- -- MP TEIE TEND SINV MP TEIE TEND SINV NDER1 NDR9 -- NDR1 -- -- NDR9 -- NDR1 -- -- -- -- -- -- -- -- CKS1 CKE1 MPB -- CKS1 CKE1 MPB -- SCI channel 0 FER/ERS PER -- O/E RE SDIR STOP MPIE H'FFFB7 Reserved area (access prohibited) SCI channel 1 FER/ERS PER -- SDIR H'FFFBF Reserved area (access prohibited) Rev. 2.0, 06/04, page 812 of 980 Address (Low) H'FFFC0 H'FFFC1 H'FFFC2 H'FFFC3 H'FFFC4 H'FFFC5 H'FFFC6 H'FFFC7 H'FFFC8 H'FFFC9 H'FFFCA H'FFFCB H'FFFCC H'FFFCD H'FFFCE H'FFFCF H'FFFD0 H'FFFD1 H'FFFD2 H'FFFD3 H'FFFD4 H'FFFD5 H'FFFD6 H'FFFD7 H'FFFD8 H'FFFD9 H'FFFDA H'FFFDB H'FFFDC H'FFFDD H'FFFDE H'FFFDF Data Register Bus Width Bit 7 Name SMR BRR SCR TDR SSR RDR SCMR 8 8 8 8 8 8 8 -- TDRE TIE C/A Bit Names Bit 6 CHR Bit 5 PE Bit 4 O/E Bit 3 STOP Bit 2 MP Bit 1 CKS1 Bit 0 CKS0 Module Name SCI channel 2 RIE TE RE MPIE TEIE CKE1 CKE0 RDRF ORER FER/ER S PER TEND MPB MPBT -- -- -- SDIR SINV -- SMIF Reserved area (access prohibited) -- -- -- -- -- -- -- -- P1DR P2DR P3DR P4DR P5DR P6DR P7DR P8DR P9DR PADR PBDR -- -- -- -- -- 8 8 8 8 8 8 8 8 8 8 8 -- -- -- -- -- -- -- -- P17 P27 P37 P47 -- P67 P77 -- -- PA7 PB7 -- -- -- -- -- -- -- -- -- -- -- -- -- P16 P26 P36 P46 -- P66 P76 -- -- PA6 PB6 -- -- -- -- -- -- -- -- -- -- -- -- -- P15 P25 P35 P45 -- P65 P75 -- P95 PA5 PB5 -- -- -- -- -- -- -- -- -- -- -- -- -- P14 P24 P34 P44 -- P64 P74 P84 P94 PA4 PB4 -- -- -- -- -- -- -- -- -- -- -- -- -- P13 P23 P33 P43 P53 P63 P73 P83 P93 PA3 PB3 -- -- -- -- -- -- -- -- -- -- -- -- -- P12 P22 P32 P42 P52 P62 P72 P82 P92 PA2 PB2 -- -- -- -- -- -- -- -- -- -- -- -- -- P11 P21 P31 P41 P51 P61 P71 P81 P91 PA1 PB1 -- -- -- -- -- -- -- -- -- -- -- -- -- P10 P20 P30 P40 P50 P60 P70 P80 P90 PA0 PB0 -- -- -- -- -- Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port B Rev. 2.0, 06/04, page 813 of 980 Address (Low) H'FFFE0 H'FFFE1 H'FFFE2 H'FFFE3 H'FFFE4 H'FFFE5 H'FFFE6 H'FFFE7 H'FFFE8 H'FFFE9 Data Register Bus Width Bit 7 Name ADDRAH 8 ADDRAL 8 ADDRBH 8 ADDRBL 8 ADDRCH 8 ADDRCL 8 ADDRDH 8 ADDRDL 8 ADCSR ADCR 8 8 AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 ADF TRGE Bit Names Bit 6 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 ADIE -- Bit 5 AD7 -- AD7 -- AD7 -- AD7 -- ADST -- Bit 4 AD6 -- AD6 -- AD6 -- AD6 -- SCAN -- Bit 3 AD5 -- AD5 -- AD5 -- AD5 -- CKS -- Bit 2 AD4 -- AD4 -- AD4 -- AD4 -- CH2 -- Bit 1 AD3 -- AD3 -- AD3 -- AD3 -- CH1 -- Bit 0 AD2 -- AD2 -- AD2 -- AD2 -- CH0 -- Module Name A/D converter Note: * For write access to TCSR, TCNT, and RSTCSR, see section 12.2.4, Notes on Register Access. The address depends on the output trigger setting. Legend WDT: Watchdog timer TPC: Programmable timing pattern controller SCI: Serial communication interface Rev. 2.0, 06/04, page 814 of 980 B.2 Address (Low) H'EE000 H'EE001 H'EE002 H'EE003 H'EE004 H'EE005 H'EE006 H'EE007 H'EE008 H'EE009 H'EE00A H'EE00B H'EE00C H'EE00D H'EE00E H'EE00F H'EE010 H'EE011 H'EE012 H'EE013 H'EE014 H'EE015 H'EE016 H'EE017 H'EE018 H'EE019 H'EE01A H'EE01B H'EE01C H'EE01D H'EE01E H'EE01F Addresses (EMC = 0) Data Register Bus Width Bit 7 Name P1DDR P2DDR P3DDR P4DDR P5DDR P6DDR -- P8DDR P9DDR PADDR PBDDR -- -- -- -- -- -- MDCR SYSCR BRCR ISCR IER ISR -- IPRA IPRB 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 P11DDR P21DDR P31DDR P41DDR P51DDR P61DDR -- P81DDR P91DDR PA1DDR PB1DDR -- -- -- -- -- -- MDS1 SSOE -- IRQ1SC IRQ1E IRQ1F -- IPRA1 IPRB1 -- DIV1 Bit 0 P10DDR P20DDR P30DDR P40DDR P50DDR P60DDR -- P80DDR P90DDR PA0DDR PB0DDR -- -- -- -- -- -- MDS0 RAME BRLE IRQ0SC IRQ0E IRQ0F -- IPRA0 -- DASTE DIV0 D/A converter System control System control Bus controller Interrupt controller Port 8 Port 9 Port A Port B Module Name Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR -- -- -- -- -- -- -- -- P53DDR P52DDR -- -- P66DDR P65DDR P64DDR P63DDR P62DDR -- -- -- -- -- -- P84DDR P83DDR P82DDR P95DDR P94DDR P93DDR P92DDR PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR -- -- -- -- -- -- -- SSBY A23E -- -- -- -- IPRA7 IPRB7 -- -- PSTOP -- -- -- -- -- -- -- STS2 A22E -- -- -- -- IPRA6 IPRB6 -- -- -- -- -- -- -- -- -- -- STS1 A21E -- -- -- -- -- -- -- STS0 A20E -- -- -- -- -- -- -- UE -- -- -- -- -- -- -- MDS2 NMIEG -- IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ5E IRQ5F -- IPRA5 IPRB5 -- -- -- IRQ4E IRQ4F -- IPRA4 -- -- -- -- IRQ3E IRQ3F -- IPRA3 IPRB3 -- -- -- IRQ2E IRQ2F -- IPRA2 IPRB2 -- -- DASTCR 8 DIVCR 8 MSTCRH 8 MSTCRL 8 ADRCR CSCR 8 8 MSTPH2 MSTPH1 MSTPH0 MSTPL0 MSTPL7 -- -- CS7E -- CS6E MSTPL5 MSTPL4 MSTPL3 MSTPL2 -- -- CS5E -- CS4E -- -- -- -- -- -- ADRCTL Bus controller -- Rev. 2.0, 06/04, page 815 of 980 B.2 Addresses (cont) Data Register Bus Width Bit 7 Name ABWCR ASTCR WCRH WCRL BCR -- DRCRA DRCRB 8 8 8 8 8 8 8 ABW7 AST7 W71 W31 ICIS1 -- DRAS2 MXC1 CMF Bit Names Bit 6 ABW6 AST6 W70 W30 ICIS0 -- DRAS1 MXC0 CMIE Bit 5 ABW5 AST5 W61 W21 Bit 4 ABW4 AST4 W60 W20 Bit 3 ABW3 AST3 W51 W11 Bit 2 ABW2 AST2 W50 W10 Bit 1 ABW1 AST1 W41 W01 RDEA -- SRFMD RCW -- Bit 0 ABW0 AST0 W40 W00 WAITE -- RFSHE RLW -- DRAM Interface Address (Low) H'EE020 H'EE021 H'EE022 H'EE023 H'EE024 H'EE025 H'EE026 H'EE027 H'EE028 H'EE029 H'EE02A H'EE02B H'EE02C H'EE02D H'EE02E H'EE02F H'EE030 H'EE031 H'EE032 H'EE033 H'EE034 H'EE035 H'EE036 H'EE037 H'EE038 H'EE039 H'EE03A H'EE03B H'EE03C H'EE03D H'EE03E H'EE03F Module Name Bus controller BROME BRSTS1 BRSTS0 -- -- DRAS0 CSEL CKS2 -- -- -- BE -- RDM TPC -- RCYCE -- CKS1 CKS0 RTMCSR 8 RTCNT RTCOR -- -- -- -- -- -- -- -- -- -- -- -- -- 8 8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Reserved area (access prohibited) P2PCR -- P4PCR P5PCR 8 P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR -- -- -- -- -- -- P21PCR -- P41PCR P51PCR P20PCR -- P40PCR P50PCR Port 2 8 8 P47PCR P46PCR P45PCR P44PCR P43PCR P42PCR -- -- -- -- P53PCR P52PCR Port 4 Port 5 Rev. 2.0, 06/04, page 816 of 980 B.2 Addresses (cont) Data Register Bus Width Bit 7 Name -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit Names Bit 6 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Address (Low) H'EE040 H'EE041 H'EE042 H'EE043 H'EE044 H'EE045 H'EE046 H'EE047 H'EE048 H'EE049 H'EE04A H'EE04B H'EE04C H'EE04D H'EE04E H'EE04F H'EE050 H'EE051 H'EE052 H'EE053 H'EE054 H'EE055 H'EE056 H'EE057 H'EE058 H'EE059 H'EE05A H'EE05B H'EE05C H'EE05D H'EE05E H'EE05F Module Name Rev. 2.0, 06/04, page 817 of 980 B.2 Addresses (cont) Data Register Bus Width Bit 7 Name -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit Names Bit 6 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Address (Low) H'EE060 H'EE061 H'EE062 H'EE063 H'EE064 H'EE065 H'EE066 H'EE067 H'EE068 H'EE069 H'EE06A H'EE06B H'EE06C H'EE06D H'EE06E H'EE06F H'EE070 H'EE071 H'EE072 H'EE073 H'EE074 H'EE075 H'EE076 H'EE077 H'EE078 H'EE079 H'EE07A H'EE07B H'EE07C H'EE07D H'EE07E H'EE07F Module Name Reserved area (access prohibited) RAMCR -- -- -- -- -- -- -- -- 8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- RAMS -- -- -- -- -- -- -- -- RAM2 -- -- -- -- -- -- -- -- RAM1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Flash memory* Rev. 2.0, 06/04, page 818 of 980 B.2 Addresses (cont) Data Bus Width Bit 7 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 8 8 -- WRST -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- OVF Bit Names Bit 6 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- WT/IT Bit 5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TME Bit 4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CKS2 Bit 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CKS1 Bit 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CKS0 WDT Address (Low) H'EE080 H'EE081 H'EE082 H'EE083 H'EE084 H'EE085 H'EE086 H'EE087 H'EE088 H'EE089 H'EE08A H'EE08B H'EE08C H'EE08D H'EE08E H'EE08F H'EE090 H'EE091 H'EE092 H'EE093 H'EE094 H'EE095 H'EE096 H'EE097 H'EE098 H'EE099 H'EE09A H'EE09B H'EE09C H'EE09D H'EE09E H'EE09F Register Name -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TCSR* TCNT* -- Module Name RSTCSR* 8 -- -- -- -- -- -- -- -- -- -- -- -- Rev. 2.0, 06/04, page 819 of 980 B.2 Addresses (cont) Data Bus Width Bit 7 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 8 8 8 FWE -- -- Bit Names Bit 6 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- FLER -- -- Bit 3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SCO PPVS EPVB Flash memory* Address (Low) H'EE0A0 H'EE0A1 H'EE0A2 H'EE0A3 H'EE0A4 H'EE0A5 H'EE0A6 H'EE0A7 H'EE0A8 H'EE0A9 H'EE0AA H'EE0AB H'EE0AC H'EE0AD H'EE0AE H'EE0AF H'EE0B0 H'EE0B1 H'EE0B2 H'EE0B3 H'EE0B4 H'EE0B5 H'EE0B6 H'EE0B7 Register Name -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- FCCS FPCS FECS Module Name Reserved area (access prohibited) FKEY FMATS FTDAR FVACR 8 8 8 8 K7 MS7 TDER K6 MS6 TDA6 K5 MS5 TDA5 -- K4 MS4 TDA4 -- K3 MS3 TDA3 K2 MS2 TDA2 K1 MS1 TDA1 K0 MS0 TDA0 FVCHG -- E FVSEL FVSEL FVSEL FVSEL 3 2 1 0 H'EE0B8 H'EE0B9 H'EE0BA H'EE0BB H'EE0BC H'EE0BD H'EE0BE H'EE0BF FVADRR FVADRE FVADRH FVADRL 8 8 8 8 Reserved area (access prohibited) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Rev. 2.0, 06/04, page 820 of 980 B.2 Addresses (cont) Data Bus Width Bit 7 8 8 8 8 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address (Low) H'FFE80 H'FFE81 H'FFE82 H'FFE83 H'FFE84 H'FFE85 H'FFE86 H'FFE87 Register Name MAR0AR MAR0AE MAR0AH MAR0AL Module Name DMAC channel 0A ETCR0AH 8 ETCR0AL 8 IOAR0A DTCR0A 8 8 DTE DTE DTSZ DTSZ DTID SAID RPE SAIDE DTIE DTIE DTS2 DTS1 DTS0 Short address mode DTS2A DTS1A DTS0A Full address mode DMAC channel 0B H'FFE88 H'FFE89 H'FFE8A H'FFE8B H'FFE8C H'FFE8D H'FFE8E H'FFE8F MAR0BR MAR0BE MAR0BH MAR0BL 8 8 8 8 ETCR0BH 8 ETCR0BL 8 IOAR0B DTCR0B 8 8 DTE DTME DTSZ -- DTID DAID RPE DAIDE DTIE TMS DTS2 DTS1 DTS0 Short address mode DTS2B DTS1B DTS0B Full address mode Rev. 2.0, 06/04, page 821 of 980 B.2 Addresses (cont) Data Bus Width Bit 7 8 8 8 8 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address (Low) H'FFE90 H'FFE91 H'FFE92 H'FFE93 H'FFE94 H'FFE95 H'FFE96 H'FFE97 Register Name MAR1AR MAR1AE MAR1AH MAR1AL Module Name DMAC channel 1A ETCR1AH 8 ETCR1AL 8 IOAR1A DTCR1A 8 8 DTE DTE DTSZ DTSZ DTID SAID RPE SAIDE DTIE DTIE DTS2 DTS1 DTS0 Short address mode DTS2A DTS1A DTS0A Full address mode DMAC channel 1B H'FFE98 H'FFE99 H'FFE9A H'FFE9B H'FFE9C H'FFE9D H'FFE9E H'FFE9F MAR1BR MAR1BE MAR1BH MAR1BL 8 8 8 8 ETCR1BH 8 ETCR1BL 8 IOAR1B DTCR1B 8 8 DTE DTME DTSZ -- DTID DAID RPE DAIDE DTIE TMS DTS2 DTS1 DTS0 Short address mode DTS2B DTS1B DTS0B Full address mode Rev. 2.0, 06/04, page 822 of 980 B.2 Addresses (cont) Data Register Bus Width Bit 7 Name TSTR TSNC TMDR TOLR TISRA TISRB TISRC -- TCR0 TIOR0 8 8 8 8 8 8 8 8 8 -- -- -- -- -- -- -- -- -- -- Bit Names Bit 6 -- -- MDF -- IMIEA2 IMIEB2 OVIE2 -- CCLR1 IOB2 Bit 5 -- -- FDIR TOB2 IMIEA1 IMIEB1 OVIE1 -- CCLR0 IOB1 Bit 4 -- -- -- TOA2 IMIEA0 IMIEB0 OVIE0 -- CKEG1 IOB0 Bit 3 -- -- -- TOB1 -- -- -- -- CKEG0 -- Bit 2 STR2 SYNC2 PWM2 TOA1 IMFA2 IMFB2 OVF2 -- TPSC2 IOA2 Bit 1 STR1 SYNC1 PWM1 TOB0 IMFA1 IMFB1 OVF1 -- TPSC1 IOA1 Bit 0 STR0 SYNC0 PWM0 TOA0 IMFA0 IMFB0 OVF0 -- TPSC0 IOA0 16-bit timer channel 0 Address (Low) H'FFEA0 H'FFEA1 H'FFEA2 H'FFEA3 H'FFEA4 H'FFEA5 H'FFEA6 H'FFEA7 H'FFEA8 H'FFEA9 H'FFEAA H'FFEAB H'FFEAC H'FFEAD H'FFEAE H'FFEAF H'FFEB0 H'FFEB1 H'FFEB2 H'FFEB3 H'FFEB4 H'FFEB5 H'FFEB6 H'FFEB7 H'FFEB8 H'FFEB9 H'FFEBA H'FFEBB H'FFEBC H'FFEBD H'FFEBE H'FFEBF Module Name 16-bit timer, (all channels) TCNT0H 16 TCNT0L GRA0H GRA0L GRB0H GRB0L TCR1 TIOR1 8 8 -- -- CCLR1 IOB2 CCLR0 IOB1 CKEG1 IOB0 CKEG0 -- TPSC2 IOA2 TPSC1 IOA1 TPSC0 IOA0 16-bit timer channel 1 16 16 TCNT1H 16 TCNT1L GRA1H GRA1L GRB1H GRB1L TCR2 TIOR2 8 8 -- -- CCLR1 IOB2 CCLR0 IOB1 CKEG1 IOB0 CKEG0 -- TPSC2 IOA2 TPSC1 IOA1 TPSC0 IOA0 16-bit timer channel 2 16 16 TCNT2H 16 TCNT2L GRA2H GRA2L GRB2H GRB2L 16 16 Rev. 2.0, 06/04, page 823 of 980 B.2 Addresses (cont) Data Register Bus Width Bit 7 Name 8 8 8 8 8 8 8 8 8 8 -- -- -- -- -- -- 8 8 8 8 8 8 8 8 8 8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CMIEB CMIEB CMFB CMFB -- -- -- -- -- -- CMIEA CMIEA CMFA CMFA -- -- -- -- -- -- OVIE OVIE OVF OVF -- -- -- -- -- -- CCLR1 CCLR1 -- ICE -- -- -- -- -- -- CCLR0 CCLR0 OIS3 OIS3 -- -- -- -- -- -- CKS2 CKS2 OIS2 OIS2 -- -- -- -- -- -- CKS1 CKS1 OS1 OS1 -- -- -- -- -- -- CKS0 CKS0 OS0 OS0 8-bit timer channels 2 and 3 CMIEB CMIEB CMFB CMFB Bit Names Bit 6 CMIEA CMIEA CMFA CMFA Bit 5 OVIE OVIE OVF OVF Bit 4 CCLR1 CCLR1 ADTE ICE Bit 3 CCLR0 CCLR0 OIS3 OIS3 Bit 2 CKS2 CKS2 OIS2 OIS2 Bit 1 CKS1 CKS1 OS1 OS1 Bit 0 CKS0 CKS0 OS0 OS0 Address (Low) Module Name 8-bit timer channels 0 and 1 H'FFEC0 TCR0 H'FFEC1 TCR1 H'FFEC2 TCSR0 H'FFEC3 TCSR1 H'FFEC4 TCORA0 H'FFEC5 TCORA1 H'FFEC6 TCORB0 H'FFEC7 TCORB1 H'FFEC8 TCNT0 H'FFEC9 TCNT1 H'FFECA -- H'FFECB -- H'FFECC -- H'FFECD -- H'FFECE -- H'FFECF -- H'FFED0 TCR2 H'FFED1 TCR3 H'FFED2 TCSR2 H'FFED3 TCSR3 H'FFED4 TCORA2 H'FFED5 TCORA3 H'FFED6 TCORB2 H'FFED7 TCORB3 H'FFED8 TCNT2 H'FFED9 TCNT3 H'FFEDA -- H'FFEDB -- H'FFEDC -- H'FFEDD -- H'FFEDE -- H'FFEDF -- Rev. 2.0, 06/04, page 824 of 980 B.2 Addresses (cont) Data Address Register Bus Width Bit 7 (Low) Name H'FFEE0 SMR H'FFEE1 BRR H'FFEE2 SCR H'FFEE3 TDR H'FFEE4 SSR H'FFEE5 RDR H'FFEE6 SCMR H'FFEE8 SMR H'FFEE9 BRR H'FFEEA SCR H'FFEEB TDR H'FFEEC SSR H'FFEED RDR H'FFEEE SCMR H'FFEF0 SMR H'FFEF1 BRR H'FFEF2 SCR H'FFEF3 TDR H'FFEF4 SSR H'FFEF5 RDR H'FFEF6 SCMR H'FFEF8 TPMR H'FFEF9 TPCR H'FFEFA NDERB H'FFEFB NDERA H'FFEFC NDRB* H'FFEFD NDRA* H'FFEFE NDRB* H'FFEFF NDRA* 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 -- -- -- -- -- -- -- -- SDIR G3NOV SINV G2NOV -- G1NOV SMIF G0NOV NDER8 NDER0 NDR8 -- NDR0 -- -- NDR8 -- NDR0 TPC TDRE RDRF ORER FER/ERS PER TEND MPB MPBT TIE RIE TE RE MPIE TEIE CKE1 CKE0 -- C/A -- CHR -- PE -- O/E SDIR STOP SINV MP -- CKS1 SMIF CKS0 SCI channel 2 TDRE RDRF ORER FER/ERS PER TEND MPB MPBT TIE RIE TE RE MPIE TEIE CKE1 CKE0 -- C/A -- CHR -- PE -- O/E SDIR STOP SINV MP -- CKS1 SMIF CKS0 SCI channel 1 TDRE RDRF ORER FER/ERS PER TEND MPB MPBT TIE RIE TE RE MPIE TEIE CKE1 CKE0 C/A Bit Names Bit 6 CHR Bit 5 PE Bit 4 O/E Bit 3 STOP Bit 2 MP Bit 1 CKS1 Bit 0 CKS0 Module Name SCI channel 0 H'FFEE7 Reserved area (access prohibited) H'FFEEF Reserved area (access prohibited) H'FFEF7 Reserved area (access prohibited) G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER7 NDR15 NDR15 NDR7 NDR7 -- -- -- -- NDER6 NDR14 NDR14 NDR6 NDR6 -- -- -- -- NDER5 NDR13 NDR13 NDR5 NDR5 -- -- -- -- NDER4 NDR12 NDR12 NDR4 NDR4 -- -- -- -- NDER3 NDR11 -- NDR3 -- -- NDR11 -- NDR3 NDER2 NDR10 -- NDR2 -- -- NDR10 -- NDR2 NDER1 NDR9 -- NDR1 -- -- NDR9 -- NDR1 Rev. 2.0, 06/04, page 825 of 980 B.2 Addresses (cont) Data Register Bus Width Bit 7 Name ADDRAH 8 ADDRAL 8 ADDRBH 8 ADDRBL 8 ADDRCH 8 ADDRCL 8 ADDRDH 8 ADDRDL 8 ADCSR ADCR -- -- DADR0 DADR1 DACR -- P1DR P2DR P3DR P4DR P5DR P6DR P7DR P8DR P9DR PADR PBDR -- -- -- -- -- 8 8 8 8 8 8 8 8 8 8 8 8 8 8 DAOE1 -- P17 P27 P37 P47 -- P67 P77 -- -- PA7 PB7 -- -- -- -- -- DAOE0 -- P16 P26 P36 P46 -- P66 P76 -- -- PA6 PB6 -- -- -- -- -- DAE -- P15 P25 P35 P45 -- P65 P75 -- P95 PA5 PB5 -- -- -- -- -- -- -- P14 P24 P34 P44 -- P64 P74 P84 P94 PA4 PB4 -- -- -- -- -- -- -- P13 P23 P33 P43 P53 P63 P73 P83 P93 PA3 PB3 -- -- -- -- -- -- -- P12 P22 P32 P42 P52 P62 P72 P82 P92 PA2 PB2 -- -- -- -- -- -- -- P11 P21 P31 P41 P51 P61 P71 P81 P91 PA1 PB1 -- -- -- -- -- -- -- P10 P20 P30 P40 P50 P60 P70 P80 P90 PA0 PB0 -- -- -- -- -- Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port B 8 8 AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 ADF TRGE -- -- Bit Names Bit 6 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 ADIE -- -- -- Bit 5 AD7 -- AD7 -- AD7 -- AD7 -- ADST -- -- -- Bit 4 AD6 -- AD6 -- AD6 -- AD6 -- SCAN -- -- -- Bit 3 AD5 -- AD5 -- AD5 -- AD5 -- CKS -- -- -- Bit 2 AD4 -- AD4 -- AD4 -- AD4 -- CH2 -- -- -- Bit 1 AD3 -- AD3 -- AD3 -- AD3 -- CH1 -- -- -- Bit 0 AD2 -- AD2 -- AD2 -- AD2 -- CH0 -- -- -- D/A converter Address (Low) H'FFFE0 H'FFFE1 H'FFFE2 H'FFFE3 H'FFFE4 H'FFFE5 H'FFFE6 H'FFFE7 H'FFFE8 H'FFFE9 H'FFFEA H'FFFEB H'FFFEC H'FFFED H'FFFEE H'FFFEF H'FFFF0 H'FFFF1 H'FFFF2 H'FFFF3 H'FFFF4 H'FFFF5 H'FFFF6 H'FFFF7 H'FFFF8 H'FFFF9 H'FFFFA H'FFFFB H'FFFFC H'FFFFD H'FFFFE H'FFFFF Module Name A/D converter Note: * For write access to TCSR, TCNT, and RSTCSR, see section 12.2.4, Notes on Register Access. The address depends on the output trigger setting. Legend WDT: Watchdog timer TPC: Programmable timing pattern controller SCI: Serial communication interface Rev. 2.0, 06/04, page 826 of 980 B.3 Functions Register abbreviation Register name TIER--Timer Interrupt Enable Register H' 90 Address to which register is mapped* Name of on-chip supporting module FRT Bit numbers Bit 7 ICIAE Initial value 6 ICIBE 0 R/W 5 ICICE 0 R/W 4 3 2 1 OVIE 1 R/W 0 Names of the bits. Dashes (--) indicate reserved bits. Initial bit values R/W: OCIDE OCIAE OCIBE 0 R/W 0 R/W 1 R/W 0 R/W 1 Possible types of access R W Read only Write only Timer overflow interrupt enable 0 1 Interrupt requested by OVF flag is disabled Interrupt requested by OVF flag is enabled R/W Read and write Output compare interrupt B enable 0 1 Interrupt requested by OCFB flag is disabled Interrupt requested by OCFB flag is enabled Full name of bit Output compare interrupt A enable 0 1 Interrupt requested by OCFA flag is disabled Interrupt requested by OCFA flag is enabled Descriptions of bit settings Input capture interrupt D enable 0 1 Interrupt requested by ICFD flag is disabled Interrupt requested by ICFD flag is enabled Note: * When the EMC bit in BCR is cleared to 0, addresses of some registers are changed. Rev. 2.0, 06/04, page 827 of 980 P1DDR--Port 1 Data Direction Register H'EE000 Port 1 Bit 7 6 5 4 3 2 1 0 P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial value Read/Write Initial value Read/Write 1 0 W 1 0 W 1 0 W 1 0 W 1 0 W 1 0 W 1 0 W 1 0 W Modes 1 to 4 Modes 5, 7 Port 1 input/output select 0 1 Generic input Generic output P2DDR--Port 2 Data Direction Register H'EE001 Port 2 Bit 7 6 5 4 3 2 1 0 P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial value Read/Write Initial value Read/Write 1 0 W 1 0 W 1 0 W 1 0 W 1 0 W 1 0 W 1 0 W 1 0 W Modes 1 to 4 Modes 5, 7 Port 2 input/output select 0 1 Generic input Generic output Rev. 2.0, 06/04, page 828 of 980 P3DDR--Port 3 Data Direction Register H'EE002 Port 3 Bit 7 6 5 4 3 2 1 0 P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Port 3 input/output select 0 1 Generic input Generic output P4DDR--Port 4 Data Direction Register H'EE003 Port 4 Bit 7 6 5 4 3 2 1 0 P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Port 4 input/output select 0 1 Generic input Generic output Rev. 2.0, 06/04, page 829 of 980 P5DDR--Port 5 Data Direction Register H'EE004 Port 5 Bit 7 6 5 4 3 2 1 0 P53DDR P52DDR P51DDR P50DDR Initial value Read/Write Initial value Read/Write 1 1 1 1 1 1 1 1 1 0 W 1 0 W 1 0 W 1 0 W Modes 1 to 4 Modes 5 , 7 Port 5 input/output select 0 1 Generic input pin Generic output pin P6DDR--Port 6 Data Direction Register H'EE005 Port 6 Bit 7 6 5 4 3 2 1 0 P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Initial value Read/Write 1 0 W 0 W 0 W 0 W 0 W 0 W 0 W Port 6 input/output select 0 1 Generic input Generic output Rev. 2.0, 06/04, page 830 of 980 P8DDR--Port 8 Data Direction Register H'EE007 Port 8 Bit 7 6 5 4 3 2 1 0 P84DDR P83DDR P82DDR P81DDR P80DDR Initial value Read/Write Initial value Read/Write 1 1 1 1 1 1 1 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Modes 1 to 4 Modes 5, 7 Port 8 input/output select 0 1 Generic input Generic output Rev. 2.0, 06/04, page 831 of 980 P9DDR--Port 9 Data Direction Register H'EE008 Port 9 Bit 7 6 5 4 3 2 1 0 P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR Initial value Read/Write 1 1 0 W 0 W 0 W 0 W 0 W 0 W Port 9 input/output select 0 1 Generic input Generic output PADDR--Port A Data Direction Register H'EE009 Port A Bit 7 6 5 4 3 2 1 0 PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR Initial value Read/Write Initial value Read/Write 1 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Modes 3, 4 Modes 1, 2, 5, 7 Port A input/output select 0 1 Generic input Generic output PBDDR--Port B Data Direction Register H'EE00A Port B Bit 7 6 5 4 3 2 1 0 PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Port B input/output select 0 1 Generic input Generic output Rev. 2.0, 06/04, page 832 of 980 MDCR--Mode Control Register H'EE011 System control Bit 7 6 5 4 3 2 MDS2 1 MDS1 * * R 0 MDS0 * R Initial value Read/Write 1 1 0 0 0 R Mode select 2 to 0 Bit 2 MD2 Bit 1 MD1 0 0 1 Bit 0 MD0 0 1 0 1 0 1 1 0 1 0 1 Note: * Determined by the state of the mode pins (MD2 to MD0). Mode 7 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Operating Mode Rev. 2.0, 06/04, page 833 of 980 SYSCR--System Control Register 7 SSBY Initial value Read/Write 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 UE 1 R/W 2 NMIEG 0 R/W H'EE012 1 SSOE 0 R/W 0 RAME 1 R/W System control Bit RAM enable 0 1 On-chip RAM is disabled On-chip RAM is enabled Software standby output port enable In software standby mode, all address bus and bus control signals are highimpedance In software standby mode, address bus retains output state and bus control signals are fixed high 0 1 NMI edge select 0 1 User bit enable 0 1 Standby timer select 2 to 0 Bit 6 STS2 0 1 0 1 1 Software standby 0 1 SLEEP instruction causes transition to sleep mode SLEEP instruction causes transition to software standby mode Bit 5 STS1 0 Bit 4 STS0 0 1 0 1 0 1 0 1 Standby Timer Waiting Time = 8,192 states Waiting Time = 16,384 states Waiting Time = 32,768 states Waiting Time = 65,536 states Waiting Time = 131,072 states Waiting Time = 26,2144 states Waiting Time = 1,024 states Illegal setting CCR bit 6 (UI) is used as an interrupt mask bit CCR bit 6 (UI) is used as a user bit An interrupt is requested at the falling edge of NMI An interrupt is requested at the rising edge of NMI Rev. 2.0, 06/04, page 834 of 980 BRCR--Bus Release Control Register H'EE013 Bus controller Bit 7 A23E 6 A22E 1 1 R/W 1 R/W 5 A21E 1 1 R/W 1 R/W 4 A20E 1 0 1 R/W 3 2 1 0 BRLE Modes 1, 2, 7 Modes 3, 4 Mode 5 Initial value Read/Write Initial value Read/Write Initial value Read/Write 1 1 R/W 1 R/W 1 1 1 1 1 1 1 1 1 0 R/W 0 R/W 0 R/W Address 23 to 20 enable 0 1 Address output Other input/output Bus release enable 0 The bus cannot be released to an external device The bus can be released to an external device 1 ISCR--IRQ Sense Control Register H'EE014 Interrupt Controller Bit 7 6 5 4 3 2 1 0 IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC Initial value Read/Write 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W IRQ5 to IRQ0 sense control 0 1 Interrupts are requested when 1435 to 1430 are low Interrupts are requested by falling-edge input at 1435 to 1430 Rev. 2.0, 06/04, page 835 of 980 IER--IRQ Enable Register H'EE015 Interrupt Controller Bit 7 6 5 IRQ5E 4 IRQ4E 0 R/W 3 IRQ3E 0 R/W 2 IRQ2E 0 R/W 1 IRQ1E 0 R/W 0 IRQ0E 0 R/W Initial value Read/Write 0 R/W 0 R/W 0 R/W IRQ5 to IRQ0 enable 0 1 IRQ5 to IRQ0 interrupts are disabled IRQ5 to IRQ0 interrupts are enabled ISR--IRQ Status Register 7 6 5 IRQ5F Initial value Read/Write 0 0 0 R/(W)* 4 IRQ4F 0 R/(W)* 3 IRQ3F 0 R/(W)* H'EE016 2 IRQ2F 0 R/(W)* 1 IRQ1F 0 R/(W)* Interrupt Controller 0 IRQ0F 0 R/(W)* Bit IRQ5 to IRQ0 flags Bits 5 to 0 IRQ5F to IRQ0F Setting and Clearing Conditions [Clearing conditions] * Read IRQnF when IRQnF = 1, then write 0 in IRQnF. 0 * IRQnSC = 0, IRQn input is high, and interrupt exception handling is being carried out. * IRQnSC = 1 and IRQn interrupt exception handling is being carried out. [Setting conditions] 1 * IRQnSC = 0 and IRQn input is low. * IRQnSC = 1 and IRQn input changes from high to low. (n = 5 to 0) Note: * Only 0 can be written, to clear the flag. Rev. 2.0, 06/04, page 836 of 980 IPRA--Interrupt Priority Register A 7 IPRA7 Initial value Read/Write 0 R/W 6 IPRA6 0 R/W 5 IPRA5 0 R/W 4 IPRA4 0 R/W H'EE018 3 IPRA3 0 R/W 2 IPRA2 0 R/W 1 IPRA1 0 R/W Interrupt Controller 0 IPRA0 0 R/W Bit Priority level A7 to A0 0 1 Priority level 0 (low priority) Priority level 1 (high priority) * Interrupt sources controlled by each bit Bit IPRA Bit 7 IPRA7 IRQ0 Interrupt source Bit 6 IPRA6 IRQ1 Bit 5 IPRA5 IRQ2, IRQ3 Bit 4 IPRA4 IRQ4, IRQ5 Bit 3 IPRA3 WDT, DRAM Bit 2 IPRA2 16-bit timer Bit 1 IPRA1 16-bit timer Bit 0 IPRA0 16-bit timer interface, channel 0 channel 1 channel 2 A/D converter IPRB--Interrupt Priority Register B H'EE019 Interrupt Controller Bit 7 IPRB7 6 IPRB6 0 R/W 5 IPRB5 0 R/W 4 3 IPRB3 2 IPRB2 0 R/W 1 IPRB1 0 R/W 0 Initial value Read/Write 0 R/W 0 R/W 0 R/W 0 R/W Priority level B7 to B5, B3 to B1 0 1 Priority level 0 (low priority) Priority level 1 (high priority) * Interrupt sources controlled by each bit Bit IPRB Bit 7 IPRB7 Bit 6 IPRB6 Bit 5 IPRB5 DMAC Bit 4 Bit 3 IPRB3 SCI Bit 2 IPRB2 SCI Bit 1 IPRB1 SCI Bit 0 8-bit timer 8-bit timer Interrupt channels channels source 0 and 1 2 and 3 channel 0 channel 1 channel 2 Rev. 2.0, 06/04, page 837 of 980 DASTCR--D/A Standby Control Register H'EE01A D/A Bit 7 6 5 4 3 2 1 0 DASTE Initial value Read/Write 1 1 1 1 1 1 1 0 R/W D/A standby enable 0 1 D/A output is disabled in software standby mode D/A output is enabled in software standby mode (Initial value) Rev. 2.0, 06/04, page 838 of 980 DIVCR--Division Control Register H'EE01B System control Bit 7 6 5 4 3 2 1 DIV1 0 DIV0 0 R/W Initial value Read/Write 1 1 1 1 1 1 0 R/W Divide 1 and 0 Bit 1 DIV1 0 Bit 0 DIV0 0 1 1 0 1 1/1 1/2 1/4 1/8 (Initial value) Frequency Division Ratio Rev. 2.0, 06/04, page 839 of 980 MSTCRH--Module Standby Control Register H H'EE01C System control Bit 7 PSTOP 6 5 4 3 2 1 0 MSTPH2 MSTPH1 MSTPH0 1 1 1 1 0 R/W 1 1 1 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Modes 1 to 5 Mode 7 Initial value Read/Write Initial value Read/Write 0 R/W 1 R/W Module standby H2 to H0 Selection bits for placing modules in standby state. Reserved bits clock stop Enables or disables clock output. MSTCRL--Module Standby Control Register L H'EE01D System control Bit 7 MSTPL7 6 5 4 3 2 1 0 MSTPL0 MSTPL5 MSTPL4 MSTPL3 MSTPL2 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial value Read/Write 0 R/W 0 R/W Module standby L7, L5 to L2, L0 Selection bits for placing modules in standby state. Reserved bits Rev. 2.0, 06/04, page 840 of 980 ADRCR--Address Control Register H'EE01E Bus controller Bit 7 6 5 4 3 2 1 0 ADRCTL 1 R/W Address control -- Initial value Read/Write 1 -- 1 -- 1 -- 1 -- 1 -- 1 -- 1 -- -- -- -- Reserved bits -- -- -- Selects address update mode 1 or address update mode 2. ADRCTL 0 1 Description Address update mode 2 is selected Address update mode 1 is selected (Initial value) CSCR--Chip Select Control Register H'EE01F Bus controller Bit 7 CS7E 6 CS6E 0 R/W 5 CS5E 0 R/W 4 CS4E 0 R/W 3 2 1 0 Initial value Read/Write 0 R/W 1 1 1 1 Chip select 7 to 4 enable Bit n CSnE 0 1 (n = 7 to 4) Output of chip select signal CSn is disabled (Initial value) Output of chip select signal CSn is enabled Description Rev. 2.0, 06/04, page 841 of 980 ABWCR--Bus Width Control Register H'EE020 Bus controller Bit 7 ABW7 6 ABW6 1 0 R/W 5 ABW5 1 0 R/W 4 ABW4 1 0 R/W 3 ABW3 1 0 R/W 2 ABW2 1 0 R/W 1 ABW1 1 0 R/W 0 ABW0 1 0 R/W Modes 1, 3, 5, 7 Modes 2, 4 Initial value Initial value Read/Write 1 0 R/W Area 7 to 0 bus width control Bits 7 to 0 ABW7 to ABW0 0 1 Areas 7 to 0 are 16-bit access areas Areas 7 to 0 are 8-bit access areas Bus Width of Access Area ASTCR--Access State Control Register H'EE021 Bus controller Bit 7 AST7 6 AST6 1 R/W 5 AST5 1 R/W 4 AST4 1 R/W 3 AST3 1 R/W 2 AST2 1 R/W 1 AST1 1 R/W 0 AST0 1 R/W Initial value Read/Write 1 R/W Area 7 to 0 access state control Bits 7 to 0 AST7 to AST0 0 1 Areas 7 to 0 are two-state access areas Areas 7 to 0 are three-state access areas Number of States in Access Area Rev. 2.0, 06/04, page 842 of 980 WCRH--Wait Control Register H H'EE022 Bus controller Bit 7 W71 6 W70 1 R/W 5 W61 1 R/W 4 W60 1 R/W 3 W51 1 R/W 2 W50 1 R/W 1 W41 1 R/W 0 W40 1 R/W Initial value Read/Write 1 R/W Area 4 wait control 1 and 0 0 No program wait is inserted 0 1 1 program wait state is inserted 1 0 1 2 program wait states are inserted 3 program wait states are inserted Area 5 wait control 1 and 0 0 No program wait is inserted 0 1 1 program wait state is inserted 1 0 1 2 program wait states are inserted 3 program wait states are inserted Area 6 wait control 1 and 0 0 No program wait is inserted 0 1 1 program wait state is inserted 1 0 1 2 program wait states are inserted 3 program wait states are inserted Area 7 wait control 1 and 0 0 No program wait is inserted 0 1 1 program wait state is inserted 1 0 1 2 program wait states are inserted 3 program wait states are inserted Rev. 2.0, 06/04, page 843 of 980 WCRL--Wait Control Register L 7 W31 Initial value Read/Write 1 R/W 6 W30 1 R/W 5 W21 1 R/W 4 W20 1 R/W 3 W11 1 R/W H'EE023 2 W10 1 R/W 1 W01 1 R/W 0 W00 1 R/W Bus controller Bit Area 0 wait control 1 and 0 0 0 1 0 1 1 No program wait is inserted 1 program wait state is inserted 2 program wait states are inserted 3 program wait states are inserted Area 1 wait control 1 and 0 0 0 1 0 1 1 No program wait is inserted 1 program wait state is inserted 2 program wait states are inserted 3 program wait states are inserted Area 2 wait control 1 and 0 0 0 1 0 1 1 No program wait is inserted 1 program wait state is inserted 2 program wait states are inserted 3 program wait states are inserted Area 3 wait control 1 and 0 0 0 1 0 1 1 No program wait is inserted 1 program wait state is inserted 2 program wait states are inserted 3 program wait states are inserted Rev. 2.0, 06/04, page 844 of 980 BCR--Bus Control Register 7 ICIS1 Initial value Read/Write 1 R/W 6 ICIS0 1 R/W 5 4 3 2 EMC 1 R/W 1 H'EE024 0 WAITE 0 R/W Wait pin enable 0 1 Bus controller Bit BROME BRSTS1 BRSTS0 0 R/W 0 R/W 0 R/W RDEA 1 R/W 9)16 pin wait input is disabled 9)16 pin wait input is enabled Area division unit select 0 Area divisions are as follows: Area 0: 2 MB Area 1: 2 MB Area 2: 8 MB Area 3: 2 MB 1 Area 4: 1.93 MB Area 5: 4 kB Area 6: 23.75 kB Area 7: 22 B Areas 0 to 7 are the same size (2 MB) Expansion memory map control 0 1 Memory map in figure 3.2 in section 3.6 (Memory Map in Each Operating Mode) Memory map in figure 3.1 in section 3.6 (Memory Map in Each Operating Mode) Burst cycle select 0 0 1 Max. 4 words in burst access Max. 8 words in burst access Burst cycle select 1 0 1 Burst access cycle comprises 2 states Burst access cycle comprises 3 states Burst ROM enable 0 1 Area 0 is a basic bus interface area Area 0 is a burst ROM interface area Idle cycle insertion 0 0 1 No idle cycle is inserted in case of consecutive external read and write cycles Idle cycle is inserted in case of consecutive external read and write cycles Idle cycle insertion 1 0 1 No idle cycle is inserted in case of consecutive external read cycles for different areas Idle cycle is inserted in case of consecutive external read cycles for different areas Rev. 2.0, 06/04, page 845 of 980 DRCRA--DRAM Control Register A Bit 7 6 5 4 3 BE 1 0 R/W H'EE026 2 1 0 DRAM interface DRAS2 DRAS1 DRAS0 Initial value Read/Write 0 R/W 0 R/W 0 R/W RDM SRFMD RFSHE 0 R/W 0 R/W 0 R/W Refresh pin enable 0 1 RFSH pin refresh signal output is disabled RFSH pin refresh signal output is enabled Self-refresh mode 0 DRAM self-refreshing is disabled in software standby mode 1 DRAM self-refreshing is enabled in software standby mode RAS down mode 0 1 DRAM interface: RAS up mode selected DRAM interface: RAS down mode selected Burst access enable 0 1 Burst disabled (always full access) DRAM space access performed in fast page mode DRAM area select DRAS2 DRAS1 DRAS0 0 0 0 1 Area 5 Normal Normal Area 4 Normal Normal Area 3 Normal Normal Area 2 Normal DRAM space (CS2) 1 0 Normal Normal DRAM space DRAM space (CS3) 1 1 0 0 Normal Normal Normal (CS2) DRAM space(CS2)* (CS3) (CS2) DRAM space DRAM space DRAM space (CS4) 1 DRAM space DRAM space DRAM space DRAM space (CS5) (CS4) (CS3) (CS2) 1 0 1 DRAM space(CS4)* DRAM space(CS2)* DRAM space(CS2)* Note: *A single CSn pin serves as a common RAS output pin for a number of areas. Unused CSn pins can be used as input/output ports. Rev. 2.0, 06/04, page 846 of 980 DRCRB--DRAM Control Register B Bit 7 MXC1 Initial value Read/Write 0 R/W 6 MXC0 0 R/W 5 4 3 2 TPC 1 0 R/W H'EE027 1 RCW 0 R/W 0 RLW 0 R/W DRAM interface CSEL RCYCE 0 R/W 0 R/W Refresh cycle wait control 0 1 Wait state (TRW) insertion is disabled 1 wait state (TRW) is inserted RAS-CAS wait 0 1 Wait state (Trw) insertion is disabled 1 wait state (Trw) is inserted TP cycle control 0 1 1-state precharge cycle is inserted 2-state precharge cycle is inserted Refresh cycle enable 0 1 Refresh cycles are disabled DRAM refresh cycles are enabled CAS output pin select 0 1 PB4 and PB5 selected as UCAS and LCAS output pins HWR and LWR selected as UCAS and LCAS output pins MXC0 0 Description Column address: 8 bits Compared address: Modes 1, 2 8-bit access space 16-bit access space Modes 3, 4, 5 8-bit access space 16-bit access space Multiplex control 1 and 0 MXC1 0 A19 to A8 A19 to A9 A23 to A8 A23 to A9 1 Column address: 9 bits Compared address: Modes 1, 2 8-bit access space 16-bit access space Modes 3, 4, 5 8-bit access space 16-bit access space A19 to A9 A19 to A10 A23 to A9 A23 to A10 1 0 Column address: 10 bits Compared address: Modes 1, 2 8-bit access space Modes 3, 4, 5 16-bit access space 8-bit access space 16-bit access space A19 to A10 A19 to A11 A23 to A10 A23 to A11 1 Illegal setting Rev. 2.0, 06/04, page 847 of 980 RTMCSR--Refresh Timer Control/Status Register B Bit 7 CMF Initial value Read/Write 0 R/(W)* 6 CMIE 0 R/W 5 CKS2 0 R/W 4 CKS1 0 R/W 3 CKS0 0 R/W 1 2 H'EE028 1 0 DRAM interface 1 1 Refresh counter clock select CKS2 0 CKS1 0 CKS0 0 1 1 0 1 1 0 0 1 1 0 1 Compare match interrupt enable 0 1 The CMI interrupt requested by the CMF flag is disabled The CMI interrupt requested by the CMF flag is enabled Description Count operation halted /2 used as counter clock /8 used as counter clock /32 used as counter clock /128 used as counter clock /512 used as counter clock /2048 used as counter clock /4096 used as counter clock Compare match flag 0 [Clearing conditions] * Cleared by a reset and in standby mode * Cleared by reading CMF when CMF = 1, then writing 0 in CMF 1 [Setting condition] When RTCNT = RTCOR Note: * Only 0 can be written to clear the flag. Rev. 2.0, 06/04, page 848 of 980 RTCNT--Refresh Timer Counter H'EE029 DRAM interface Bit 7 6 5 4 3 2 1 0 Initial value Read/Write 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Incremented by internal clock selected by bits CKS2 to CKS0 in RTMCSR RTCOR--Refresh Time Constant Register H'EE02A DRAM interface Bit 7 6 5 4 3 2 1 0 Initial value Read/Write 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W RTCNT compare match period Note: Only byte access can be used on this register. Rev. 2.0, 06/04, page 849 of 980 P2PCR--Port 2 Input Pull-Up Control Register H'EE03C Port 2 Bit 7 6 5 4 3 2 1 0 P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR Initial value Read/Write 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Port 2 input pull-up control 7 to 0 0 1 Input pull-up transistor is off Input pull-up transistor is on Note: Valid when the corresponding P2DDR bit is cleared to 0 (designating generic input). Rev. 2.0, 06/04, page 850 of 980 P4PCR--Port 4 Input Pull-Up Control Register H'EE03E Port 4 Bit 7 6 5 4 3 2 1 0 P47PCR P46PCR P45PCR P44PCR P43PCR P42PCR P41PCR P40PCR Initial value Read/Write 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Port 4 input pull-up control 7 to 0 0 1 Input pull-up transistor is off Input pull-up transistor is on Note: Valid when the corresponding P4DDR bit is cleared to 0 (designating generic input). P5PCR--Port 5 Input Pull-Up Control Register H'EE03F Port 5 Bit 7 6 5 4 3 2 1 0 P53PCR P52PCR P51PCR P50PCR Initial value Read/Write 1 1 1 1 0 R/W 0 R/W 0 R/W 0 R/W Port 5 input pull-up control 3 to 0 0 1 Input pull-up transistor is off Input pull-up transistor is on Note: Valid when the corresponding P5DDR bit is cleared to 0 (designating generic input). Rev. 2.0, 06/04, page 851 of 980 RAMCR -- RAM Control Register Bit 7 -- Modes 1 to 4 Modes 5, 7 Initial value R/W Initial value R/W 1 -- 1 -- 6 -- 1 -- 1 -- 5 -- 1 -- 1 -- 4 -- 1 -- 1 -- H'EE077 3 RAMS 0 R 0 R/W* 2 Flash Memory 1 RAM1 0 R 0 R/W* 0 RAM0 0 -- 0 R/W* RAM2 0 R 0 R/W* Reserved bits RAM select, RAMS to RAM0 Bit 3 0 1 Bit 2 0/1 0 Bit 1 0/1 0 Bit 0 0/1 0 1 1 0 1 1 0 0 1 1 0 1 RAM Area RAM Emulation Status RAMS RAM2 RAM1 RAM0 H'FFFFE000 to H'FFFFEFFF Emulation H'00000000 to H'00000FFF H'00001000 to H'00001FFF H'00002000 to H'00002FFF H'00003000 to H'00003FFF H'00004000 to H'00004FFF H'00005000 to H'00005FFF H'00006000 to H'00006FFF H'00007000 to H'00007FFF Mapping RAM Note: * In user boot mode, flash memory emulation by RAM is not supported; these bits can be modified, but must not be set to 1. Rev. 2.0, 06/04, page 852 of 980 FCCS--Flash Code Control Status Register 7 FWE Initial value Read/Write 1/0 R 0 R 0 R 6 5 4 FLER 0 R H'EE0B0 3 2 Flash Memory 1 0 SCO Bit 0 R 0 R Reserved bits 0 R 0 (R)/W Reserved bits Source program copy operation 0 On-chip programming/erase control program is not downloaded to on-chip RAM (Initial value) [Clearing condition] When download has finished Request to download on-chip programming/erase control program to on-chip RAM is generated [Setting conditions] When 1 is written while all of the following conditions are satisfied * H'A5 is written to FKEY * Program being executed is in on-chip RAM * Not in RAM emulation mode (RAMS in RAMER is 0) 1 Flash memory error 0 Flash memory operates normally. Program/erase protection (error protection) for flash memory is disabled. [Clearing condition] Power-on reset or in hardware standby mode Erroe occurred during programming/erasing of flash memory. Program/erase protection (error protection) for flash memory is enabled. [Setting conditions] See section 18.6.3, Error Protection 1 Flash write enable 0 1 Low level is input to FWE pin (hardware-protection state) High level is input to FWE pin Rev. 2.0, 06/04, page 853 of 980 FECS--Flash Erase Code Register H'EE0B2 Flash Memory Bit 7 6 5 4 3 2 1 0 EPVB Initial value Read/Write 0 R 0 R 0 R 0 R Reserved bits 0 R 0 R 0 R 0 R/W Erase pulse verify block 0 On-chip erase program is not selected (Initial value) [Clearing condition] When transfer has finished On-chip erase program is selected 1 FPCS--Flash Program Code Select Register 7 6 5 4 3 H'EE0B1 2 Flash Memory 1 0 PPVS Bit Initial value Read/Write 0 R 0 R 0 R 0 R Reserved bits 0 R 0 R 0 R 0 R/W Program pulse verify block 0 On-chip programming control program is not selected (Initial value) [Clearing condition] When transfer has finished On-chip programming control program is selected 1 Rev. 2.0, 06/04, page 854 of 980 FKEY--Flash Key Code Register H'EE0B4 Flash Memory Bit 7 K7 6 K6 0 R/W 5 K5 0 R/W 4 K4 0 R/W 3 K3 0 R/W 2 K2 0 R/W 1 K1 0 R/W 0 K0 0 R/W Initial value Read/Write 0 R/W Key code H'A5 H'5A H'00 Write to SC0 bit is enabled (SC0 bit can be set only when FKEY is H'A5) Programming/erase is enabled (software-protection state when FKEY is not H'5A) Initial value FMATS--Flash Mat Select Register 7 MS7 Initial value Initial value Read/Write 0 1 R/W 6 MS6 0 0 R/W 5 MS5 0 1 R/W 4 MS4 0 0 R/W 3 MS3 0 1 R/W 2 MS2 0 0 R/W H'EE0B5 1 MS1 0 1 R/W 0 MS0 Flash Memory Bit 0 (Mode other than user boot mode) 0 (User boot mode) R/W Mat select User boot mode is selected (user mat selection when FMATS is not H'AA). H'AA H'00 Initial value when started up in user boot mode. Initial value when not started up in user boot mode (user mat selection) [Programmable condition] Program being executed is in on-chip RAM Rev. 2.0, 06/04, page 855 of 980 FTDAR-- Flash Transfer Destination Address Register H'EE0B6 Flash Memory Bit 7 TDER 6 TDA6 0 R/W 5 TDA5 0 R/W 4 TDA4 0 R/W 3 TDA3 0 R/W 2 TDA2 0 R/W 1 TDA1 0 R/W 0 TDA0 0 R/W Initial value Read/Write 0 R/W Transfer Destination Address H'00 H'01 H'02 H'03 H'04 to H'FF Sets the download destination address to H'FFEF20 (initial value) Sets the download destination address to H'FFDF20 Sets the download destination address to H'FFCF20 Sets the download destination address to H'FFBF20 These setting values should not be used. If one of these values is used, bit 7, TDER, is set to 1 when a download commences, causing the download to be interrupted. Transfer Destination Address Setting Error 0 1 Settings of TDA6 to TDA0 are normal values (initial value) Settings of TDER and TDA6 to TDA0 are in the range H'04 to F'FF, so download is interrupted Rev. 2.0, 06/04, page 856 of 980 FVACR--Flash Vector Address Control Register H'EE0B7 Flash Memory Bit 7 FVCHGE 6 5 4 3 FVSEL3 2 FVSEL2 0 R/W 1 FVSEL1 0 R/W 0 FVSEL0 0 R/W Initial value Read/Write 0 R/W 0 R/W 0 R/W Reserved bits 0 R/W 0 R/W Interrut source selection Bit 3 Bit 2 Bit 1 Bit 0 FVSEL3 FVSEL2 FVSEL1 FVSEL0 0 0 0 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 1 0 1 Setting prohibited Vector table data is in internal I/O registers (FVADDR to FVADRL) Setting prohibited Description Vector table data is in area 0 (H'00001C to H'00004F) (Initial value) 0 0 1 0 1 Vector switching function enable 0 1 Function to change space from which to read vector table data is disable (Initial value) Function to change space from which to read vector table data is enabled Rev. 2.0, 06/04, page 857 of 980 FVADR R, E, H, L--Flash Vector Address Data Register R, E, H, l H'EE0B8, H'EE0B9, H'EE0BA, H'EE0BB Flash Memory Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value Read/Write 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W FVADRR FVADRE Vector address setting Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value Read/Write 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W FVADRH FVADRL Vector address setting Rev. 2.0, 06/04, page 858 of 980 MAR0A R/E/H/L--Memory Address Register 0A R/E/H/L H'FFF20 H'FFF21 H'FFF22 H'FFF23 DMAC0 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value Read/Write 1 1 1 1 1 1 1 1 Undetermined R/W R/W R/W R/W R/W R/W R/W R/W MAR0AR Bit 15 14 13 12 11 10 9 8 7 6 5 MAR0AE 4 3 2 1 0 Initial value Read/Write Undetermined Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MAR0AH MAR0AL Source or destination address Rev. 2.0, 06/04, page 859 of 980 ETCR0A H/L--Execute Transfer Count Register 0A H/L * Short address mode I/O mode and idle mode Bit 15 14 13 12 11 10 9 8 7 6 H'FFF24 H'FFF25 DMAC0 5 4 3 2 1 0 Initial value Read/Write Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Transfer counter Repeat mode Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Initial value Read/Write Undetermined R/W R/W R/W R/W R/W R/W R/W R/W ETCR0AH Undetermined R/W R/W R/W R/W R/W R/W R/W R/W ETCR0AL Transfer counter Initial count * Full address mode Normal mode Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value Read/Write Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Transfer counter Block transfer mode Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Initial value Read/Write Undetermined R/W R/W R/W R/W R/W R/W R/W R/W ETCR0AH Undetermined R/W R/W R/W R/W R/W R/W R/W R/W ETCR0AL Block size counter Initial block size Rev. 2.0, 06/04, page 860 of 980 IOAR0A--I/O Address Register 0A H'FFF26 DMAC0 Bit 7 6 5 4 3 2 1 0 Initial value Read/Write R/W R/W R/W Undetermined R/W R/W R/W R/W R/W Short address mode : source or destination address Full address mode : not used Rev. 2.0, 06/04, page 861 of 980 DTCR0A--Data Transfer Control Register 0A * Short address mode Bit 7 DTE Initial value Read/Write 0 R/W 6 DTSZ 0 R/W 5 DTID 0 R/W 4 RPE 0 R/W 3 DTIE 0 R/W 2 DTS2 0 R/W H'FFF27 DMAC0 1 DTS1 0 R/W 0 DTS0 0 R/W Data transfer select Bit 2 Bit 1 Bit 0 DTS2 DTS1 DTS0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 Data Transfer Activation Source Compare match/input capture A interrupt from 16-bit timer channel 0 Compare match/input capture A interrupt from 16-bit timer channel 1 Compare match/input capture A interrupt from 16-bit timer channel 2 A/D converter conversion end interrupt SCI0 transmit-data-empty interrupt SCI0 receive-data-full interrupt Transfer in full address mode Transfer in full address mode Data transfer interrupt enable Interrupt requested by 0 DTE bit is disabled Interrupt requested by 1 DTE bit is enabled Repeat enable RPE DTIE Description 0 0 I/O mode 1 0 Repeat mode 1 1 Idle mode Data transfer increment/decrement 0 1 Incremented: If DTSZ = 0, MAR is incremented by 1 after each transfer If DTSZ = 1, MAR is incremented by 2 after each transfer Decremented: If DTSZ = 0, MAR is decremented by 1 after each transfer If DTSZ = 1, MAR is decremented by 2 after each transfer Data transfer size 0 1 0 1 Byte-size transfer Word-size transfer Data transfer enable Data transfer is disabled Data transfer is enabled Rev. 2.0, 06/04, page 862 of 980 DTCR0A--Data Transfer Control Register 0A (cont) * Full address mode Bit 7 DTE Initial value Read/Write 0 R/W 6 DTSZ 0 R/W 5 SAID 0 R/W 4 SAIDE 0 R/W 3 DTIE 0 R/W 2 DTS2A 0 R/W H'FFF27 DMAC0 1 DTS1A 0 R/W 0 DTS0A 0 R/W Data transfer select 0A 0 1 Set both bits to 1 Data transfer interrupt enable 0 1 Interrupt requested by DTE bit is disabled Interrupt requested by DTE bit is enabled Normal mode Block transfer mode Data transfer select 2A and 1A Source address increment/decrement (bit 5) Source address increment/decrement enable (bit 4) Bit 5 Bit 4 Increment/Decrement Enable SAID SAIDE 0 MARA is held fixed 0 Incremented: If DTSZ = 0, MARA is incremented by 1 after each transfer 1 If DTSZ = 1, MARA is incremented by 2 after each transfer 0 MARA is held fixed 1 Decremented: If DTSZ = 0, MARA is decremented by 1 after each transfer 1 If DTSZ = 1, MARA is decremented by 2 after each transfer Data transfer size 0 1 Byte-size transfer Word-size transfer Data transfer enable 0 1 Data transfer is disabled Data transfer is enabled Rev. 2.0, 06/04, page 863 of 980 MAR0B R/E/H/L--Memory Address Register 0B R/E/H/L H'FFF28 H'FFF29 H'FFF2A H'FFF2B 22 21 20 19 18 DMAC0 Bit 31 30 29 28 27 26 25 24 23 17 16 Initial value Read/Write 1 1 1 1 1 1 1 1 Undetermined R/W R/W R/W R/W R/W R/W R/W R/W MAR0BR Bit 15 14 13 12 11 10 9 8 7 6 5 MAR0BE 4 3 2 1 0 Initial value Read/Write Undetermined Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MAR0BH MAR0BL Source or destination address Rev. 2.0, 06/04, page 864 of 980 ETCR0B H/L--Execute Transfer Count Register 0B H/L * Short address mode I/O mode and idle mode Bit 15 14 13 12 11 10 9 8 7 6 H'FFF2C, H'FFF2D DMAC0 5 4 3 2 1 0 Initial value Read/Write Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Transfer counter Repeat mode Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Initial value Read/Write : Undetermined R/W R/W R/W R/W R/W R/W R/W R/W ETCR0BH Undetermined R/W R/W R/W R/W R/W R/W R/W R/W ETCR0BL Transfer counter Initial count * Full address mode Normal mode Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value Read/Write Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Not used Block transfer mode Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value Read/Write Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Block transfer counter Rev. 2.0, 06/04, page 865 of 980 IOAR0B--I/O Address Register 0B H'FFF2E DMAC0 Bit 7 6 5 4 3 2 1 0 Initial value Read/Write R/W R/W R/W Undetermined R/W R/W R/W R/W R/W Short address mode : source or destination address Full address mode : not used Rev. 2.0, 06/04, page 866 of 980 DTCR0B--Data Transfer Control Register 0B * Short address mode Bit 7 DTE Initial value Read/Write 0 R/W 6 DTSZ 0 R/W 5 DTID 0 R/W 4 RPE 0 R/W 3 DTIE 0 R/W 2 DTS2 0 R/W H'FFF2F DMAC0 1 DTS1 0 R/W 0 DTS0 0 R/W Data transfer select Bit 2 Bit 1 Bit 0 DTS2 DTS1 DTS0 0 0 1 0 1 0 1 0 1 0 1 0 1 Data Transfer Activation Source Compare match/input capture A interrupt from 16-bit timer channel 0 Compare match/input capture A interrupt from 16-bit timer channel 1 Compare match/input capture A interrupt from 16-bit timer channel 2 A/D converter conversion end interrupt SCI0 transmit-data-empty interrupt SCI0 receive-data-full interrupt Falling edge of ,4-3 input Low level of ,4-3 input 1 Data transfer interrupt enable 0 1 Repeat enable Description RPE DTIE 0 0 I/O mode 1 0 Repeat mode 1 1 Idle mode Data transfer increment/decrement 0 1 Incremented: If DTSZ = 0, MAR is incremented by 1 after each transfer If DTSZ = 1, MAR is incremented by 2 after each transfer Decremented: If DTSZ = 0, MAR is decremented by 1 after each transfer If DTSZ = 1, MAR is decremented by 2 after each transfer Interrupt requested by DTE bit is disabled Interrupt requested by DTE bit is enabled Data transfer size 0 1 0 1 Byte-size transfer Word-size transfer Data transfer enable Data transfer is disabled Data transfer is enabled Rev. 2.0, 06/04, page 867 of 980 DTCR0B--Data Transfer Control Register 0B (cont) * Full address mode Bit 7 DTME Initial value Read/Write 0 R/W 0 R/W 6 5 DAID 0 R/W 4 DAIDE 0 R/W 3 TMS 0 R/W 2 DTS2B 0 R/W 1 DTS1B 0 R/W H'FFF2F DMAC0 0 DTS0B 0 R/W Data transfer master enable 0 1 Data transfer is disabled Data transfer is enabled Data transfer select 2B to 0B Bit 2 Bit 1 Bit 0 DTS2B DTS1B DTS0B 0 0 Not available 1 0 Auto-request (cycle-steal mode) Not available Not available Not available Falling edge input of Compare match/input capture A interrupt from 16-bit timer channel 1 Compare match/input capture A interrupt from 16-bit timer channel 2 A/D converter conversion end interrupt Not available Not available Falling edge input of Data Transfer Activation Source Normal Mode Block Transfer Mode Auto-request (burst mode) Compare match/input capture A interrupt from 16-bit timer channel 0 1 0 1 0 1 1 0 1 0 1 ,4-3 Low level input at ,4-3 ,4-3 Not available Transfer mode select 0 1 Destination address increment/decrement (bit 5) Destination address increment/decrement enable (bit 4) Bit 5 Bit 4 Increment/Decrement Enable DAID DAIDE 0 MARB is held fixed 0 Incremented: If DTSZ = 0, MARB is incremented by 1 after each transfer 1 If DTSZ = 1, MARB is incremented by 2 after each transfer 0 MARB is held fixed 1 Decremented: If DTSZ = 0, MARB is decremented by 1 after each transfer 1 If DTSZ = 1, MARB is decremented by 2 after each transfer Destination is the block area in block transfer mode Source is the block area in block transfer mode Rev. 2.0, 06/04, page 868 of 980 MAR1A R/E/H/L--Memory Address Register 1A R/E/H/L H'FFF30 H'FFF31 H'FFF32 H'FFF33 22 21 20 19 18 DMAC1 Bit 31 30 29 28 27 26 25 24 23 17 16 Initial value Read/Write 1 1 1 1 1 1 1 1 Undetermined R/W R/W R/W R/W R/W R/W R/W R/W MAR1AR Bit 15 14 13 12 11 10 9 8 7 6 5 MAR1AE 4 3 2 1 0 Initial value Read/Write Undetermined Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MAR1AH MAR1AL Note: Bit functions are the same as for DMAC0. ETCR1A H/L--Execute Transfer Count Register 1A H/L 15 14 13 12 11 10 9 8 7 6 H'FFF34 H'FFF35 5 4 3 2 DMAC1 1 0 Bit Initial value Read/Write Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Initial value Read/Write Undetermined R/W R/W R/W R/W R/W R/W R/W R/W ETCR1AH Undetermined R/W R/W R/W R/W R/W R/W R/W R/W ETCR1AL Note: Bit functions are the same as for DMAC0. Rev. 2.0, 06/04, page 869 of 980 IOAR1A--I/O Address Register 1A H'FFF36 DMAC1 Bit 7 6 5 4 3 2 1 0 Initial value Read/Write R/W R/W R/W Undetermined R/W R/W R/W R/W R/W Note: Bit functions are the same as for DMAC0. DTCR1A--Data Transfer Control Register 1A * Short address mode Bit 7 DTE Initial value Read/Write 0 R/W 6 DTSZ 0 R/W 5 DTID 0 R/W 4 RPE 0 R/W 3 DTIE 0 R/W H'FFF37 DMAC1 2 DTS2 0 R/W 1 DTS1 0 R/W 0 DTS0 0 R/W * Full address mode Bit 7 DTE Initial value Read/Write 0 R/W 6 DTSZ 0 R/W 5 SAID 0 R/W 4 SAIDE 0 R/W 3 DTIE 0 R/W 2 DTS2A 0 R/W 1 DTS1A 0 R/W 0 DTS0A 0 R/W Note: Bit functions are the same as for DMAC0. Rev. 2.0, 06/04, page 870 of 980 MAR1B R/E/H/L--Memory Address Register 1B R/E/H/L H'FFF38 H'FFF39 H'FFF3A H'FFF3B 22 21 20 19 18 DMAC1 Bit 31 30 29 28 27 26 25 24 23 17 16 Initial value Read/Write 1 1 1 1 1 1 1 1 Undetermined R/W R/W R/W R/W R/W R/W R/W R/W MAR1BR Bit 15 14 13 12 11 10 9 8 7 6 5 MAR1BE 4 3 2 1 0 Initial value Read/Write Undetermined Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MAR1BH MAR1BL Note: Bit functions are the same as for DMAC0. ETCR1B H/L--Execute Transfer Count Register 1B H/L 15 14 13 12 11 10 9 8 7 6 H'FFF3C H'FFF3D 5 4 3 2 DMAC1 1 0 Bit Initial value Read/Write Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Initial value Read/Write Undetermined R/W R/W R/W R/W R/W R/W R/W R/W ETCR1BH Undetermined R/W R/W R/W R/W R/W R/W R/W R/W ETCR1BL Note: Bit functions are the same as for DMAC0. Rev. 2.0, 06/04, page 871 of 980 IOAR1B--I/O Address Register 1B 7 6 5 4 3 H'FFF3E 2 1 DMAC1 0 Bit Initial value Read/Write R/W R/W R/W Undetermined R/W R/W R/W R/W R/W Note: Bit functions are the same as for DMAC0. DTCR1B--Data Transfer Control Register 1B * Short address mode Bit 7 DTE Initial value Read/Write 0 R/W 6 DTSZ 0 R/W 5 DTID 0 R/W 4 RPE 0 R/W 3 DTIE 0 R/W H'FFF3F DMAC1 2 DTS2 0 R/W 1 DTS1 0 R/W 0 DTS0 0 R/W * Full address mode Bit 7 DTME Initial value Read/Write 0 R/W 0 R/W 6 5 DAID 0 R/W 4 DAIDE 0 R/W 3 TMS 0 R/W 2 DTS2B 0 R/W 1 DTS1B 0 R/W 0 DTS0B 0 R/W Note: Bit functions are the same as for DMAC0. Rev. 2.0, 06/04, page 872 of 980 TSTR--Timer Start Register H'FFF60 16-bit timer (all channels) Bit 7 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 STR2 0 R/W 1 STR1 0 R/W 0 STR0 0 R/W Initial value Read/Write 1 -- Reserved bits Counter start 0 0 1 Counter start 1 0 1 Counter start 2 0 1 TCNT2 is halted TCNT2 is counting (Initial value) TCNT1 is halted TCNT1 is counting (Initial value) TCNT0 is halted TCNT0 is counting (Initial value) Rev. 2.0, 06/04, page 873 of 980 TSNC--Timer Synchro Register H'FFF61 16-bit timer (all channels) Bit 7 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 1 0 SYNC2 SYNC1 SYNC0 0 R/W 0 R/W 0 R/W Initial value Read/Write 1 -- Reserved bits Timer synchronization 0 0 Channel 0 timer counter (TCNT0) operates independently (TCNT0 presetting/clearing is unrelated to other channels) (Initial value) Channel 0 operates synchronously TCNT0 synchronous presetting/synchronous clearing is possible 1 Timer synchronization 1 0 Channel 1 timer counter (TCNT1) operates independently (TCNT1 presetting/clearing is unrelated to other channels) (Initial value) Channel 1 operates synchronously TCNT1 synchronous presetting/synchronous clearing is possible 1 Timer synchronization 2 0 Channel 2 timer counter (TCNT2) operates independently (TCNT2 presetting/clearing is unrelated to other channels) (Initial value) Channel 2 operates synchronously TCNT2 synchronous presetting/synchronous clearing is possible 1 Rev. 2.0, 06/04, page 874 of 980 TMDR--Timer Mode Register H'FFF62 16-bit timer (all channels) Bit 7 -- 6 MDF 0 R/W 5 FDIR 0 R/W 4 -- 1 -- 3 -- 1 -- 2 PWM2 0 R/W 1 PWM1 0 R/W 0 PWM0 0 R/W Initial value Read/Write 1 -- PWM mode 0 0 1 Channel 0 operates normally (Initial value) Channel 0 operates in PWM mode PWM mode 1 0 1 Channel 1 operates normally (Initial value) Channel 1 operates in PWM mode PWM mode 2 0 1 Channel 2 operates normally (Initial value) Channel 2 operates in PWM mode Flag direction 0 1 OVF is set to 1 in TISRC when TCNT2 overflows or underflows (Initial value) OVF is set to 1 in TISRC when TCNT2 overflows Phase counting mode flag 0 1 Channel 2 operates normally (Initial value) Channel 2 operates in phase counting mode Rev. 2.0, 06/04, page 875 of 980 TOLR--Timer Output Level Setting Register H'FFF63 16-bit timer (all channels) Bit 7 -- 6 -- 1 -- 5 TOB2 0 W 4 TOA2 0 W 3 TOB1 0 W 2 TOA1 0 W 1 TOB0 0 W 0 TOA0 0 W Initial value Read/Write 1 -- Output level setting A0 0 1 TIOCA0 is 0 TIOCA0 is 1 (Initial value) Output level setting B0 0 1 TIOCB0 is 0 TIOCB0 is 1 (Initial value) Output level setting A1 0 1 TIOCA1 is 0 TIOCA1 is 1 (Initial value) Output level setting B1 0 1 TIOCB1 is 0 TIOCB1 is 1 (Initial value) Output level setting A2 0 1 TIOCA2 is 0 TIOCA2 is 1 (Initial value) Output level setting B2 0 1 TIOCB2 is 0 TIOCB2 is 1 (Initial value) Rev. 2.0, 06/04, page 876 of 980 TISRA--Timer Interrupt Status Register A H'FFF64 16-bit timer (all channels) Bit: 7 -- 6 5 4 3 -- 1 -- 2 1 0 IMIEA2 IMIEA1 IMIEA0 0 R/W 0 R/W 0 R/W IMFA2 IMFA1 IMFA0 0 0 0 R/(W)* R/(W)* R/(W)* Initial value: Read/Write: 1 -- Input capture/compare match flag A0 [Clearing conditions] 0 Read IMFA0 when IMFA0=1, then write 0 in IMFA0 DMAC activated by IMIA0 interrupt. [Setting conditions] TCNT0=GRA0 when GRA0 functions as an output compare register. 1 TCNT0 value is transferred to GRA0 by an input capture signal when GRA0 functions as an input capture register. Input capture/compare match flag A1 [Clearing conditions] 0 Read IMFA1 when IMFA1=1, then write 0 in IMFA1 DMAC activated by IMIA1 interrupt. [Setting conditions] TCNT1=GRA1 when GRA1 functions as an output compare register. 1 TCNT1 value is transferred to GRA1 by an input capture signal when GRA1 functions as an input capture register. Input capture/compare match flag A2 [Clearing conditions] 0 Read IMFA2 when IMFA2=1, then write 0 in IMFA2 DMAC activated by IMIA2 interrupt. [Setting conditions] TCNT2=GRA2 when GRA2 functions as an output compare register. 1 TCNT2 value is transferred to GRA2 by an input capture signal when GRA2 functions as an input capture register. Input capture/compare match interrupt enable A0 0 IMIA0 interrupt requested by IMFA0 flag is disabled 1 IMIA0 interrupt requested by IMFA0 flag is enabled (Initial value) (Initial value) (Initial value) (Initial value) (Initial value) Input capture/compare match interrupt enable A1 0 IMIA1 interrupt requested by IMFA1 flag is disabled 1 IMIA1 interrupt requested by IMFA1 flag is enabled Input capture/compare match interrupt enable A2 0 IMIA2 interrupt requested by IMFA2 flag is disabled 1 IMIA2 interrupt requested by IMFA2 flag is enabled (Initial value) Note: * Only 0 can be written, to clear the flag. Rev. 2.0, 06/04, page 877 of 980 TISRB--Timer Interrupt Status Register B H'FFF65 16-bit timer (all channels) Bit: 7 -- 6 5 4 3 -- 1 -- 2 1 0 IMIEB2 IMIEB1 IMIEB0 0 R/W 0 R/W 0 R/W IMFB2 IMFB1 IMFB0 0 0 0 R/(W)* R/(W)* R/(W)* Initial value: Read/Write: 1 -- Input capture/compare match flag B0 [Clearing condition] Read IMFB0 when IMFB0=1, then write 0 in IMFB0. (Initial value) 0 [Setting conditions] TCNT0=GRB0 when GRB0 functions as an output compare register. 1 TCNT0 value is transferred to GRB0 by an input capture signal when GRB0 functions as an input capture register. Input capture/compare match flag B1 [Clearing condition] Read IMFB1 when IMFB1=1, then write 0 in IMFB1. [Setting conditions] TCNT1=GRB1 when GRB1 functions as an output compare register. 1 TCNT1 value is transferred to GRB1 by an input capture signal when GRB1 functions as an input capture register. Input capture/compare match flag B2 [Clearing condition] Read IMFB2 when IMFB2=1, then write 0 in IMFB2. [Setting conditions] TCNT2=GRB2 when GRB2 functions as an output compare register. 1 TCNT2 value is transferred to GRB2 by an input capture signal when GRB2 functions as an input capture register. Input capture/compare match interrupt enable B0 0 IMIB0 interrupt requested by IMFB0 flag is disabled 1 IMIB0 interrupt requested by IMFB0 flag is enabled (Initial value) (Initial value) (Initial value) 0 0 (Initial value) Input capture/compare match interrupt enable B1 0 IMIB1 interrupt requested by IMFB1 flag is disabled 1 IMIB1 interrupt requested by IMFB1 flag is enabled Input capture/compare match interrupt enable B2 0 IMIB2 interrupt requested by IMFB2 flag is disabled 1 IMIB2 interrupt requested by IMFB2 flag is enabled (Initial value) Note : * Only 0 can be written, to clear the flag. Rev. 2.0, 06/04, page 878 of 980 TISRC--Timer Interrupt Status Register C H'FFF66 16-bit timer (all channels) Bit: 7 -- 6 5 4 3 -- 1 -- 2 1 0 OVIE2 OVIE1 OVIE0 0 R/W 0 R/W 0 R/W OVF2 OVF1 OVF0 0 0 0 R/(W)* R/(W)* R/(W)* Initial value: Read/Write: 1 -- Overflow flag 0 0 1 [Clearing condition] Read OVF0 when OVF0 = 1, then write 0 in OVF0. [Setting condition] TCNT0 overflowed from H'FFFF to H'0000. (Initial value) Overflow flag 1 0 1 [Clearing condition] Read OVF1 when OVF1 = 1, then write 0 in OVF1. [Setting condition] TCNT1 overflowed from H'FFFF to H'0000. (Initial value) Overflow flag 2 0 [Clearing condition] Read OVF2 when OVF2 = 1, then write 0 in OVF2. (Initial value) 1 [Setting condition] TCNT2 overflowed from H'FFFF to H'0000, or underflowed from H'0000 to H'FFFF. Overflow interrupt enable 0 OVI0 interrupt requested by OVF0 flag is disabled 0 1 OVI0 interrupt requested by OVF0 flag is enabled (Initial value) Overflow interrupt enable 1 OVI1 interrupt requested by OVF1 flag is disabled 0 1 OVI1 interrupt requested by OVF1 flag is enabled (Initial value) Overflow interrupt enable 2 OVI2 interrupt requested by OVF2 flag is disabled 0 1 OVI2 interrupt requested by OVF2 flag is enabled (Initial value) Note : * Only 0 can be written, to clear the flag. Rev. 2.0, 06/04, page 879 of 980 16TCR0--Timer Control Register H'FFF68 16-bit timer channel 0 Bit 7 -- 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 CKEG1 0 R/W 3 CKEG0 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W Initial value Read/Write 1 -- Timer prescaler 2 to 0 Bit 1 Bit 0 Bit 2 TPSC2 TPSC1 TPSC0 TCNT Clock Source Internal clock : Internal clock : / 2 Internal clock : / 4 Internal clock : / 8 External clock A : TCLKA input External clock B : TCLKB input External clock C : TCLKC input External clock D : TCLKD input (Initial value) 0 0 1 0 1 1 0 1 0 1 0 1 0 1 Clock edge 1 and 0 Bit 4 Bit 3 CKEG1 CKEG0 Counted Edges of External Clock Rising edges counted Falling edges counted Both edges counted (Initial value) 0 0 1 0 1 -- Counter clear 1 and 0 Bit 6 Bit 5 CCLR1 CCLR0 TCNT clear Sources (Initial value) TCNT is not cleared TCNT is cleared by GRA compare match or input capture TCNT is cleared by GRB compare match or input capture Synchronous clear : TCNT is cleared in synchronization with other synchronized timers 0 1 0 1 0 1 Rev. 2.0, 06/04, page 880 of 980 TIOR0--Timer I/O Control Register 0 7 -- Initial value: Read/Write: 1 -- 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W H'FFF69 3 -- 1 -- 2 IOA2 0 R/W 1 IOA1 0 R/W 16-bit timer channel 0 0 IOA0 0 R/W Bit: I/O control A2 to A0 Bit 2 Bit 1 IOA2 IOA1 0 0 1 Bit 0 IOA0 0 1 0 1 0 1 0 1 GRA Functions GRA is an output compare register No output at compare match 0 output at GRA compare match 1 output at GRA compare match Output toggles at GRA compare match (channel 2 only: 1 output) GRA is an input capture register GRA captures rising edges of input GRA captures falling edges of input GRA captures both edges of input (Initial value) 0 1 1 I/O control B2 to B0 Bit 6 Bit 5 IOB2 IOB1 0 0 1 Bit 4 IOB0 0 1 0 1 0 1 0 1 GRB Functions GRB is an output compare register No output at compare match (Initial value) 0 output at GRB compare match 1 output at GRB compare match Output toggles at GRB compare match (channel 2 only: 1 output) GRB captures rising edges of input GRB captures falling edges of input GRB captures both edges of input 0 1 1 GRB is an input capture register Rev. 2.0, 06/04, page 881 of 980 16TCNT0 H/L--Timer Counter 0 H/L H'FFF6A, H'FFF6B 16-bit timer channel 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value Read/Write 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up - counter GRA0 H/L--General Register A0 H/L 15 14 13 12 11 10 9 H'FFF6C, H'FFF6D 8 7 6 5 16-bit timer channel 0 4 3 2 1 0 Bit Initial value Read/Write 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Output compare or input capture register GRB0 H/L--General Register B0 H/L 15 14 13 12 11 10 9 H'FFF6E, H'FFF6F 8 7 6 5 16-bit timer channel 0 4 3 2 1 0 Bit Initial value Read/Write 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Output compare or input capture register Rev. 2.0, 06/04, page 882 of 980 16TCR1 Timer Control Register 1 H'FFF70 16-bit timer channel 1 Bit 7 -- 6 5 4 3 2 1 0 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial value Read/Write 1 -- Note: Bit functions are the same as for 16-bit timer channel 0. TIOR1--Timer I/O Control Register 1 H'FFF71 16-bit timer channel 1 Bit 7 -- 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 -- 1 -- 2 IOA2 0 R/W 1 IOA1 0 R/W 0 IOA0 0 R/W Initial value Read/Write 1 -- Note: Bit functions are the same as for 16-bit timer channel 0. 16TCNT1 H/L--Timer Counter 1 H/L H'FFF72, H'FFF73 16-bit timer channel 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value Read/Write 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: Bit functions are the same as for 16-bit timer channel 0. Rev. 2.0, 06/04, page 883 of 980 GRA1 H/L--General Register A1 H/L H'FFF74, H'FFF75 16-bit timer channel 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value Read/Write 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: Bit functions are the same as for 16-bit timer channel 0. GRB1 H/L--General Register B1 H/L H'FFF76, H'FFF77 16-bit timer channel 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value Read/Write 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: Bit functions are the same as for 16-bit timer channel 0. 16TCR2 Timer Control Register 2 H'FFF78 16-bit timer channel 2 Bit 7 -- 6 5 4 3 2 1 0 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial value Read/Write 1 -- Notes : 1. Bit functions are the same as for 16-bit timer channel 0. 2. When phase counting mode is selected in channel 2, the settings of bits CKEG1 and CKEG0 and TPSC2 to TPSC0 in TCR2 are ignored. Rev. 2.0, 06/04, page 884 of 980 TIOR2--Timer I/O Control Register 2 H'FFF79 16-bit timer channel 2 Bit 7 -- 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 -- 1 -- 2 IOA2 0 R/W 1 IOA1 0 R/W 0 IOA0 0 R/W Initial value Read/Write 1 -- Note: Bit functions are the same as for 16-bit timer channel 0. 16TCNT2 H/L--Timer Counter 2 H/L 15 14 13 12 11 10 9 H'FFF7A, H'FFF7B 8 7 6 5 16-bit timer channel 2 4 3 2 1 0 Bit Initial value Read/Write 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Phase counting mode : up/down counter Other mode : up-counter GRA2 H/L--General Register A2 H/L 15 14 13 12 11 10 9 H'FFF7C, H'FFF7D 8 7 6 5 16-bit timer channel 2 4 3 2 1 0 Bit Initial value Read/Write 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: Bit functions are the same as for 16-bit timer channel 0. Rev. 2.0, 06/04, page 885 of 980 GRB2 H/L--General Register B2 H/L 15 14 13 12 11 10 9 H'FFF7E, H'FFF7F 8 7 6 5 16-bit timer channel 2 4 3 2 1 0 Bit Initial value Read/Write 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: Bit functions are the same as for 16-bit timer channel 0. Rev. 2.0, 06/04, page 886 of 980 8TCR0--Timer Control Register 0 8TCR1--Timer Control Register 1 Bit 7 CMIEB Initial value Read/Write 0 R/W 6 CMIEA 0 R/W 5 OVIE 0 R/W 4 CCLR1 0 R/W 3 H'FFF80 H'FFF81 2 CKS2 0 R/W 1 CKS1 0 R/W 0 8-bit timer channel 0 8-bit timer channel 1 CCLR0 0 R/W CKS0 0 R/W Clock select 2 to 0 0 0 0 1 1 1 0 Clock input is disabled Internal clock, counted on rising edge of /8 Internal clock, counted on rising edge of /64 Internal clock, counted on rising edge of /8192 Channel 0: Count on TCNT1 overflow signal* Channel 1: Count on TCNT0 compare match A* External clock, counted on falling edge External clock, counted on rising edge External clock, counted on both rising and falling edges 0 1 0 1 0 1 1 Notes: * If the clock input of channel 0 is the TCNT1 overflow signal and that of channel 1 is the TCNT0 compare match signal, no incrementing clock is generated. Do not use this setting. Counter clear 1 and 0 0 0 1 1 0 1 Clearing is disabled Cleared by compare match A Cleared by compare match B/input capture B Cleared by input capture B Timer overflow interrupt enable 0 1 OVI interrupt requested by OVF is disabled OVI interrupt requested by OVF is enabled Compare match interrupt enable A 0 1 CMIA interrupt requested by CMFA is disabled CMIA interrupt requested by CMFA is enabled Compare match interrupt enable B 0 1 CMIB interrupt requested by CMFB is disabled CMIB interrupt requested by CMFB is enabled Rev. 2.0, 06/04, page 887 of 980 8TCSR0--Timer Control/Status Register 0 Bit 7 CMFB Initial value Read/Write 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 ADTE 0 R/W 3 OIS3 0 R/W H'FFF82 2 OIS2 0 R/W 1 OS1 0 R/W 0 OS0 0 R/W 8-bit timer channel 0 Output select A1 and A0 Bit 1 Bit 0 Description OS1 OS0 0 0 1 0 No change at compare match A 0 output at compare match A 1 output at compare match A Output toggles at compare match A 1 1 Output/input capture edge select B3 and B2 ICE in Bit 3 TCSR1 OIS3 0 0 1 1 0 0 1 1 1 0 1 Bit 2 OIS2 Description No change at compare match B 0 output at compare match B 1 output at compare match B Output toggles at compare match B TCORB input capture on rising edge TCORB input capture on falling edge TCORB input capture on both rising and falling edges 0 1 0 A/D trigger enable (TCSR0 only) TRGE*1 Bit 4 ADTE Description A/D converter start requests by compare match A or an external trigger are disabled A/D converter start requests by compare match A or an external trigger are enabled A/D converter start requests by an external trigger are enabled A/D converter start requests by compare match A are enabled 0 0 1 1 0 1 Note: *1 TRGE is bit 7 of the A/D control register (ADCR). Timer overflow flag 0 1 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF [Setting condition] TCNT overflows from H'FF to H'00 Compare match flag A 0 1 [Clearing condition] Read CMFA when CMFA = 1, then write 0 in CMFA [Setting condition] TCNT = TCORA Compare match/input capture flag B 0 [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB [Setting conditions] TCNT = TCORB The TCNT value is transferred to TCORB by an input capture signal when TCORB functions as an input capture register. 1 Note: * Only 0 can be written to bits 7 to 5, to clear these flags. Rev. 2.0, 06/04, page 888 of 980 8TCSR1--Timer Control/Status Register 1 Bit 7 CMFB Initial value Read/Write 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 ICE 0 R/W 3 OIS3 0 R/W H'FFF83 2 OIS2 0 R/W 1 OS1 0 R/W 0 8-bit timer channel 1 OS0 0 R/W Output select A1 and A0 Bit 1 Bit 0 Description OS1 OS0 0 0 1 0 No change at compare match A 0 output at compare match A 1 output at compare match A Output toggles at compare match A 1 1 Output/input capture edge select B3 and B2 ICE in Bit 3 TCSR1 OIS3 Bit 2 OIS2 Description No change at compare match B 0 output at compare match B 1 output at compare match B Output toggles at compare match B TCORB input capture on rising edge TCORB input capture on falling edge TCORB input capture on both rising and falling edges 0 0 1 0 1 0 1 0 0 1 1 Input capture enable 0 1 1 0 1 TCORB is a compare match register TCORB is an input capture register Timer overflow flag 0 1 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF [Setting condition] TCNT overflows from H'FF to H'00 Compare match flag A 0 1 [Clearing condition] Read CMFA when CMFA = 1, then write 0 in CMFA [Setting condition] TCNT = TCORA Compare match/input capture flag B 0 [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB [Setting conditions] TCNT = TCORB The TCNT value is transferred to TCORB by an input capture signal when TCORB functions as an input capture register. 1 Note: * Only 0 can be written to bits 7 to 5, to clear these flags. Rev. 2.0, 06/04, page 889 of 980 TCORA0--Time Constant Register A0 TCORA1--Time Constant Register A1 H'FFF84 H'FFF85 8-bit timer channel 0 8-bit timer channel 1 TCORA0 Bit 15 14 13 12 11 10 9 8 7 6 5 TCORA1 4 3 2 1 0 Initial value Read/Write 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCORB0--Time Constant Register B0 TCORB1--Time Constant Register B1 H'FFF86 H'FFF87 8-bit timer channel 0 8-bit timer channel 1 TCORB0 Bit 15 14 13 12 11 10 9 8 7 6 5 TCORB1 4 3 2 1 0 Initial value Read/Write 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8TCNT0--Timer Counter 0 8TCNT1--Timer Counter 1 H'FFF88 H'FFF89 8-bit timer channel 0 8-bit timer channel 1 TCNT0 Bit 15 14 13 12 11 10 9 8 7 6 5 TCNT1 4 3 2 1 0 Initial value Read/Write 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. 2.0, 06/04, page 890 of 980 TCSR--Timer Control/Status Register 7 OVF Initial value Read/Write 0 R/(W)* 6 WT/16 0 R/W 5 TME 0 R/W 1 1 4 3 H'FFF8C 2 CKS2 0 R/W 1 CKS1 0 R/W WDT 0 CKS0 0 R/W Bit Clock select 2 to 0 CKS2 CKS1 CKS0 0 0 0 1 1 0 1 0 0 1 1 Timer enable Timer disabled 0 * TCNT is initialized to H'00 and halted Timer enabled 1 * TCNT is counting 1 0 1 Description /2 /32 /64 /128 /256 /512 /2048 /4096 Timer mode select Interval timer: 0 requests interval timer interrupts Watchdog timer: generates a reset signal 1 Overflow flag 0 1 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF [Setting condition] TCNT changes from H'FF to H'00 Note: * Only 0 can be written, to clear the flag. Rev. 2.0, 06/04, page 891 of 980 TCNT--Timer Counter H'FFF8D (read), H'FFF8C (write) WDT Bit 7 6 5 4 3 2 1 0 Initial value Read/Write 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Count value RSTCSR--Reset Control/Status Register H'FFF8F (read), H'FFF8E (write) WDT Bit 7 WRST 6 5 4 3 2 1 0 Initial value Read/Write 0 R/(W)* 0 R/W 1 1 1 1 1 1 Reserved bits Watchdog timer reset 0 [Clearing conditions] Reset signal at 4-5 pin Read WRST when WRST = 1, then write 0 in WRST [Setting condition] 1 TCNT overflow generates a reset signal Note: * Only 0 can be written in bit 7, to clear the flag. Rev. 2.0, 06/04, page 892 of 980 8TCR2--Timer Control Register 2 8TCR3--Timer Control Register 3 Bit 7 CMIEB Initial value Read/Write 0 R/W 6 CMIEA 0 R/W 5 OVIE 0 R/W 4 CCLR1 0 R/W 3 CCLR0 0 R/W 2 H'FFF90 H'FFF91 1 CKS1 0 R/W 0 8-bit timer channel 2 8-bit timer channel 3 CKS2 0 R/W CKS0 0 R/W Clock select 2 to 0 CSK2 CSK1 CSK0 0 0 1 0 0 1 1 Description Clock input is disabled Internal clock, counted on rising edge of /8 Internal clock, counted on rising edge of /64 Internal clock, counted on rising edge of /8192 Channel 2: Count on TCNT3 overflow signal* Channel 3: Count on TCNT2 compare match A* External clock, counted on falling edge External clock, counted on rising edge External clock, counted on both rising and falling edges 0 1 1 0 1 0 1 Note: * If the clock input of channel 2 is the TCNT3 overflow signal and that of channel 3 is the TCNT2 compare match signal, no incrementing clock is generated. Do not use this setting. Counter clear 1 and 0 0 0 1 0 1 Clearing is disabled Cleared by compare match A Cleared by compare match B/input capture B Cleared by input capture B 1 Timer overflow interrupt enable 0 1 OVI interrupt requested by OVF is disabled OVI interrupt requested by OVF is enabled Compare match interrupt enable A 0 1 CMIA interrupt requested by CMFA is disabled CMIA interrupt requested by CMFA is enabled Compare match interrupt enable B 0 1 CMIB interrupt requested by CMFB is disabled CMIB interrupt requested by CMFB is enabled Rev. 2.0, 06/04, page 893 of 980 8TCSR2--Timer Control/Status Register 2 8TCSR3--Timer Control/Status Register 3 TCSR2 Bit 7 CMFB Initial value Read/Write TCSR3 Bit 0 R/(W)* 7 CMFB Initial value Read/Write 0 R/(W)* 6 CMFA 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 5 OVF 0 R/(W)* 1 4 ICE 0 R/W 4 3 OIS3 0 R/W 3 OIS3 0 R/W H'FFF92 H'FFF93 2 OIS2 0 R/W 2 OIS2 0 R/W 1 OS1 0 R/W 1 OS1 0 R/W 8-bit timer channel 2 8-bit timer channel 3 0 OS0 0 R/W 0 OS0 0 R/W Output select A1 and A0 Bit 1 Bit 0 Description OS1 OS0 0 0 1 0 No change at compare match A 0 output at compare match A 1 output at compare match A Output toggles at compare match A 1 1 Output/input capture edge select B3 and B2 ICE in Bit 3 TCSR3 OIS3 Bit 3 OIS2 Description No change at compare match B 0 output at compare match B 1 output at compare match B Output toggles at compare match B TCORB input capture on rising edge TCORB input capture on falling edge TCORB input capture on both rising and falling edges 0 0 1 0 1 0 1 0 0 1 1 1 0 Input capture enable (TCSR3 only) 0 1 TCORB is a compare match register TCORB is an input capture register Timer overflow flag 0 1 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF [Setting condition] TCNT overflows from H'FF to H'00 Compare match flag A 0 1 [Clearing condition] Read CMFA when CMFA = 1, then write 0 in CMFA [Setting condition] TCNT = TCORA Compare match/input capture flag B 0 [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB [Setting conditions] TCNT = TCORB The TCNT value is transferred to TCORB by an input capture signal when TCORB functions as an input capture register. 1 Note: * Only 0 can be written to bits 7 to 5, to clear these flags. Rev. 2.0, 06/04, page 894 of 980 TCORA2--Time Constant Register A2 TCORA3--Time Constant Register A3 H'FFF94 H'FFF95 8-bit timer channel 2 8-bit timer channel 3 TCORA2 Bit 15 14 13 12 11 10 9 8 7 6 5 TCORA3 4 3 2 1 0 Initial value Read/Write 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCORB2--Time Constant Register B2 TCORB3--Time Constant Register B3 H'FFF96 H'FFF97 8-bit timer channel 2 8-bit timer channel 3 TCORB2 Bit 15 14 13 12 11 10 9 8 7 6 5 TCORB3 4 3 2 1 0 Initial value Read/Write 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8TCNT2--Timer Counter 2 8TCNT3--Timer Counter 3 H'FFF98 H'FFF99 8-bit timer channel 2 8-bit timer channel 3 TCNT2 Bit 15 14 13 12 11 10 9 8 7 6 5 TCNT3 4 3 2 1 0 Initial value Read/Write 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. 2.0, 06/04, page 895 of 980 DADR0--D/A Data Register 0 H'FFF9C D/A Bit 7 6 5 4 3 2 1 0 Initial value Read/Write 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W D/A conversion data DADR1--D/A Data Register 1 H'FFF9D D/A Bit 7 6 5 4 3 2 1 0 Initial value Read/Write 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W D/A conversion data Rev. 2.0, 06/04, page 896 of 980 DACR--D/A Control Register H'FFF9E D/A Bit 7 DAOE1 6 DAOE0 0 R/W 5 DAE 0 R/W 4 3 2 1 0 Initial value Read/Write 0 R/W 1 1 1 1 1 D/A enable Bit 7 DAOE1 0 Bit 6 DAOE0 0 Bit 5 Description DAE D/A conversion is disabled in channels 0 and 1 D/A conversion is enabled in channel 0 0 1 0 D/A conversion is disabled in channel 1 0 1 1 D/A conversion is enabled in channels 0 and 1 D/A conversion is disabled in channel 0 D/A conversion is enabled in channel 1 1 0 1 D/A conversion is enabled in channels 0 and 1 D/A conversion is enabled in channels 0 and 1 1 0 0 1 1 D/A output enable 0 0 1 DA0 analog output is disabled Channel-0 D/A conversion and DA0 analog output are enabled D/A output enable 1 0 1 DA1 analog output is disabled Channel-1 D/A conversion and DA1 analog output are enabled Rev. 2.0, 06/04, page 897 of 980 TPMR--TPC Output Mode Register 7 6 5 4 3 G3NOV Initial value Read/Write 1 1 1 1 0 R/W 2 G2NOV 0 R/W 1 G1NOV 0 R/W H'FFFA0 0 G0NOV 0 R/W TPC Bit Group 0 non-overlap 0 Normal TPC output in group 0. Output values change at compare match A in the selected 16-bit timer channel Non-overlapping TPC output in group 0, controlled by compare match A and B in the selected 16-bit timer channel 1 Group 1 non-overlap 0 1 Normal TPC output in group 1. Output values change at compare match A in the selected 16-bit timer channel Non-overlapping TPC output in group 1, controlled by compare match A and B in the selected 16-bit timer channel Group 2 non-overlap 0 1 Normal TPC output in group 2. Output values change at compare match A in the selected 16-bit timer channel Non-overlapping TPC output in group 2, controlled by compare match A and B in the selected 16-bit timer channel Group 3 non-overlap 0 1 Normal TPC output in group 3. Output values change at compare match A in the selected 16-bit timer channel Non-overlapping TPC output in group 3, controlled by compare match A and B in the selected 16-bit timer channel Rev. 2.0, 06/04, page 898 of 980 TPCR--TPC Output Control Register Bit 7 G3CMS1 Initial value Read/Write 1 R/W 6 G3CMS0 1 R/W 5 G2CMS1 1 R/W 4 G2CMS0 1 R/W 3 G1CMS1 1 R/W 2 G1CMS0 1 R/W 1 G0CMS1 1 R/W H'FFFA1 0 G0CMS0 1 R/W TPC Group 0 compare match select 1 and 0 Bit 1 Bit 0 G0CMS1 G0CMS0 0 0 1 1 0 1 16-Bit Timer Channel Selected as Output Trigger TPC output group 0 (TP3 to TP0) is triggered by compare match in 16-bit timer channel 0 TPC output group 0 (TP3 to TP0) is triggered by compare match in 16-bit timer channel 1 TPC output group 0 (TP3 to TP0) is triggered by compare match in 16-bit timer channel 2 Group 1 compare match select 1 and 0 Bit 3 Bit 2 G1CMS1 G1CMS0 0 0 1 1 0 1 Group 2 compare match select 1 and 0 Bit 5 Bit 4 0 1 0 1 G2CMS1 G2CMS0 0 1 16-Bit Timer Channel Selected as Output Trigger TPC output group 2 (TP11 to TP8) is triggered by compare match in 16-bit timer channel 0 TPC output group 2 (TP11 to TP8) is triggered by compare match in 16-bit timer channel 1 TPC output group 2 (TP11 to TP8) is triggered by compare match in 16-bit timer channel 2 16-Bit Timer Channel Selected as Output Trigger TPC output group 1 (TP7 to TP4) is triggered by compare match in 16-bit timer channel 0 TPC output group 1 (TP7 to TP4) is triggered by compare match in 16-bit timer channel 1 TPC output group 1 (TP7 to TP4) is triggered by compare match in 16-bit timer channel 2 Group 3 compare match select 1 and 0 Bit 7 Bit 6 0 1 0 1 G3CMS1 G3CMS0 0 1 16-Bit Timer Channel Selected as Output Trigger TPC output group 3 (TP15 to TP12) is triggered by compare match in 16-bit timer channel 0 TPC output group 3 (TP15 to TP12) is triggered by compare match in 16-bit timer channel 1 TPC output group 3 (TP15 to TP12) is triggered by compare match in 16-bit timer channel 2 Rev. 2.0, 06/04, page 899 of 980 NDERB--Next Data Enable Register B H'FFFA2 TPC Bit 7 NDER15 6 NDER14 0 R/W 5 NDER13 0 R/W 4 NDER12 0 R/W 3 NDER11 0 R/W 2 NDER10 0 R/W 1 NDER9 0 R/W 0 NDER8 0 R/W Initial value Read/Write 0 R/W Next data enable 15 to 8 Bits 7 to 0 NDER15 to NDER8 0 Description TPC outputs TP15 to TP8 are disabled (NDR15 to NDR8 are not transferred to PB7 to PB0) TPC outputs TP15 to TP8 are enabled (NDR15 to NDR8 are transferred to PB7 to PB0) 1 NDERA--Next Data Enable Register A H'FFFA3 TPC Bit 7 NDER7 6 NDER6 0 R/W 5 NDER5 0 R/W 4 NDER4 0 R/W 3 NDER3 0 R/W 2 NDER2 0 R/W 1 NDER1 0 R/W 0 NDER0 0 R/W Initial value Read/Write 0 R/W Next data enable 7 to 0 Bits 7 to 0 NDER7 to NDER0 0 Description TPC outputs TP7 to TP0 are disabled (NDR7 to NDR0 are not transferred to PA7 to PA0) TPC outputs TP7 to TP0 are enabled (NDR7 to NDR0 are transferred to PA7 to PA0) 1 Rev. 2.0, 06/04, page 900 of 980 NDRB--Next Data Register B * Same trigger for TPC output groups 2 and 3 Address H'FFFA4 Bit 7 NDR15 Initial value Read/Write 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W 3 NDR11 0 R/W H'FFFA4/H'FFFA6 TPC 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W Store the next output data for TPC output group 3 Store the next output data for TPC output group 2 Address H'FFFA6 Bit 7 6 5 4 3 2 1 0 Initial value Read/Write 1 1 1 1 1 1 1 1 * Different triggers for TPC output groups 2 and 3 Address H'FFFA4 Bit 7 NDR15 Initial value Read/Write 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W 1 1 1 1 3 2 1 0 Store the next output data for TPC output group 3 Address H'FFFA6 Bit 7 6 5 4 3 NDR11 Initial value Read/Write 1 1 1 1 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W Store the next output data for TPC output group 2 Rev. 2.0, 06/04, page 901 of 980 NDRA--Next Data Register A * Same trigger for TPC output groups 0 and 1 Address H'FFFA5 Bit 7 NDR7 Initial value Read/Write 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W 3 NDR3 0 R/W H'FFFA5/H'FFFA7 TPC 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W Store the next output data for TPC output group 1 Store the next output data for TPC output group 0 Address H'FFFA7 Bit 7 6 5 4 3 2 1 0 Initial value Read/Write 1 1 1 1 1 1 1 1 * Different triggers for TPC output groups 0 and 1 Address H'FFFA5 Bit 7 NDR7 Initial value Read/Write 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W 1 1 1 1 3 2 1 0 Store the next output data for TPC output group 1 Address H'FFFA7 Bit 7 6 5 4 3 NDR3 Initial value Read/Write 1 1 1 1 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W Store the next output data for TPC output group 0 Rev. 2.0, 06/04, page 902 of 980 SMR--Serial Mode Register 7 C/) Initial value Read/Write 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/0 R/W 3 STOP 0 R/W H'FFFB0 2 MP 0 R/W 1 CKS1 0 R/W SCI0 0 CKS0 0 R/W Bit Clock select 1 and 0 Bit 1 Bit 0 CKS1 CKS0 Clock Source clock /4 clock /16 clock /64 clock 0 0 1 0 1 1 Multiprocessor mode 0 1 Multiprocessor function disabled Multiprocessor format selected Stop bit length 0 1 Parity mode 0 1 Parity enable 0 1 Character length 0 1 8-bit data 7-bit data Parity bit is not added or checked Parity bit is added and checked Even parity Odd parity One stop bit Two stop bits Communication mode (for serial communication interface) 0 1 Asynchronous mode Synchronous mode GSM mode (for smart card interface) 0 1 TEND flag is set 12.5 etu* after start bit TEND flag is set 11.0 etu* after start bit Note: * etu: Elementary time unit (time required to transmit one bit) Rev. 2.0, 06/04, page 903 of 980 BRR--Bit Rate Register 7 6 5 4 3 H'FFFB1 2 1 SCI0 0 Bit Initial value Read/Write 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Serial communication bit rate setting Rev. 2.0, 06/04, page 904 of 980 SCR--Serial Control Register 7 TIE Initial value Read/Write 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W H'FFFB2 0 CKE0 0 R/W SCI0 Bit Receive enable 0 1 Receiving is disabled Receiving is enabled Transmit enable 0 1 Transmitting is disabled Transmitting is enabled Clock enable 1 and 0 (for serial communication interface) Bit 1 Bit 0 Description CKE1 CKE0 Internal clock, SCK pin Asynchronous mode available for generic I/O 0 Internal clock, SCK pin Synchronous mode used for serial clock output 0 Internal clock, SCK pin Asynchronous mode used for clock output 1 Internal clock, SCK pin Synchronous mode used for serial clock output External clock, SCK pin Asynchronous mode used for clock input 0 External clock, SCK pin Synchronous mode used for serial clock input 1 External clock, SCK pin Asynchronous mode used for clock input 1 External clock, SCK pin Synchronous mode used for serial clock input Clock enable 1 and 0 (for smart card interface) SMR Bit 1 Bit 0 Description GM CKE1 CKE0 SCK pin available for generic I/O 0 0 0 SCK pin used for clock output 1 SCK pin output fixed low 0 0 SCK pin used for clock output 1 1 SCK pin output fixed high 0 1 SCK pin used for clock output 1 Transmit-end interrupt enable 0 1 Transmit-end interrupt requests (TEI) are disabled Transmit-end interrupt requests (TEI) are enabled Multiprocessor interrupt enable 0 1 Receive interrupt enable 0 1 Receive-data-full (RXI) and receive-error (ERI) interrupt requests are disabled Receive-data-full (RXI) and receive-error (ERI) interrupt requests are enabled Multiprocessor interrupts are disabled (normal receive operation) Multiprocessor interrupts are enabled Transmit interrupt enable 0 1 Transmit-data-empty interrupt request (TXI) is disabled Transmit-data-empty interrupt request (TXI) is enabled Rev. 2.0, 06/04, page 905 of 980 TDR--Transmit Data Register H'FFFB3 SCI0 Bit 7 6 5 4 3 2 1 0 Initial value Read/Write 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Serial transmit data Rev. 2.0, 06/04, page 906 of 980 SSR--Serial Status Register 7 TDRE Initial value Read/Write 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER/ERS 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R H'FFFB4 0 MPBT 0 R/W Multiprocessor bit transfer SCI0 Bit 0 Multiprocessor bit value in transmit data is 0 1 Multiprocessor bit value in transmit data is 1 Multiprocessor bit Multiprocessor bit value in receive data is 1 Transmit end (for serial communication interface) 0 [Clearing conditions] Read TDRE when TDRE = 1, then write 0 in TDRE. The DMAC writes data in TDR. [Setting conditions] Reset or transition to standby mode TE is cleared to 0 in SCR. TDRE is 1 when last bit of 1-byte serial character is transmitted. 0 1 Multiprocessor bit value in receive data is 0 1 Transmit end (for smart card interface) 0 [Clearing conditions] Read TDRE when TDRE = 1, then write 0 in TDRE. The DMAC writes data in TDR. [Setting conditions] Reset or transition to standby mode TE is cleared to 0 in SCR and FER/ERS is cleared to 0. TDRE is 1 and FER/ERS is 0 (normal transmission) 2.5 etu*1 (when GM = 0) or 1.0 etu (when GM = 1) after 1-byte serial character is transmitted. 1 Note: *1 etu: Elementary time unit (time required to transmit one bit) Parity error 0 1 [Clearing conditions] Reset or transition to standby mode. Read PER when PER = 1, then write 0 in PER [Setting condition] Parity error (parity of receive data does not match parity setting of O/- bit in SMR) Framing error (for serial communication interface) 0 1 [Clearing conditions] Reset or transition to standby mode. Read FER when FER = 1, then write 0 in FER [Setting condition] Framing error (stop bit is 0) [Clearing conditions] Reset or transition to standby mode. Read ERS when ERS = 1, then write 0 in ERS [Setting condition] A low error signal is received Error signal status (for smart card interface) 0 1 Overrun error 0 1 [Clearing conditions] Reset or transition to standby mode. Read ORER when ORER = 1, then write 0 in ORER [Setting condition] Overrun error (reception of the next serial data ends when RDRF = 1) Receive data register full 0 1 [Clearing conditions] Reset or transition to standby mode. Read RDRF when RDRF = 1, then write 0 in RDRF The DMAC reads data from RDR [Setting condition] Serial data is received normally and transferred from RSR to RDR Transmit data register empty 0 1 [Clearing conditions] Read TDRE when TDRE = 1, then write 0 in TDRE The DMAC writes data in TDR [Setting conditions] Reset or transition to standby mode. TE is 0 in SCR Data is transferred from TDR to TSR, enabling new data to be written in TDR. Note: * Only 0 can be written, to clear the flag. Rev. 2.0, 06/04, page 907 of 980 RDR--Receive Data Register H'FFFB5 SCI0 Bit 7 6 5 4 3 2 1 0 Initial value Read/Write 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Serial receive data Rev. 2.0, 06/04, page 908 of 980 SCMR--Smart Card Mode Register 7 6 5 4 3 SDIR Initial value Read/Write 1 1 1 1 0 R/W 2 SINV 0 R/W 1 1 0 SMIF 0 R/W H'FFFB6 SCI0 Bit Smart card interface mode select 0 1 Smart card interface function is disabled Smart card interface function is enabled (Initial value) Smart card data invert Unmodified TDR contents are transmitted 0 Receive data is stored unmodified in RDR Inverted 1/0 logic levels of TDR contents are transmitted 1/0 logic levels of received data are inverted before storage in RDR (Initial value) 1 Smart card data transfer direction TDR contents are transmitted LSB-first 0 Receive data is stored LSB-first in RDR TDR contents are transmitted MSB-first Receive data is stored MSB-first in RDR (Initial value) 1 Rev. 2.0, 06/04, page 909 of 980 SMR--Serial Mode Register 7 C/) Initial value Read/Write 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/0 R/W 3 STOP 0 R/W H'FFFB8 2 MP 0 R/W 1 CKS1 0 R/W SCI1 0 CKS0 0 R/W Bit Note: Bit functions are the same as for SCI0. BRR--Bit Rate Register 7 6 5 4 3 H'FFFB9 2 1 SCI1 0 Bit Initial value Read/Write 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Note: Bit functions are the same as for SCI0. SCR--Serial Control Register 7 TIE Initial value Read/Write 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W H'FFFBA 2 TEIE 0 R/W 1 CKE1 0 R/W SCI1 0 CKE0 0 R/W Bit Note: Bit functions are the same as for SCI0. Rev. 2.0, 06/04, page 910 of 980 TDR--Transmit Data Register 7 6 5 4 3 H'FFFBB 2 1 SCI1 0 Bit Initial value Read/Write 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Note: Bit functions are the same as for SCI0. SSR--Serial Status Register 7 TDRE Initial value Read/Write 0 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER/ERS 0 R/(W)* 3 PER 0 R/(W)* H'FFFBC 2 TEND 1 R 1 MPB 0 R SCI1 0 MPBT 0 R/W Bit Notes: Bit functions are the same as for SCI0. * Only 0 can be written, to clear the flag. RDR--Receive Data Register 7 6 5 4 3 H'FFFBD 2 1 SCI1 0 Bit Initial value Read/Write 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Note: Bit functions are the same as for SCI0. Rev. 2.0, 06/04, page 911 of 980 SCMR--Smart Card Mode Register 6 5 4 3 SDIR Initial value Read/Write 1 1 1 1 0 R/W H'FFFBE 2 SINV 0 R/W 1 1 SCI1 0 SMIF 0 R/W Bit 7 Note: Bit functions are the same as for SCI0. Rev. 2.0, 06/04, page 912 of 980 SMR--Serial Mode Register 7 C/) Initial value Read/Write 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/0 R/W 3 STOP 0 R/W H'FFFC0 2 MP 0 R/W 1 CKS1 0 R/W SCI2 0 CKS0 0 R/W Bit Note: Bit functions are the same as for SCI0. BRR--Bit Rate Register 7 6 5 4 3 H'FFFC1 2 1 SCI2 0 Bit Initial value Read/Write 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Note: Bit functions are the same as for SCI0. SCR--Serial Control Register 7 TIE Initial value Read/Write 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W H'FFFC2 2 TEIE 0 R/W 1 CKE1 0 R/W SCI2 0 CKE0 0 R/W Bit Note: Bit functions are the same as for SCI0. Rev. 2.0, 06/04, page 913 of 980 TDR--Transmit Data Register 7 6 5 4 3 H'FFFC3 2 1 SCI2 0 Bit Initial value Read/Write 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Note: Bit functions are the same as for SCI0. SSR--Serial Status Register 7 TDRE Initial value Read/Write 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER/ERS 0 R/(W)* 3 PER 0 R/(W)* H'FFFC4 2 TEND 1 R 1 MPB 0 R SCI2 0 MPBT 0 R/W Bit Notes: Bit functions are the same as for SCI0. * Only 0 can be written, to clear the flag. RDR--Receive Data Register 7 6 5 4 3 H'FFFC5 2 1 SCI2 0 Bit Initial value Read/Write 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Note: Bit functions are the same as for SCI0. Rev. 2.0, 06/04, page 914 of 980 SCMR--Smart Card Mode Register 6 5 4 3 SDIR Initial value Read/Write 1 1 1 1 0 R/W H'FFFC6 2 SINV 0 R/W 1 1 SCI2 0 SMIF 0 R/W Bit 7 Note: Bit functions are the same as for SCI0. Rev. 2.0, 06/04, page 915 of 980 P1DR--Port 1 Data Register H'FFFD0 Port 1 Bit 7 P17 6 P16 0 R/W 5 P15 0 R/W 4 P14 0 R/W 3 P13 0 R/W 2 P12 0 R/W 1 P11 0 R/W 0 P10 0 R/W Initial value Read/Write 0 R/W Data for port 1 pins P2DR--Port 2 Data Register H'FFFD1 Port 2 Bit 7 P27 6 P26 0 R/W 5 P25 0 R/W 4 P24 0 R/W 3 P23 0 R/W 2 P22 0 R/W 1 P21 0 R/W 0 P20 0 R/W Initial value Read/Write 0 R/W Data for port 2 pins P3DR--Port 3 Data Register H'FFFD2 Port 3 Bit 7 P37 6 P36 0 R/W 5 P35 0 R/W 4 P34 0 R/W 3 P33 0 R/W 2 P32 0 R/W 1 P31 0 R/W 0 P30 0 R/W Initial value Read/Write 0 R/W Data for port 3 pins Rev. 2.0, 06/04, page 916 of 980 P4DR--Port 4 Data Register H'FFFD3 Port 4 Bit 7 P47 6 P46 0 R/W 5 P45 0 R/W 4 P44 0 R/W 3 P43 0 R/W 2 P42 0 R/W 1 P41 0 R/W 0 P40 0 R/W Initial value Read/Write 0 R/W Data for port 4 pins P5DR--Port 5 Data Register H'FFFD4 Port 5 Bit 7 6 5 4 3 P53 2 P52 0 R/W 1 P51 0 R/W 0 P50 0 R/W Initial value Read/Write 1 1 1 1 0 R/W Data for port 5 pins P6DR--Port 6 Data Register H'FFFD5 Port 6 Bit 7 P67 6 P66 0 R/W 5 P65 0 R/W 4 P64 0 R/W 3 P63 0 R/W 2 P62 0 R/W 1 P61 0 R/W 0 P60 0 R/W Initial value Read/Write 1 R Data for port 6 pins Rev. 2.0, 06/04, page 917 of 980 P7DR--Port 7 Data Register H'FFFD6 Port 7 Bit 7 P77 6 P76 * * R 5 P75 * R 4 P74 * R 3 P73 * R 2 P72 * R 1 P71 * R 0 P70 * R Initial value Read/Write R Data for port 7 pins Note: * Determined by pins P77 to P70. P8DR--Port 8 Data Register H'FFFD7 Port 8 Bit 7 6 5 4 P84 3 P83 0 R/W 2 P82 0 R/W 1 P81 0 R/W 0 P80 0 R/W Initial value Read/Write 1 1 1 0 R/W Data for port 8 pins Rev. 2.0, 06/04, page 918 of 980 P9DR--Port 9 Data Register H'FFFD8 Port 9 Bit 7 6 5 P95 4 P94 0 R/W 3 P93 0 R/W 2 P92 0 R/W 1 P91 0 R/W 0 P90 0 R/W Initial value Read/Write 1 1 0 R/W Data for port 9 pins PADR--Port A Data Register H'FFFD9 Port A Bit 7 PA7 6 PA6 0 R/W 5 PA5 0 R/W 4 PA4 0 R/W 3 PA3 0 R/W 2 PA2 0 R/W 1 PA1 0 R/W 0 PA0 0 R/W Initial value Read/Write 0 R/W Data for port A pins PBDR--Port B Data Register H'FFFDA Port B Bit 7 PB7 6 PB6 0 R/W 5 PB5 0 R/W 4 PB4 0 R/W 3 PB3 0 R/W 2 PB2 0 R/W 1 PB1 0 R/W 0 PB0 0 R/W Initial value Read/Write 0 R/W Data for port B pins Rev. 2.0, 06/04, page 919 of 980 ADDRA H/L--A/D Data Register A H/L H'FFFE0, H'FFFE1 A/D Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Initial value Read/Write 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R ADDRAH ADDRAL A/D conversion data 10-bit data giving an A/D conversion result ADDRB H/L--A/D Data Register B H/L H'FFFE2, H'FFFE3 A/D Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Initial value Read/Write 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R ADDRBH ADDRBL A/D conversion data 10-bit data giving an A/D conversion result Rev. 2.0, 06/04, page 920 of 980 ADDRC H/L--A/D Data Register C H/L H'FFFE4, H'FFFE5 A/D Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Initial value Read/Write 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R ADDRCH ADDRCL A/D conversion data 10-bit data giving an A/D conversion result ADDRD H/L--A/D Data Register D H/L H'FFFE6, H'FFFE7 A/D Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Initial value Read/Write 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R ADDRDH ADDRDL A/D conversion data 10-bit data giving an A/D conversion result ADCR--A/D Control Register H'FFFE9 A/D Bit 7 TRGE 6 5 4 3 2 1 0 Initial value Read/Write 0 R/W 1 1 1 1 1 R/W 1 R/W 0 R/W Trigger Enable 0 1 A/D conversion start by external trigger or 8-bit timer compare match is disabled A/D conversion is started by falling edge of external trigger signal ( ) or 8-bit timer compare match Rev. 2.0, 06/04, page 921 of 980 ADCSR--A/D Control/Status Register 7 ADF Initial value Read/Write 0 R/(W)* 6 ADIE 0 R/W 5 ADST 0 R/W 4 SCAN 0 R/W 3 CKS 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W H'FFFE8 0 CH0 0 R/W A/D Bit Channel select 2 to 0 Clock select Conversion time = Group Selection Channel Selection Description 0 134 states (maximum) CH2 CH1 CH0 Single Mode Scan Mode 0 AN0 AN0 Conversion time = 1 0 1 AN1 AN0, AN1 70 states (maximum) 0 0 AN2 AN0 to AN2 1 1 AN3 AN0 to AN3 0 AN4 AN4 0 Scan mode 1 AN5 AN4, AN5 1 Single mode 0 0 AN6 AN4 to AN6 1 1 Scan mode 1 AN7 AN4 to AN7 A/D start 0 1 A/D conversion is stopped Single mode: A/D conversion starts; ADST is automatically cleared to 0 when conversion ends Scan mode: A/D conversion starts and continues, cycling among the selected channels ADST is cleared to 0 by software, by a reset, or by a transition to standby mode A/D interrupt enable 0 1 A/D end flag 0 1 [Clearing conditions] Read ADF when ADF = 1, then write 0 in ADF The DMAC is activated by an ADI interrupt [Setting conditions] Single mode: A/D conversion ends Scan mode: A/D conversion ends in all selected channels A/D end interrupt request is disabled A/D end interrupt request is enabled Note: * Only 0 can be written, to clear the flag. Rev. 2.0, 06/04, page 922 of 980 Appendix C I/O Port Block Diagrams C.1 Port 1 Block Diagram Software standby SSOE Internal data bus (upper) Modes 1 to 4 Reset R Q P1 n DDR C WP1D Reset D Mode 7 R P1n Q P1 nDR C WP1 D Modes 1 to 5 RP1 WP1D: Write to P1DDR WP1: Write to port 1 RP1: Read port 1 SSOE: Software standby output port enable n = 0 to 7 Figure C.1 Port 1 Block Diagram Rev. 2.0, 06/04, page 923 of 980 Internal address bus Hardware standby External bus released Mode 7 C.2 Port 2 Block Diagram Software standby Reset Internal data bus (upper) SSOE R Q P2 n PCR C RP2P Mode 7 Hardware standby External bus released Reset Modes 1 to 4 R Q P2n DDR C WP2D Reset Mode 7 R Q P2 nDR C WP2 D D WP2P D P2n Modes 1 to 5 RP2 WP2P: Write to P2PCR RP2P: Read P2PCR WP2D: Write to P2DDR WP2: Write to port 2 RP2: Read port 2 SSOE: Software standby output port enable n = 0 to 7 Figure C.2 Port 2 Block Diagram Rev. 2.0, 06/04, page 924 of 980 Internal address bus C.3 Port 3 Block Diagram Internal data bus (upper) Reset Hardware standby External bus released R Mode 7 Q Write to external address P3 n DDR C WP3D Reset R Mode 7 P3n Q P3 nDR C WP3 D D Modes 1 to 5 RP3 Read external address WP3D: Write to P3DDR WP3: Write to port 3 RP3: Read port 3 n = 0 to 7 Figure C.3 Port 3 Block Diagram Rev. 2.0, 06/04, page 925 of 980 Internal data bus (lower) C.4 Port 4 Block Diagram 8-bit bus 16-bit bus mode mode Mode 7 Modes 1 to 5 Reset Internal data bus (upper) Internal data bus (lower) R Q P4 n PCR RP4P Hardware standby Write to external address External bus release Q P4 n DDR C WP4D Reset R P4n Q P4n DR C WP4 D C WP4P Reset R D D RP4 Read external address WP4P: Write to P4PCR RP4P: Read P4PCR WP4D: Write to P4DDR WP4: Write to port 4 RP4: Read port 4 n = 0 to 7 Figure C.4 Port 4 Block Diagram Rev. 2.0, 06/04, page 926 of 980 C.5 Port 5 Block Diagram Software standby SSOE Reset Q P5 n PCR RP5P C WP5P Modes 1 to 4 D Internal data bus (upper) R Hardware standby External bus released Mode 7 Reset R Q P5 n DDR C WP5D Reset R Q P5n DR C D D Mode 7 P5n Modes 1 to 5 WP5 RP5 WP5P: Write to P5PCR RP5P: Read P5PCR WP5D: Write to P5DDR WP5: Write to port 5 RP5: Read port 5 SSOE: Software standby output port enable n = 0 to 3 Figure C.5 Port 5 Block Diagram Rev. 2.0, 06/04, page 927 of 980 Internal address bus C.6 Port 6 Block Diagrams Reset Hardware standby Q P60 DDR C WP6D D Internal data bus R Bus controller WAIT input enable Mode 7 Reset R P60 Q P60 DR C WP6 D RP6 Bus controller WAIT input WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6 Figure C.6 (a) Port 6 Block Diagram (Pin P60) Rev. 2.0, 06/04, page 928 of 980 Reset Internal data bus R Hardware standby Mode 7 Q P6 1 DDR C WP6D Reset R P61 Q P61 DR C WP6 D D Bus controller Bus release enable RP6 BREQ input WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6 Figure C.6 (b) Port 6 Block Diagram (Pin P61) Rev. 2.0, 06/04, page 929 of 980 Reset Hardware standby Q P6 2 DDR C WP6D Reset R P62 Q P62 DR C Mode 7 WP6 D Bus controller Bus release enable BACK output R D RP6 WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6 Figure C.6 (c) Port 6 Block Diagram (Pin P62) Rev. 2.0, 06/04, page 930 of 980 Internal data bus SSOE Software standby Mode 7 Hardware standby External bus released Reset R Q P6 3 DDR C WP6D Reset R Mode 7 D Internal data bus Mode 7 P63 Q Modes 1 to 5 P6 3DR C WP6 D Bus controller AS output RP6 WP6D: WP6: RP6: SSOE: Write to P6DDR Write to port 6 Read port 6 Software standby output port enable Figure C.6 (d) Port 6 Block Diagram (Pin P63) Rev. 2.0, 06/04, page 931 of 980 SSOE Software standby Mode 7 Hardware standby External bus released Reset R Q P6 4 DDR C WP6D Reset R Mode 7 D Internal data bus Mode 7 P64 Modes 1 to 5 Q P6 4DR C WP6 D Bus controller WE output enable RD output WE output RP6 WP6D: WP6: RP6: SSOE: Write to P6DDR Write to port 6 Read port 6 Software standby output port enable Figure C.6 (e) Port 6 Block Diagram (Pin P64) Rev. 2.0, 06/04, page 932 of 980 SSOE Software standby Mode 7 Hardware standby External bus released Reset R Q P6 n DDR C WP6D Reset R Mode 7 D Internal data bus Mode 7 P6n Modes 1 to 5 Q P6 nDR C WP6 D Bus controller CAS output enable HWR output LWR output UCAS output LCAS output RP6 WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6 SSOE: Software standby output port enable n = 5 and 6 Figure C.6 (f) Port 6 Block Diagram (Pins P65 and P66) Rev. 2.0, 06/04, page 933 of 980 Hardware standby output enable Internal data bus P67 output RP6 RP6: Read port 6 Figure C.6 (g) Port 6 Block Diagram (Pin P67) Rev. 2.0, 06/04, page 934 of 980 C.7 Port 7 Block Diagrams RP7 P7n Internal data bus A/D converter Analog input RP7: Read port 7 n = 0 to 5 Input enable Channel select signal Figure C.7 (a) Port 7 Block Diagram (Pins P70 to P75) RP7 P7n Internal data bus A/D converter Analog input Input enable Channel select signal D/A converter Output enable Analog output RP7: Read port 7 n = 6 and 7 Figure C.7 (b) Port 7 Block Diagram (Pins P76 and P77) Rev. 2.0, 06/04, page 935 of 980 C.8 Port 8 Block Diagrams Hardware standby Q P8 0 DDR C D WP8D Reset R P80 Q P80 DR C Mode 7 WP8 D Internal data bus SSOE Software standby External bus released Reset R Bus controller Self-refresh output enable RFSH output enable RFSH output RP8 Interrupt controller WP8D: WP8: RP8: SSOE: Write to P8DDR Write to port 8 Read port 8 Software standby output port enable IRQ 0 input Figure C.8 (a) Port 8 Block Diagram (Pin P80) Rev. 2.0, 06/04, page 936 of 980 SSOE Software standby External bus release Reset R Hardware standby Q P8 1 DDR C WP8D Mode 7 Q P81 DR C WP8 CS3 output RAS3 output RAS3 output enable Area 3 DRAM connection enable Bus controller Reset R P8n Modes 1 to 5 D D RP8 Interrupt controller Internal data bus IRQ1 input WP8D: WP8: RP8: SSOE: Write to P8DDR Write to port 8 Read port 8 Software standby output port enable Figure C.8 (b) Port 8 Block Diagram (Pin P81) Rev. 2.0, 06/04, page 937 of 980 SSOE Software standby External bus release Reset Hardware standby R Q P8 2 DDR C WP8D Reset Mode 7 P82 Modes 1 to 5 Q P82 DR C WP8 CS2 output RAS2 output RAS2 output enable Bus controller R D D RP8 Interrupt controller Internal data bus IRQ2 input WP8D: WP8: RP8: SSOE: Write to P8DDR Write to port 8 Read port 8 Software standby output port enable Figure C.8 (c) Port 8 Block Diagram (Pin P82) Rev. 2.0, 06/04, page 938 of 980 Mode 7 Software standby SSOE External bus release Reset R Q D P83DDR C WP8D CS1 output Reset Hardware standby Internal data bus Bus controller Mode 7 P83 Modes 1 to 5 R Q D P83DR C WP8 RP8 Interrupt controller IRQ3 input A/D converter ADTRG input WP8D: WP8: RP8: SSOE: Write to P8DDR Write to port 8 Read port 8 Software standby output port enable Figure C.8 (d) Port 8 Block Diagram (Pin P83) Rev. 2.0, 06/04, page 939 of 980 Reset Modes 1 to 4 Mode 7 Software standby S Q R D Internal data bus SSOE External bus release Hardware standby P8 4 DDR C WP8D Reset R Bus controller CS 0 output Mode 7 P84 Modes 1 to 5 Q P84 DR C WP8 D RP8 WP8D: WP8: RP8: SSOE: Write to P8DDR Write to port 8 Read port 8 Software standby output port enable Figure C.8 (e) Port 8 Block Diagram (Pin P84) Rev. 2.0, 06/04, page 940 of 980 C.9 Port 9 Block Diagrams Reset Q P9 0 DDR C WP9D Reset R P90 Q P90 DR C WP9 D D SCI Output enable Serial transmit data Guard time RP9 WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Figure C.9 (a) Port 9 Block Diagram (Pin P90) Rev. 2.0, 06/04, page 941 of 980 Internal data bus Hardware standby R Reset Internal data bus Hardware standby Q R D P9 1 DDR C WP9D Reset R P91 Q P91 DR C WP9 D SCI Output enable Serial transmit data Guard time RP9 WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Figure C.9 (b) Port 9 Block Diagram (Pin P91) Rev. 2.0, 06/04, page 942 of 980 Reset R Hardware standby Q P9 2 DDR C WP9D Reset R P9 2 Q P9 2 DR C WP9 D D Internal data bus SCI Input enable RP9 Serial receive data WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Figure C.9 (c) Port 9 Block Diagram (Pin P92) Rev. 2.0, 06/04, page 943 of 980 Reset R Q D P93DDR C WP9D Reset P93 R Q D P93DR C WP9 Hardware standby Internal data bus SCI Input enable Serial receive data RP9 WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Figure C.9 (d) Port 9 Block Diagram (Pin P93) Rev. 2.0, 06/04, page 944 of 980 Reset R Hardware standby Q P9 4DDR C WP9D Reset R P94 Q P9 4 DR C WP9 Clock output enable Clock output D D Internal data bus SCI Clock input enable RP9 Clock input WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Interrupt controller IRQ 4 input Figure C.9 (e) Port 9 Block Diagram (Pin P94) Rev. 2.0, 06/04, page 945 of 980 Reset Hardware standby R Q D P95DDR C WP9D Reset P95 R Q D P95DR C WP9 Internal data bus SCI Clock input enable Clock output enable Clock output RP9 Clock input Interrupt controller IRQ5 input WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Figure C.9 (f) Port 9 Block Diagram (Pin P95) Rev. 2.0, 06/04, page 946 of 980 C.10 Port A Block Diagrams Reset Hardware standby Q PA n DDR C WPAD Reset R R D Internal data bus TPC PA n Q PA n DR C D TPC output enable Next data WPA Output trigger DMA controller Output enable Transfer end output RPA 16-bit timer Counter clock input 8-bit timer Counter clock input WPAD: Write to PADDR WPA: Write to port A RPA: Read port A n = 0 and 1 Figure C.10 (a) Port A Block Diagram (Pins PA0, PA1) Rev. 2.0, 06/04, page 947 of 980 Reset Hardware standby Q PA n DDR C WPAD Reset R PA n Q PA n DR C D R D Internal data bus TPC TPC output enable Next data WPA Output trigger 16-bit timer Output enable Compare match output RPA Input capture Counter clock input 8-bit timer Counter clock input WPAD: Write to PADDR WPA: Write to port A RPA: Read port A n = 2 and 3 Figure C.10 (b) Port A Block Diagram (Pins PA2, PA3) Rev. 2.0, 06/04, page 948 of 980 Software standby Bus released SSOE Hardware standby Q R D PAnDDR C WPAD Reset R Internal address bus Internal data bus Address output enable Mode 3/4 Reset TPC PA n TPC output enable D Next data Q PAnDR C WPA Output trigger 16-bit timer Output enable Compare match output PRA Input capture WPAD: Write to PADDR WPA: Write to port A RPA: Read port A SSOE: Software standby output port enable n = 4 to 7 Note: The PA7 address output enable setting is fixed at 1 in modes 3 and 4. Figure C.10 (c) Port A Block Diagram (Pins PA4 to PA7) Rev. 2.0, 06/04, page 949 of 980 C.11 Port B Block Diagrams Hardware standby Q R D PB 0 DDR C Internal data bus Software standby SSOE Reset Bus controller CS7 output CS output enable TPC TPC output enable Bus released WPBD Reset PB 0 Modes 1 to 5 Q PB 0 DR C R D Next data WPB Output trigger 8-bit timer Output enable Compare match output RPB WPBD: WPB: RPB: SSOE: Write to PBDDR Write to port B Read port B Software standby output port enable Figure C.11 (a) Port B Block Diagram (Pin PB0) Rev. 2.0, 06/04, page 950 of 980 Software standby Reset SSOE Hardware R standby Q D PB1DDR C Bus released Modes 1 to 5 WPBD Reset R Q D PB1DR C WPB Internal data bus Bus controller CS6 output PB1 CS output enable TPC TPC output enable Next data Output trigger 8-bit timer Output enable Compare match output RPB TMO2 TMO3 input DMAC DREQ0 DREQ1 input WPBD: WPB: RPB: SSOE: Write to PBDDR Write to port B Read port B Software standby output port enable Figure C.11 (b) Port B Block Diagram (Pin PB1) Rev. 2.0, 06/04, page 951 of 980 SSOE Software standby External bus release Reset Hardware standby R Q D PB2DDR C WPBD Internal data bus Bus controller RAS5 output enable Area 5 DRAM connection output enable RAS5 output PB2 Mode 7 Reset R Q D PB2DR C CS5 output CS5 output enable TPC TPC output enable Next data WPB Output trigger 8-bit timer Output enable Compare match output RPB WPBD: WPB: RPB: SSOE: Write to PBDDR Write to port B Read port B Software standby output port enable Note: Area 5 DRAM connection output enable, RAS5 output enable, and CS5 output enable are all fixed at 0 in mode 7. Figure C.11 (c) Port B Block Diagram (Pin PB2) Rev. 2.0, 06/04, page 952 of 980 SSOE Software standby External bus release Reset Hardware standby R Q D PB3DDR C WPBD Internal data bus Bus controller RAS4 output enable Area 4 DRAM connection output enable RAS4 output PB3 Mode 7 Reset R Q D PB3DR C CS4 output CS4 output enable TPC TPC output enable Next data WPB Output trigger 8-bit timer Output enable Compare match output RPB TMIO3 input DMAC DREQ1 input WPBD: WPB: RPB: SSOE: Write to PBDDR Write to port B Read port B Software standby output port enable Note: Area 4 DRAM connection output enable, RAS4 output enable, and CS4 output enable are all fixed at 0 in mode 7. Figure C.11 (d) Port B Block Diagram (Pin PB3) Rev. 2.0, 06/04, page 953 of 980 Hardware standby External bus release SSOE Software standby R Q PB 4 DDR C WPBD Reset R PB4 Q PB 4 DR C D D Internal data bus WPB Reset TPC TPC output enable Next data Output trigger Bus controller Output enable CAS output RPB WPBD: WPB: RPB: SSOE: Write to PBDDR Write to port B Read port B Software standby output port enable Note: In mode 7, CAS output enable is fixed at 0. Figure C.11 (e) Port B Block Diagram (Pin PB4) Rev. 2.0, 06/04, page 954 of 980 External bus release Software standby SSOE Internal data bus Hardware standby Reset R Q D PB5DDR C WPBD Reset R Q D PB5DR C WPB SCI Clock input enable TPC TPC output enable PB5 Next data Output trigger Bus controller CAS output enable CAS output SCI Clock output enable Clock output RPB Clock input Note: In mode 7, CAS output enable is fixed at 0. Write to PBDDR Write to port B Read port B Software standby output port enable WPBD: WPB: RPB: SSOE: Figure C.11 (f) Port B Block Diagram (Pin PB5) Rev. 2.0, 06/04, page 955 of 980 Hardware standby Q R PB 6 DDR C WPBD Reset R D Internal data bus WPB Reset TPC PB6 Q PB6 DR C D TPC output enable Next data Output trigger SCI Output enable Serial transmit data Guard time RPB WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B Figure C.11 (g) Port B Block Diagram (Pin PB6) Rev. 2.0, 06/04, page 956 of 980 R Hardware standby Q PB 7 DDR C WPBD Reset R PB7 Q PB7 DR C D D Internal data bus WPB Reset SCI Input enable TPC TPC output enable Next data Output trigger RPB SCI WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B Serial receive data Figure C.11 (h) Port B Block Diagram (Pin PB7) Rev. 2.0, 06/04, page 957 of 980 Appendix D Pin States D.1 Port States in Each Mode Port States Hardware Standby Software Standby Reset Mode Mode L T (SSOE=0) T (SSOE=1) Keep (DDR = 0) Keep (DDR=1, SSOE=0) T (DDR=1, SSOE=1) Keep Keep (SSOE = 0) T (SSOE = 1) Keep (DDR = 0) Keep (DDR=1,SSOE=0) T (DDR=1,SSOE=1) Keep Keep T Keep Keep T Keep Bus-Released Mode T Program Execution Mode A7 to A0 Table D.1 Pin Name Mode P17 to 1 to 4 P10 5 T T T (DDR=0) Input port (DDR=1) A7 to A0 7 P27 to 1 to 4 P20 T L T T -- T I/O port A15 to A8 5 T T T (DDR=0) Input port (DDR=1) A15 to A8 7 P37 to 1 to 5 P30 7 T T T T T T T T T -- T -- Keep T -- I/O port D15 to D8 I/O port I/O port D7 to D0 I/O port P47 to 1, 3, 5 T P40 2, 4 7 T T Rev. 2.0, 06/04, page 958 of 980 Pin Name Mode Hardware Standby Software Standby Reset Mode Mode L T (SSOE=0) T (SSOE=1) Keep (DDR=0) Keep (DDR=1, SSOE=0) T (DDR=1, SSOE=1) Keep Keep Keep Keep (BRLE=0) Keep (BRLE=1) T Keep (BRLE=0) Keep (BRLE=1) H Keep (SSOE=0) T (SSOE=1) H Keep (PSTOP=0) H (PSTOP=1) Keep (PSTOP=0) H (PSTOP=1) Keep T Bus-Released Mode T Program Execution Mode A19 to A16 P53 to 1 to 4 P50 5 T T T (DDR=0) Input port (DDR=1) A19 to A16 7 P60 1 to 5 7 P61 1 to 5 T T T T T T T T -- Keep -- T I/O port I/O port WAIT I/O port I/O port BREQ 7 P62 1 to 5 T T T T -- L I/O port (BRLE=0) I/O port (BRLE=1) BACK I/O port AS, RD, HWR, LWR 7 P66 to 1 to 5 P63 T H T T -- T 7 P67 1 to 5 T T -- (PSTOP=0) (PSTOP=1) Keep (PSTOP=0) (PSTOP=1) Keep T I/O port (PSTOP=0) (PSTOP=1) Input port (PSTOP=0) (PSTOP=1) Input port Input port Clock T output 7 T T P77 to 1 to P70 5, 7 T T Rev. 2.0, 06/04, page 959 of 980 Pin Name P80 Mode 1 to 5 Hardware Standby Software Standby Reset Mode Mode T T When DRAM space is not selected*1 (RFSHE=0) Keep (RFSHE=1) Illegal setting When DRAM space is selected*2 (RFSHE=0) Keep (RFSHE=1, SRFMD=0, SSOE=0) T (RFSHE=1, SRFMD=0, SSOE=1) H (RFSHE=1, SRFMD=1) RFSH Keep When DRAM space is selected and RAS3 is output*3 (SSOE=0) T (SSOE=1) H When DRAM space is selected and RAS3 is not output*4 Keep Otherwise*5 *1 (DDR=0) T (DDR=1, SSOE=0) T (DDR=1, SSOE=1) H Keep Bus-Released Mode When DRAM space is selected*1 (RFSHE=0) Keep (RFSHE=1) Illegal setting When DRAM space is selected*2 (RFSHE=0) Keep (RFSHE=1) T Program Execution Mode (RFSHE=0) I/O port (RFSHE=1) RFSH 7 P81 1 to 5 T T T T -- When DRAM space is selected and RAS3 is output*3 T When DRAM space is selected and RAS3 is not output *4 Keep Otherwise*1 (DDR=0) Keep (DDR=1) T I/O port When DRAM space is selected and RAS3 is output RAS3 When DRAM space is selected and RAS3 is not output I/O port Otherwise (DDR=0) Input port (DDR=1) CS3 7 T T -- I/O port Rev. 2.0, 06/04, page 960 of 980 Pin Name P82 Mode 1 to 5 Hardware Standby Software Standby Reset Mode Mode T T RAS2 output*2 (SSOE=0) T (SSOE=1) H Otherwise*1 (DDR=0) T (DDR=1, SSOE=0) T (DDR=1, SSOE=1) H Keep (DDR=0) T (DDR=1, SSOE=0) T (DDR=1, SSOE=1) H Keep (DDR=0) T (DDR=1, SSOE=0) T (DDR=1, SSOE=1) H (DDR=0) T (DDR=1, SSOE=0) T (DDR=1, SSOE=1) H Keep Keep Keep Keep Bus-Released Mode RAS2 output*2 T Otherwise*1 (DDR=0) Keep (DDR=1) T Program Execution Mode RAS2 output RAS2 Otherwise (DDR=0) I/O port (DDR=1) CS2 7 P83 1 to 5 T T T T -- (DDR=0) Keep (DDR=1) T I/O port (DDR=0) Input port (DDR=1) CS1 7 P84 1 to 4 T H T T -- (DDR = 0) Keep (DDR = 1) T I/O port (DDR = 0) Input port (DDR = 1) CS0 5 T T (DDR=0) Keep (DDR=1) T (DDR=0) Input port (DDR=1) CS0 7 P95 to 1 to P90 5, 7 PA3 to 1 to PA0 5, 7 T T T T T T T -- Keep Keep Keep I/O port I/O port I/O port I/O port PA6 to 1, 2, 7 T PA4 Rev. 2.0, 06/04, page 961 of 980 Pin Name Mode Hardware Standby Software Standby Reset Mode Mode T T Address output*5 (SSOE=0) T (SSOE=1) Keep Otherwise*6 Keep Keep (SSOE=0) T (SSOE=1) Keep When A20E = 0 SSOE = 0 T SSOE = 1 Keep When A20E = 1 Keep Keep CS output*7 (SSOE=0) T (SSOE=1) H Otherwise*8 Keep Keep RAS5 output*9 (SSOE=0) T (SSOE=1) H CS output*10 (SSOE=0) T (SSOE=1) H Otherwise*11 Keep Keep Bus-Released Mode Address output*5 T Otherwise*6 Keep Program Execution Mode Address output A23 to A21 Otherwise I/O port PA6 to 3 to 5 PA4 PA7 1, 2 3, 4 T L T T Keep T I/O port A20 5 L T When A20E = 0 T When A20E = 1 Keep When A20E = 0 A20 When A20E = 1 I/O port 7 PB1, PB0 1 to 5 T T T T -- CS output*7 T Otherwise*8 Keep I/O port CS output CS7, CS6 Otherwise I/O port 7 PB2 1 to 5 T T T T -- RAS5 output*9 T CS output*10 T Otherwise*11 Keep I/O port RAS5 output RAS5 CS output CS5 Otherwise I/O port 7 T T -- I/O port Rev. 2.0, 06/04, page 962 of 980 Pin Name PB3 Mode 1 to 5 Hardware Standby Software Standby Reset Mode Mode T T RAS4 output*12 (SSOE=0) T (SSOE=1) H CS output*13 (SSOE=0) T (SSOE=1) H Otherwise*14 Keep Keep CAS (SSOE=0) T (SSOE=1) H Otherwise*16 Keep Keep Keep output*15 Bus-Released Mode RAS4 output*12 T CS output*13 T Otherwise*14 Keep Program Execution Mode RAS4 output RAS4 CS output CS4 Otherwise I/O port 7 PB5, PB4 1 to 5 T T T T -- CAS T Otherwise*16 Keep output*15 I/O port CAS output UCAS, LCAS Otherwise I/O port 7 PB7, PB6 1 to 5, 7 T T T T -- Keep I/O port I/O port Legend H: High L: Low T: High-impedance state Keep: Input pins are in the high-impedance state; output pins maintain their previous state. DDR: Data direction register Notes: *1 When bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control register A) are all cleared to 0. *2 When any of bits DRAS2, DRAS1, or DRAS0 in DRCRA (DRAM control register A) is set to 1. *3 When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control register A) is 010, 100, or 101. *4 When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control register A) is other than 010, 100, 101, or 000. *5 When bit A23E, A22E, or A21E, respectively, in BRCR (bus release control register) is cleared to 0. *6 When bit A23E, A22E, or A21E, respectively, in BRCR (bus release control register) is set to 1. *7 When bit CS7E or CS6E, respectively, in CSCR (chip select control register) is set to 1. *8 When bit CS7E or CS6E, respectively, in CSCR (chip select control register) is cleared to 0. Rev. 2.0, 06/04, page 963 of 980 *9 When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control register A) is 101. *10 When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control register A) is other than 101, and bit CS5E in CSCR (chip select control register) is set to 1. *11 When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control register A) is other than 101, and bit CS5E in CSCR (chip select control register) is cleared to 0. *12 When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control register A) is 100, 101, or 110. *13 When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control register A) is other than 100, 101, or 110, and bit CS4E in CSCR (chip select control register) is set to 1. *14 When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control register A) is other than 100, 101, or 110, and bit CS4E in CSCR (chip select control register) is cleared to 0. *15 When any of bits DRAS2, DRAS1, or DRAS0 in DRCRA (DRAM control register A) is set to 1, and bit CSEL in DRCRB (DRAM control register B) is cleared to 0. *16 When any of bits DRAS2, DRAS1, or DRAS0 in DRCRA (DRAM control register A) is set to 1, and bit CSEL in DRCRB (DRAM control register B) is set to 1; or, when bits DRAS2, DRAS1, and DRAS0 are all cleared to 0. Rev. 2.0, 06/04, page 964 of 980 D.2 Pin States at Reset Modes 1 and 2: Figure D.1 is a timing diagram for the case in which RES goes low during an external memory access in mode 1 or 2. As soon as RES goes low, all ports are initialized to the input state. AS, RD, HWR, LWR, and CS0 go high, and D15 to D0 go to the high-impedance state. The address bus is initialized to the low output level 2.5 clock cycles after the low level of RES is sampled. Clock pin P67/ goes to the output state at the next rise of after RES goes low. Access to external memory T1 P67/ T2 T3 RES Internal reset signal A19 to A0 H'00000 CS0 AS, RD (read) HWR, LWR (write) D15 to D0 (write) I/O port, CS7 to CS1 High impedance High impedance Figure D.1 Reset during Memory Access (Modes 1 and 2) Rev. 2.0, 06/04, page 965 of 980 Modes 3 and 4: Figure D.2 is a timing diagram for the case in which RES goes low during an external memory access in mode 3 or 4. As soon as RES goes low, all ports are initialized to the input state. AS, RD, HWR, LWR, and CS0 go high, and D15 to D0 go to the high-impedance state. The address bus is initialized to the low output level 2.5 clock cycles after the low level of RES is sampled. However, when PA4 to PA6 are used as address bus pins, or when P83 to P81 and PB0 to PB3 are used as CS output pins, they go to the high-impedance state at the same time as RES goes low. Clock pin P67/ goes to the output state at the next rise of after RES goes low. Access to external memory T1 P67/ T2 T3 RES Internal reset signal A20 to A0 H'000000 CS0 AS, RD (read) HWR, LWR (write) D15 to D0 (write) I/O port, PA4/A23 to PA6/A21, CS7 to CS1 High impedance High impedance Figure D.2 Reset during Memory Access (Modes 3 and 4) Mode 5: Figure D.3 is a timing diagram for the case in which RES goes low during an external memory access in mode 5. As soon as RES goes low, all ports are initialized to the input state. AS, RD, HWR, and LWR go high, and the address bus and D15 to D0 go to the high-impedance state. Clock pin P67/ goes to the output state at the next rise of after RES goes low. Rev. 2.0, 06/04, page 966 of 980 Access to external memory T1 P67/ T2 T3 RES Internal reset signal A23 to A0 High impedance AS, RD (read) HWR, LWR (write) D15 to D0 (write) I/O port, CS7 to CS1 High impedance High impedance Figure D.3 Reset during Memory Access (Mode 5) Mode 7: Figure D.4 is a timing diagram for the case in which RES goes low during an operation in mode 7. As soon as RES goes low, all ports and clock pin P67/ are initialized to the input state. High impedance P67/ 4-5 Internal reset signal I/O port High impedance Figure D.4 Reset during Operation (Mode 7) Rev. 2.0, 06/04, page 967 of 980 Appendix E Timing of Transition to and Recovery from Hardware Standby Mode Timing of Transition to Hardware Standby Mode 1. To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low 10 system clock cycles before the STBY signal goes low, as shown below. RES must remain low until STBY goes low (minimum delay from STBY low to RES high: 0 ns). STBY t1 10tcyc RES t2 0 ns 2. To retain RAM contents with the RAME bit cleared to 0 in SYSCR, RES does not have to be driven low as in (1). Timing of Recovery from Hardware Standby Mode: Drive the RES signal low approximately 100 ns before STBY goes high. STBY t 100 ns RES tOSC Rev. 2.0, 06/04, page 968 of 980 Appendix F Product Code Lineup F.1 H8/3029 Product Code Lineup Product Code (Catalog Package Code) Regular product code (Internal Product Code) HD64F3029F25 HD64F3029F25W HD64F3029FBL25 HD64F3029X25 HD64F3029X25W HD64F3029XBL25 100-pin TQFP (TFP-100B) Product Type Package (Package Code) 100-pin QFP (FP-100B) H8/3029 On-chip flash HD64F3029F25 memory HD64F3029F25W HD64F3029FBL25 HD64F3029TE25 HD64F3029TE25W HD64F3029TEBL25W Rev. 2.0, 06/04, page 969 of 980 Appendix G Package Dimensions Figures G.1 show the FP-100B package dimensions of the H8/3029. Figure G.2 shows the TFP100B package dimensions. 16.0 0.3 14 As of July, 2002 Unit: mm 51 50 75 76 16.0 0.3 100 1 *0.22 0.05 0.20 0.04 25 26 0.5 3.05 Max 2.70 0.08 M 1.0 *0.17 0.05 0.15 0.04 1.0 0 - 8 0.5 0.2 0.10 0.12 +0.13 -0.12 *Dimension including the plating thickness Base material dimension Package Code JEDEC JEITA Mass (reference value) FP-100B -- Conforms 1.2 g Figure G.1 Package Dimensions (FP-100B) Rev. 2.0, 06/04, page 970 of 980 As of July, 2002 16.0 0.2 14 75 76 51 50 Unit: mm 16.0 0.2 100 1 *0.22 0.05 0.20 0.04 25 0.08 M 1.0 26 0.5 *0.17 0.05 0.15 0.04 1.00 1.20 Max 1.0 0 - 8 0.5 0.1 0.10 0.10 0.10 *Dimension including the plating thickness Base material dimension Package Code JEDEC JEITA Mass (reference value) TFP-100B -- Conforms 0.5 g Figure G.2 Package Dimensions (TFP-100B) Rev. 2.0, 06/04, page 971 of 980 Appendix H Comparison of H8/300H Series Product Specifications H.1 Differences between H8/3029, H8/3069R, H8/3067 Group and H8/3062 Group, H8/3048 Group, H8/3007 and H8/3006, and H8/3002 Item 1 Operating mode Mode 5 H8/3069R, H8/3029 16 Mbytes ROM enabled expanded mode -- H8/3067 Group, H8/3062 Group 16 Mbytes ROM enabled expanded mode H8/3048 Group 1 Mbyte ROM enabled expanded mode H8/3007, H8/3006 H8/3002 Mode 6 64 kbytes single-chip 16 Mbyte mode ROM enabled expanded mode 36 (H8/3067) 27 (H8/3062) Yes (H8/3067) No (H8/3062) Yes 30 36 30 2 Interrupt controller Bus controller Internal interrupt sources 36 3 Burst ROMYes interface Idle cycle Yes insertion function Wait mode 2 modes Wait state Per area number setting Address output method Choice of address update fixed No Yes No No Yes No 2 modes Per area 4 modes Common to all areas 2 modes Per area 4 modes Common to all areas Fixed Choice of address Fixed update mode (fixed in H8/3067F-ZTAT and H8/3062F-ZTAT) Area 2/3/4/5 (H8/3067 only) Area 3 Fixed 4 DRAM interface Connect- Area 2/3/4/5 able areas Area 2/3/4/5 Area 3 Rev. 2.0, 06/04, page 972 of 980 Item 4 DRAM interface H8/3069R, H8/3029 Precharge Yes cycle insertion function Fast page Yes mode Address shift amount 8 bit/9 bit/10 bit H8/3067 Group, H8/3062 Group Yes (H8/3067 only) H8/3048 H8/3007, Group H8/3006 No Yes H8/3002 No Yes (H8/3067 only) 8 bit/9 bit/10 bit (H8/3067 only) 16-bit timers 8-bit timers No Yes No 8-bit/9-bit 8 bit/9 bit 8-bit/9-bit/10-bit 5 Timer functions 16-bit timers 8-bit timers ITU 16-bit timers 8-bit timers ITU Number of 16 bits x 3 8 bits x 4 16 bits x 3 8 bits x 4 16 bits x 5 16 bits x 3 8 bits x 4 16 bits x 5 channels (16 bits x (16 bits x (16 bits x 2) 2) 2) Pulse output Input capture External clock Internal clock Complementary PWM function 6 pins 6 4 pins (2 pins) 2 6 pins 6 4 pins (2 pins) 2 12 pins 10 6 pins 6 4 pins (2 pins) 2 12 pins 10 4 systems 4 systems 4 systems 4 systems 4 systems 4 systems 4 systems 4 systems (select(fixed) (select(fixed) (select(select(fixed) (selectable) able) able) able) able) , /2, /4, /8, /64, , /2, /4, /8, /64, , /2, /4, , /2, /4, /8, /64, , /2, /4, /8 /8192 /8 /8192 /8 /8 /8192 /8 No No No No Yes No No Yes ResetNo synchronous PWM function Buffer No operation Output initialization function Yes No No No Yes No No Yes No No No Yes No No Yes No Yes No No Yes No No Rev. 2.0, 06/04, page 973 of 980 Item 5 Timer functions PWM output H8/3069R, H8/3029 3 4 (2) H8/3067 Group, H8/3062 Group 3 4 (2) H8/3048 H8/3007, Group H8/3006 5 3 4 (2) H8/3002 5 4 channels DMAC 3 channels No activation 3 channels No (H8/3067 only) No Yes 4 channels 3 channels No A/D No conversion activation Interrupt sources 6 TPC Yes No No Yes No 3 sources 8 sources 3 sources 8 sources 3 sources 3 sources 8 sources 3 sources x3 x3 x5 x3 x5 3 kinds, 16-bit timer base 4 kinds, 3 kinds, 16-bit timer ITU base base 4 kinds, ITU base Time base 3 kinds, 16-bit timer base 7 WDT Reset signal external output function No Yes (except products with onchip flash memory) Yes Yes Yes Yes 8 SCI Number of 3 channels channels Smart card Supported on all interface channels 3 channels (H8/3067) 2 channels 3 channels 2 channels (H8/3062) Supported on all channels Supported Supported on all on SCI0 channels only 2 channels No Rev. 2.0, 06/04, page 974 of 980 Item 9 A/D converter H8/3069R, H8/3029 H8/3067 Group, H8/3062 Group H8/3048 H8/3007, Group H8/3006 H8/3002 Conversion External trigger/8-bit External trigger/8-bit External start trigger timer compare match timer compare match trigger input Conversion 70/134 state 70/134 /input port multiplexing A20 / I/O port multiplexing 134/266 output only A20 output External trigger/8-bit External timer compare match trigger 70/134 /input port multiplexing 134/266 output only 10 Pin control pin A20 in 16 MB ROM enabled expanded mode /input port multiplexing A20 / I/O port multiplexing High-level Address High-level High-level High-level High-level output bus, output/highoutput/highoutput output/highAS, RD, impedance selectable impedance selectable (except impedance selectable (except HWR, LWR, CS 0) (RFSH: H8/3067 only) CS0) CS7-CS0, Low-level Low-level RFSH in output output software (CS0) (CS 0) standby state CS7-CS0 in busreleased state 11 Flash memory functions Program/ erase voltage High-impedance High-impedance High-level High-impedance output High-level output 12 V application unnecessary. Single-power-supply programming. 16 blocks 12 V application unnecessary. Single-power-supply programming. 12 V application from offchip Block divisions 8 blocks (12 blocks in 16 blocks H8/3064F-ZTAT) Yes Yes Yes Yes Boot mode Yes User program mode User boot mode Yes Yes No No Rev. 2.0, 06/04, page 975 of 980 H.2 Comparison of Pin Functions of 100-Pin Package Products (FP-100B, TFP-100B) Pin Arrangement of Each Product (FP-100B, TFP-100B) ROMless Version Table H.1 H8/3069R, Pin No. H8/3029 1 2 3 VCL PB0/TP8/ TMO0/CS7 PB1/TP9/ TMIO1/ DREQ0/CS6 PB2/TP10/TM O2/ CS5 PB3/TP11/ TMIO3/ DREQ1/CS4 PB4/TP12/ UCAS PB5/TP13/ LCAS/ SCK2 PB6/TP14/ TxD2 PB7/TP15/ RxD2 FWE Vss P90/TxD0 P91/TxD1 P92/RxD0 P93/RxD1 P94/SCK0/ IRQ4 P95/SCK1/ IRQ5 P40/D0 P41/D1 H8/3067 Group VCC PB0/TP8/ TMO0/CS7 PB1/TP9/ TMIO1/ DREQ0/CS6 PB2/TP10/TM O2/ CS5 PB3/TP11/ TMIO3/ DREQ1/CS4 PB4/TP12/ UCAS PB5/TP13/ LCAS/ SCK2 PB6/TP14/ TxD2 PB7/TP15/ RxD2 RESO/ FWE*1 Vss P90/TxD0 P91/TxD1 P92/RxD0 P93/RxD1 P94/SCK0/ IRQ4 P95/SCK1/ IRQ5 P40/D0 P41/D1 H8/3062 Group VCC/VCL* PB0/TP8/ TMO0/CS7 PB1/TP9/ TMIO1/CS6 PB2/TP10/TM O2/ CS5 PB3/TP11/ TMIO3/CS4 PB4/TP12 PB5/TP13 2 H8/3048 Group VCC PB0/TP8/ TIOCA3 PB1/TP9/ TIOCB3 PB2/TP10/ TIOCA4 PB3/TP11/ TIOCB4 PB4/TP12/ TOCXA4 PB5/TP13/ TOCXB4 PB6/TP14/ DREQ0/ CS7 PB7/TP15/ DREQ1/ ADTRG RESO/VPP Vss P90/TxD0 P91/TxD1 P92/RxD0 P93/RxD1 P94/SCK0/ IRQ4 P95/SCK1/ IRQ5 P40/D0 P41/D1 H8/3042 Group VCC PB0/TP8/ TIOCA3 PB1/TP9/ TIOCB3 PB2/TP10/ TIOCA4 PB3/TP11/ TIOCB4 PB4/TP12/ TOCXA4 PB5/TP13/ TOCXB4 PB6/TP14/ DREQ0 PB7/TP15/ DREQ1/ ADTRG RESO Vss P90/TxD0 P91/TxD1 P92/RxD0 P93/RxD1 P94/SCK0/ IRQ4 P95/SCK1/ IRQ5 P40/D0 P41/D1 H8/3007, H8/3006 VCC PB0/TP8/ TMO0/CS7 PB1/TP9/ TMIO1/ DREQ0/CS6 PB2/TP10/ TMO2/CS5 PB3/TP11/ TMIO3/ DREQ1/CS4 PB4/TP12/ UCAS PB5/TP13/ LCAS/SCK2 PB6/TP14/ TxD2 PB7/TP15/ RxD2 RESO Vss P90/TxD0 P91/TxD1 P92/RxD0 P93/RxD1 P94/SCK0/ IRQ4 P95/SCK1/ IRQ5 P40/D0 P41/D1 H8/3002 VCC PB0/TP8/TIOC A3 PB1/TP9/TIOC B3 PB2/TP10/ TIOCA4 PB3/TP11/ TIOCB4 PB4/TP12/ TOCXA4 PB5/TP13/ TOCXB4 PB6/TP14/ DREQ0 PB7/TP16/ DREQ1/ ADTRG RESO Vss P90/TxD0 P91/TxD1 P92/RxD0 P93/RxD1 P94/SCK0/ IRQ4 P95/SCK1/ IRQ5 P40/D0 P41/D1 4 5 6 7 8 PB6/TP14 9 PB7/TP15 10 11 12 13 14 15 16 17 18 19 RESO/ FWE*1 Vss P90/TxD0 P91/TxD1 P92/RxD0 P93/RxD1 P94/SCK0/ IRQ4 P95/SCK1/ IRQ5 P40/D0 P41/D1 Rev. 2.0, 06/04, page 976 of 980 ROMless Version H8/3069R, Pin No. H8/3029 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 P42/D2 P43/D3 Vss P44/D4 P45/D5 P46/D6 P47/D7 P30/D8 P31/D9 P32/D10 P33/D11 P34/D12 P35/D13 P36/D14 P37/D15 Vcc P10/A0 P11/A1 P12/A2 P13/A3 P14/A4 P15/A5 P16/A6 P17/A7 Vss P20/A8 P21/A9 P22/A10 P23/A11 P24/A12 P25/A13 P26/A14 P27/A15 P50/A16 P51/A17 P52/A18 P53/A19 H8/3067 Group P42/D2 P43/D3 Vss P44/D4 P45/D5 P46/D6 P47/D7 P30/D8 P31/D9 P32/D10 P33/D11 P34/D12 P35/D13 P36/D14 P37/D15 Vcc P10/A0 P11/A1 P12/A2 P13/A3 P14/A4 P15/A5 P16/A6 P17/A7 Vss P20/A8 P21/A9 P22/A10 P23/A11 P24/A12 P25/A13 P26/A14 P27/A15 P50/A16 P51/A17 P52/A18 P53/A19 H8/3062 Group P42/D2 P43/D3 Vss P44/D4 P45/D5 P46/D6 P47/D7 P30/D8 P31/D9 P32/D10 P33/D11 P34/D12 P35/D13 P36/D14 P37/D15 Vcc P10/A0 P11/A1 P12/A2 P13/A3 P14/A4 P15/A5 P16/A6 P17/A7 Vss P20/A8 P21/A9 P22/A10 P23/A11 P24/A12 P25/A13 P26/A14 P27/A15 P50/A16 P51/A17 P52/A18 P53/A19 H8/3048 Group P42/D2 P43/D3 Vss P44/D4 P45/D5 P46/D6 P47/D7 P30/D8 P31/D9 P32/D10 P33/D11 P34/D12 P35/D13 P36/D14 P37/D15 Vcc P10/A0 P11/A1 P12/A2 P13/A3 P14/A4 P15/A5 P16/A6 P17/A7 Vss P20/A8 P21/A9 P22/A10 P23/A11 P24/A12 P25/A13 P26/A14 P27/A15 P50/A16 P51/A17 P52/A18 P53/A19 H8/3042 Group P42/D2 P43/D3 Vss P44/D4 P45/D5 P46/D6 P47/D7 P30/D8 P31/D9 P32/D10 P33/D11 P34/D12 P35/D13 P36/D14 P37/D15 Vcc P10/A0 P11/A1 P12/A2 P13/A3 P14/A4 P15/A5 P16/A6 P17/A7 Vss P20/A8 P21/A9 P22/A10 P23/A11 P24/A12 P25/A13 P26/A14 P27/A15 P50/A16 P51/A17 P52/A18 P53/A19 H8/3007, H8/3006 P42/D2 P43/D3 Vss P44/D4 P45/D5 P46/D6 P47/D7 D8 D9 D10 D11 D12 D13 D14 D15 Vcc A0 A1 A2 A3 A4 A5 A6 A7 Vss A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 H8/3002 P42/D2 P43/D3 Vss P44/D4 P45/D5 P46/D6 P47/D7 D8 D9 D10 D11 D12 D13 D14 D15 Vcc A0 A1 A2 A3 A4 A5 A6 A7 Vss A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 Rev. 2.0, 06/04, page 977 of 980 ROMless Version H8/3069R, Pin No. H8/3029 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 Vss P60/WAIT P61/BREQ P62/BACK P67/ STBY RES NMI Vss EXTAL XTAL Vcc P63/AS P64/RD P65/HWR P66/LWR MD0 MD1 MD2 AVcc VREF P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 AVss P80/RFSH/ IRQ0 H8/3067 Group Vss P60/WAIT P61/BREQ P62/BACK P67/ STBY RES NMI Vss EXTAL XTAL Vcc P63/AS P64/RD P65/HWR P66/LWR MD0 MD1 MD2 AVcc VREF P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 AVss P80/RFSH/ IRQ0 H8/3062 Group Vss P60/WAIT P61/BREQ P62/BACK P67/ STBY RES NMI Vss EXTAL XTAL Vcc P63/AS P64/RD P65/HWR P66/LWR MD0 MD1 MD2 AVcc VREF P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 AVss P80/IRQ0 H8/3048 Group Vss P60/WAIT P61/BREQ P62/BACK STBY RES NMI Vss EXTAL XTAL Vcc P63/AS P64/RD P65/HWR P66/LWR MD0 MD1 MD2 AVcc VREF P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 AVss P80/RFSH/ IRQ0 H8/3042 Group Vss P60/WAIT P61/BREQ P62/BACK STBY RES NMI Vss EXTAL XTAL Vcc P63/AS P64/RD P65/HWR P66/LWR MD0 MD1 MD2 AVcc VREF P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 AVss P80/RFSH/ IRQ0 H8/3007, H8/3006 Vss P60/WAIT P61/BREQ P62/BACK P67/ STBY RES NMI Vss EXTAL XTAL Vcc AS RD HWR LWR MD0 MD1 MD2 AVcc VREF P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7 AVss P80/RFSH/ IRQ0 H8/3002 Vss P60/WAIT P61/BREQ P62/BACK STBY RES NMI NMI EXTAL XTAL Vcc AS RD HWR LWR MD0 MD1 MD2 AVcc VREF P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 AVss P80/RFSH/ IRQ0 P81/CS3/IRQ1 P81/CS3/IRQ1 P81/CS3/IRQ1 P81/CS3/IRQ1 P81/CS3/IRQ1 P81/CS3/IRQ1 P81/CS3/IRQ1 P82/CS2/IRQ2 P82/CS2/IRQ2 P82/CS2/IRQ2 P82/CS2/IRQ2 P82/CS2/IRQ2 P82/CS2/IRQ2 P82/CS2/IRQ2 P83/CS1/IRQ3/ P83/CS1/IRQ3/ P83/CS1/IRQ3/ P83/CS1/IRQ3 P83/CS1/IRQ3 P83/CS1/IRQ3/ P83/CS1/IRQ3 ADTRG ADTRG ADTRG ADTRG P84/CS0 P84/CS0 P84/CS0 P84/CS0 P84/CS0 P84/CS0 P84/CS0 Rev. 2.0, 06/04, page 978 of 980 ROMless Version H8/3069R, Pin No. H8/3029 92 93 Vss PA0/TP0/ TEND0/ TCLKA 94 PA1/TP1/ TEND1/ TCLKB PA2/TP2/ TIOCA0/ TCLKC PA3/TP3/ TIOCB0/ TCLKD PA4/TP4/ TIOCA1/ A23 PA5/TP5/ TIOCB1/ A22 PA6/TP6/ TIOCA2/ A21 PA7/TP7/ TIOCB2/A20 H8/3067 Group Vss PA0/TP0/ TEND0/ TCLKA PA1/TP1/ TEND1/ TCLKB PA2/TP2/ TIOCA0/ TCLKC PA3/TP3/ TIOCB0/ TCLKD PA4/TP4/ TIOCA1/ A23 PA5/TP5/ TIOCB1/ A22 PA6/TP6/ TIOCA2/ A21 PA7/TP7/ TIOCB2/A20 H8/3062 Group Vss PA0/TP0/ TCLKA H8/3048 Group Vss PA0/TP0/ TEND0/ TCLKA PA1/TP1/ TEND1/ TCLKB PA2/TP2/ TIOCA0/ TCLKC PA3/TP3/ TIOCB0/ TCLKD PA4/TP4/ TIOCA1/ CS6/A23 PA5/TP5/ TIOCB1/ CS5/A22 PA6/TP6/ TIOCA2/ CS4/A21 PA7/TP7/ TIOCB2/A20 H8/3042 Group Vss PA0/TP0/ TEND0/ TCLKA PA1/TP1/ TEND1/ TCLKB PA2/TP2/ TIOCA0/ TCLKC PA3/TP3/ TIOCB0/ TCLKD PA4/TP4/ TIOCA1/ A23 PA5/TP5/ TIOCB1/ A22 PA6/TP6/ TIOCA2/ A21 PA7/TP7/ TIOCB2/A20 H8/3007, H8/3006 Vss PA0/TP0/ TEND0/ TCLKA PA1/TP1/ TEND1/ TCLKB PA2/TP2/ TIOCA0/ TCLKC PA3/TP3/ TIOCB0/ TCLKD PA4/TP4/ TIOCA1/ A23 PA5/TP5/ TIOCB1/ A22 PA6/TP6/ TIOCA2/ A21 PA7/TP7/ TIOCB2/A20 H8/3002 Vss PA0/TP0/ TEND0/ TCLKA PA1/TP1/ TEND1/ TCLKB PA2/TP2/ TIOCA0/ TCLKC PA3/TP3/ TIOCB0/ TCLKD PA4/TP4/ TIOCA1/ A23 PA5/TP5/ TIOCB1/ A22 PA6/TP6/ TIOCA2/ A21 PA7/TP7/ TIOCB2/A20 PA1/TP1/ TCLKB PA2/TP2/ TIOCA0/ TCLKC PA3/TP3/ TIOCB0/ TCLKD PA4/TP4/ TIOCA1/ A23 PA5/TP5/ TIOCB1/ A22 PA6/TP6/ TIOCA2/ A21 PA7/TP7/ TIOCB2/A20 95 96 97 98 99 100 Notes: *1 Functions as RESO in the mask ROM versions, and as FWE in the flash memory and flash memory R versions. *2 Functions as the VCL pin in the 5-V products of the H8/3064F-ZTAT and H8/3062FZTAT B-mask versions, and requires an external capacitor (0.1 F). Rev. 2.0, 06/04, page 979 of 980 Rev. 2.0, 06/04, page 980 of 980 Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8/3029F-ZTATTM Publication Date: Rev.1.00, August 25, 2003 Rev.2.00, June 10, 2004 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Technical Documentation & Information Department Renesas Kodaira Semiconductor Co., Ltd. 2004. Renesas Technology Corp., All rights reserved. Printed in Japan. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501 Renesas Technology Europe Limited. Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900 Renesas Technology Europe GmbH Dornacher Str. 3, D-85622 Feldkirchen, Germany Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11 Renesas Technology Hong Kong Ltd. 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2375-6836 Renesas Technology Taiwan Co., Ltd. FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. 26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 http://www.renesas.com Colophon 1.0 H8/3029F-ZTAT Hardware Manual TM 2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan |
Price & Availability of H83029
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |